diff --git a/.gitattributes b/.gitattributes index 9aa5ca482f9e756d8b5bbf0819d286fab089ff2a..2a1691a3b2247a75f0e5a824c0993775952b3573 100644 --- a/.gitattributes +++ b/.gitattributes @@ -128,3 +128,9 @@ hardware/tools/avr/avr/bin/objdump.exe filter=lfs diff=lfs merge=lfs -text hardware/tools/avr/avr/bin/ranlib.exe filter=lfs diff=lfs merge=lfs -text hardware/tools/avr/avr/bin/readelf.exe filter=lfs diff=lfs merge=lfs -text hardware/tools/avr/avr/bin/strip.exe filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr25/libc.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr25/tiny-stack/libc.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr3/libc.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr31/libc.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr35/libc.a filter=lfs diff=lfs merge=lfs -text +hardware/tools/avr/avr/lib/avr4/libc.a filter=lfs diff=lfs merge=lfs -text diff --git a/hardware/tools/avr/avr/include/avr/iotn5.h b/hardware/tools/avr/avr/include/avr/iotn5.h new file mode 100644 index 0000000000000000000000000000000000000000..f6be1ccc9cfc4f3633850a739a722dfb3ef62776 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn5.h @@ -0,0 +1,512 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn5.h 2063 2009-11-18 22:06:28Z arcanum $ */ + +/* avr/iotn5.h - definitions for ATtiny5 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn5.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny5_H_ +#define _AVR_ATtiny5_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x00) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x01) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x02) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x03) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x0C) +#define BBMB 1 + +#define PCMSK _SFR_IO8(0x10) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define DIDR0 _SFR_IO8(0x17) +#define ADC0D 0 +#define AIN0D 0 +#define ADC1D 1 +#define AIN1D 1 +#define ADC2D 2 +#define ADC3D 3 + +#define ADCL _SFR_IO8(0x19) +#define ADC0 0 +#define ADC1 1 +#define ADC2 2 +#define ADC3 3 +#define ADC4 4 +#define ADC5 5 +#define ADC6 6 +#define ADC7 7 + +#define ADMUX _SFR_IO8(0x1B) +#define MUX0 0 +#define MUX1 1 + +#define ADCSRB _SFR_IO8(0x1C) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 + +#define ADCSRA _SFR_IO8(0x1D) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ACSR _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACD 7 + +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0_0 0 +#define ICR0_1 1 +#define ICR0_2 2 +#define ICR0_3 3 +#define ICR0_4 4 +#define ICR0_5 5 +#define ICR0_6 6 +#define ICR0_7 7 + +#define ICR0H _SFR_IO8(0x23) +#define ICR0_8 0 +#define ICR0_9 1 +#define ICR0_10 2 +#define ICR0_11 3 +#define ICR0_12 4 +#define ICR0_13 5 +#define ICR0_14 6 +#define ICR0_15 7 + +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define OCR0BH _SFR_IO8(0x25) +#define OCR0B8 0 +#define OCR0B9 1 +#define OCR0B10 2 +#define OCR0B11 3 +#define OCR0B12 4 +#define OCR0B13 5 +#define OCR0B14 6 +#define OCR0B15 7 + +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0AH _SFR_IO8(0x27) +#define OCR0A8 0 +#define OCR0A9 1 +#define OCR0A10 2 +#define OCR0A11 3 +#define OCR0A12 4 +#define OCR0A13 5 +#define OCR0A14 6 +#define OCR0A15 7 + +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCNT0H _SFR_IO8(0x29) +#define TCNT0_8 0 +#define TCNT0_9 1 +#define TCNT0_10 2 +#define TCNT0_11 3 +#define TCNT0_12 4 +#define TCNT0_13 5 +#define TCNT0_14 6 +#define TCNT0_15 7 + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define TSM 7 + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 + +#define __AVR_HAVE_PRR ((1< instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn804.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY804_H_INCLUDED +#define _AVR_ATTINY804_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x25 + + +#endif /* #ifdef _AVR_ATTINY804_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn806.h b/hardware/tools/avr/avr/include/avr/iotn806.h new file mode 100644 index 0000000000000000000000000000000000000000..bb1f7352bf6c5c5169b1beb8b6bf738092bbc996 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn806.h @@ -0,0 +1,4640 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn806.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY806_H_INCLUDED +#define _AVR_ATTINY806_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x24 + + +#endif /* #ifdef _AVR_ATTINY806_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn807.h b/hardware/tools/avr/avr/include/avr/iotn807.h new file mode 100644 index 0000000000000000000000000000000000000000..a17da4de5d291fdfd93e757b3fe0578f3e05070b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn807.h @@ -0,0 +1,4640 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn807.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY807_H_INCLUDED +#define _AVR_ATTINY807_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Positive Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Positive Pin 3 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor/DAC1 */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ + ADC_REFSEL_VREFA_gc = (0x02<<4), /* External reference */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + BOD_SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[51]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[7]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t reserved_1[6]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t reserved_2[7]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t ASYNCUSER11; /* Asynchronous User Ch 11 Input Selection - TCB1 */ + register8_t ASYNCUSER12; /* Asynchronous User Ch 12 Input Selection - ADC1 */ + register8_t reserved_3[3]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ + EVSYS_ASYNCCH0_AC1_OUT_gc = (0x13<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH0_AC2_OUT_gc = (0x14<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ + EVSYS_ASYNCCH1_AC1_OUT_gc = (0x12<<0), /* Analog Comparator 1 out */ + EVSYS_ASYNCCH1_AC2_OUT_gc = (0x13<<0), /* Analog Comparator 2 out */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 11 Input Selection - TCB1 select */ +typedef enum EVSYS_ASYNCUSER11_enum +{ + EVSYS_ASYNCUSER11_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER11_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER11_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER11_t; + +/* Asynchronous User Ch 12 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER12_enum +{ + EVSYS_ASYNCUSER12_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER12_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER12_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER12_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ + EVSYS_SYNCCH0_TCB1_gc = (0x15<<0), /* Timer/Counter B1 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous User Ch 0 - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[2]; + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125HZ_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[2]; +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0680) /* Analog Comparator */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_ASYNCUSER11 _SFR_MEM8(0x019D) +#define EVSYS_ASYNCUSER12 _SFR_MEM8(0x019E) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0680) +#define AC0_MUXCTRLA _SFR_MEM8(0x0682) +#define AC0_INTCTRL _SFR_MEM8(0x0686) +#define AC0_STATUS _SFR_MEM8(0x0687) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_gm 0x18 /* Positive Input MUX Selection group mask. */ +#define AC_MUXPOS_gp 3 /* Positive Input MUX Selection group position. */ +#define AC_MUXPOS0_bm (1<<3) /* Positive Input MUX Selection bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* Positive Input MUX Selection bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* Positive Input MUX Selection bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* Positive Input MUX Selection bit 1 position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.ASYNCUSER11 bit masks and bit positions */ +#define EVSYS_ASYNCUSER11_gm 0xFF /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */ +#define EVSYS_ASYNCUSER11_gp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */ +#define EVSYS_ASYNCUSER110_bm (1<<0) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */ +#define EVSYS_ASYNCUSER110_bp 0 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */ +#define EVSYS_ASYNCUSER111_bm (1<<1) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */ +#define EVSYS_ASYNCUSER111_bp 1 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */ +#define EVSYS_ASYNCUSER112_bm (1<<2) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */ +#define EVSYS_ASYNCUSER112_bp 2 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */ +#define EVSYS_ASYNCUSER113_bm (1<<3) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */ +#define EVSYS_ASYNCUSER113_bp 3 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */ +#define EVSYS_ASYNCUSER114_bm (1<<4) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */ +#define EVSYS_ASYNCUSER114_bp 4 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */ +#define EVSYS_ASYNCUSER115_bm (1<<5) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */ +#define EVSYS_ASYNCUSER115_bp 5 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */ +#define EVSYS_ASYNCUSER116_bm (1<<6) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */ +#define EVSYS_ASYNCUSER116_bp 6 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */ +#define EVSYS_ASYNCUSER117_bm (1<<7) /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */ +#define EVSYS_ASYNCUSER117_bp 7 /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */ + +/* EVSYS.ASYNCUSER12 bit masks and bit positions */ +#define EVSYS_ASYNCUSER12_gm 0xFF /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER12_gp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER120_bm (1<<0) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER120_bp 0 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER121_bm (1<<1) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER121_bp 1 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER122_bm (1<<2) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER122_bp 2 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER123_bm (1<<3) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER123_bp 3 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER124_bm (1<<4) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER124_bp 4 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER125_bm (1<<5) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER125_bp 5 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER126_bm (1<<6) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER126_bp 6 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER127_bm (1<<7) /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER127_bp 7 /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ +#define USART_ABMBP_bm 0x80 /* Autobaud majority voter bypass bit mask. */ +#define USART_ABMBP_bp 7 /* Autobaud majority voter bypass bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 17 +#define AC0_AC_vect _VECTOR(17) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 20 +#define ADC0_RESRDY_vect _VECTOR(20) /* */ +#define ADC0_WCOMP_vect_num 21 +#define ADC0_WCOMP_vect _VECTOR(21) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 24 +#define TWI0_TWIS_vect _VECTOR(24) /* */ +#define TWI0_TWIM_vect_num 25 +#define TWI0_TWIM_vect _VECTOR(25) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 26 +#define SPI0_INT_vect _VECTOR(26) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 27 +#define USART0_RXC_vect _VECTOR(27) /* */ +#define USART0_DRE_vect_num 28 +#define USART0_DRE_vect _VECTOR(28) /* */ +#define USART0_TXC_vect_num 29 +#define USART0_TXC_vect _VECTOR(29) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 30 +#define NVMCTRL_EE_vect _VECTOR(30) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (31 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 Reserved */ + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x23 + + +#endif /* #ifdef _AVR_ATTINY807_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn814.h b/hardware/tools/avr/avr/include/avr/iotn814.h new file mode 100644 index 0000000000000000000000000000000000000000..471ecb488cc063b4642bbfdc26f40ff3130c310c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn814.h @@ -0,0 +1,5266 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn814.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY814_H_INCLUDED +#define _AVR_ATTINY814_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ + BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ + BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ + BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_bm 0x08 /* Positive Input MUX Selection bit mask. */ +#define AC_MUXPOS_bp 3 /* Positive Input MUX Selection bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x22 + + +#endif /* #ifdef _AVR_ATTINY814_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn816.h b/hardware/tools/avr/avr/include/avr/iotn816.h new file mode 100644 index 0000000000000000000000000000000000000000..64cc6996f32e56cb23c4a6d076e40765f9e5c52b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn816.h @@ -0,0 +1,5292 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn816.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY816_H_INCLUDED +#define _AVR_ATTINY816_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ + BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ + BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ + BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_bm 0x08 /* Positive Input MUX Selection bit mask. */ +#define AC_MUXPOS_bp 3 /* Positive Input MUX Selection bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x21 + + +#endif /* #ifdef _AVR_ATTINY816_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn817.h b/hardware/tools/avr/avr/include/avr/iotn817.h new file mode 100644 index 0000000000000000000000000000000000000000..4c14d09a95bfa438a97a6d02196c0a9925074876 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn817.h @@ -0,0 +1,5292 @@ +/***************************************************************************** + * + * Copyright (C) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn817.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATTINY817_H_INCLUDED +#define _AVR_ATTINY817_H_INCLUDED + +/* Ungrouped common registers */ +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +#define GPIOR0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x001C) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x001D) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x001E) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x001F) /* General Purpose IO Register 3 */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t MUXCTRLA; /* Mux Control A */ + register8_t reserved_2[3]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Hysteresis Mode select */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_OFF_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_10mV_gc = (0x01<<1), /* 10mV hysteresis */ + AC_HYSMODE_25mV_gc = (0x02<<1), /* 25mV hysteresis */ + AC_HYSMODE_50mV_gc = (0x03<<1), /* 50mV hysteresis */ +} AC_HYSMODE_t; + +/* Interrupt Mode select */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGE_gc = (0x00<<4), /* Any Edge */ + AC_INTMODE_NEGEDGE_gc = (0x02<<4), /* Negative Edge */ + AC_INTMODE_POSEDGE_gc = (0x03<<4), /* Positive Edge */ +} AC_INTMODE_t; + +/* Low Power Mode select */ +typedef enum AC_LPMODE_enum +{ + AC_LPMODE_DIS_gc = (0x00<<3), /* Low power mode disabled */ + AC_LPMODE_EN_gc = (0x01<<3), /* Low power mode enabled */ +} AC_LPMODE_t; + +/* Negative Input MUX Selection select */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Negative Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Negative Pin 1 */ + AC_MUXNEG_VREF_gc = (0x02<<0), /* Voltage Reference */ + AC_MUXNEG_DAC_gc = (0x03<<0), /* DAC output */ +} AC_MUXNEG_t; + +/* Positive Input MUX Selection select */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Positive Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Positive Pin 1 */ +} AC_MUXPOS_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog to Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog to Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t SAMPCTRL; /* Sample Control */ + register8_t MUXPOS; /* Positive mux input */ + register8_t reserved_1[1]; + register8_t COMMAND; /* Command */ + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Data */ + register8_t reserved_2[2]; + _WORDREGISTER(RES); /* ADC Accumulator Result */ + _WORDREGISTER(WINLT); /* Window comparator low threshold */ + _WORDREGISTER(WINHT); /* Window comparator high threshold */ + register8_t CALIB; /* Calibration */ + register8_t reserved_3[1]; +} ADC_t; + +/* Automatic Sampling Delay Variation select */ +typedef enum ADC_ASDV_enum +{ + ADC_ASDV_ASVOFF_gc = (0x00<<4), /* The Automatic Sampling Delay Variation is disabled */ + ADC_ASDV_ASVON_gc = (0x01<<4), /* The Automatic Sampling Delay Variation is enabled */ +} ADC_ASDV_t; + +/* Duty Cycle select */ +typedef enum ADC_DUTYCYC_enum +{ + ADC_DUTYCYC_DUTY50_gc = (0x00<<0), /* 50% Duty cycle */ + ADC_DUTYCYC_DUTY25_gc = (0x01<<0), /* 25% Duty cycle */ +} ADC_DUTYCYC_t; + +/* Initial Delay Selection select */ +typedef enum ADC_INITDLY_enum +{ + ADC_INITDLY_DLY0_gc = (0x00<<5), /* Delay 0 CLK_ADC cycles */ + ADC_INITDLY_DLY16_gc = (0x01<<5), /* Delay 16 CLK_ADC cycles */ + ADC_INITDLY_DLY32_gc = (0x02<<5), /* Delay 32 CLK_ADC cycles */ + ADC_INITDLY_DLY64_gc = (0x03<<5), /* Delay 64 CLK_ADC cycles */ + ADC_INITDLY_DLY128_gc = (0x04<<5), /* Delay 128 CLK_ADC cycles */ + ADC_INITDLY_DLY256_gc = (0x05<<5), /* Delay 256 CLK_ADC cycles */ +} ADC_INITDLY_t; + +/* Analog Channel Selection Bits select */ +typedef enum ADC_MUXPOS_enum +{ + ADC_MUXPOS_AIN0_gc = (0x00<<0), /* ADC input pin 0 */ + ADC_MUXPOS_AIN1_gc = (0x01<<0), /* ADC input pin 1 */ + ADC_MUXPOS_AIN2_gc = (0x02<<0), /* ADC input pin 2 */ + ADC_MUXPOS_AIN3_gc = (0x03<<0), /* ADC input pin 3 */ + ADC_MUXPOS_AIN4_gc = (0x04<<0), /* ADC input pin 4 */ + ADC_MUXPOS_AIN5_gc = (0x05<<0), /* ADC input pin 5 */ + ADC_MUXPOS_AIN6_gc = (0x06<<0), /* ADC input pin 6 */ + ADC_MUXPOS_AIN7_gc = (0x07<<0), /* ADC input pin 7 */ + ADC_MUXPOS_AIN8_gc = (0x08<<0), /* ADC input pin 8 */ + ADC_MUXPOS_AIN9_gc = (0x09<<0), /* ADC input pin 9 */ + ADC_MUXPOS_AIN10_gc = (0x0A<<0), /* ADC input pin 10 */ + ADC_MUXPOS_AIN11_gc = (0x0B<<0), /* ADC input pin 11 */ + ADC_MUXPOS_DAC0_gc = (0x1C<<0), /* DAC0 */ + ADC_MUXPOS_INTREF_gc = (0x1D<<0), /* Internal Ref */ + ADC_MUXPOS_TEMPSENSE_gc = (0x1E<<0), /* Temp sensor */ + ADC_MUXPOS_GND_gc = (0x1F<<0), /* GND */ +} ADC_MUXPOS_t; + +/* Clock Pre-scaler select */ +typedef enum ADC_PRESC_enum +{ + ADC_PRESC_DIV2_gc = (0x00<<0), /* CLK_PER divided by 2 */ + ADC_PRESC_DIV4_gc = (0x01<<0), /* CLK_PER divided by 4 */ + ADC_PRESC_DIV8_gc = (0x02<<0), /* CLK_PER divided by 8 */ + ADC_PRESC_DIV16_gc = (0x03<<0), /* CLK_PER divided by 16 */ + ADC_PRESC_DIV32_gc = (0x04<<0), /* CLK_PER divided by 32 */ + ADC_PRESC_DIV64_gc = (0x05<<0), /* CLK_PER divided by 64 */ + ADC_PRESC_DIV128_gc = (0x06<<0), /* CLK_PER divided by 128 */ + ADC_PRESC_DIV256_gc = (0x07<<0), /* CLK_PER divided by 256 */ +} ADC_PRESC_t; + +/* Reference Selection select */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INTREF_gc = (0x00<<4), /* Internal reference */ + ADC_REFSEL_VDDREF_gc = (0x01<<4), /* VDD */ +} ADC_REFSEL_t; + +/* ADC Resolution select */ +typedef enum ADC_RESSEL_enum +{ + ADC_RESSEL_10BIT_gc = (0x00<<2), /* 10-bit mode */ + ADC_RESSEL_8BIT_gc = (0x01<<2), /* 8-bit mode */ +} ADC_RESSEL_t; + +/* Accumulation Samples select */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_ACC1_gc = (0x00<<0), /* 1 ADC sample */ + ADC_SAMPNUM_ACC2_gc = (0x01<<0), /* Accumulate 2 samples */ + ADC_SAMPNUM_ACC4_gc = (0x02<<0), /* Accumulate 4 samples */ + ADC_SAMPNUM_ACC8_gc = (0x03<<0), /* Accumulate 8 samples */ + ADC_SAMPNUM_ACC16_gc = (0x04<<0), /* Accumulate 16 samples */ + ADC_SAMPNUM_ACC32_gc = (0x05<<0), /* Accumulate 32 samples */ + ADC_SAMPNUM_ACC64_gc = (0x06<<0), /* Accumulate 64 samples */ +} ADC_SAMPNUM_t; + +/* Window Comparator Mode select */ +typedef enum ADC_WINCM_enum +{ + ADC_WINCM_NONE_gc = (0x00<<0), /* No Window Comparison */ + ADC_WINCM_BELOW_gc = (0x01<<0), /* Below Window */ + ADC_WINCM_ABOVE_gc = (0x02<<0), /* Above Window */ + ADC_WINCM_INSIDE_gc = (0x03<<0), /* Inside Window */ + ADC_WINCM_OUTSIDE_gc = (0x04<<0), /* Outside Window */ +} ADC_WINCM_t; + +/* +-------------------------------------------------------------------------- +BOD - Bod interface +-------------------------------------------------------------------------- +*/ + +/* Bod interface */ +typedef struct BOD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t reserved_1[6]; + register8_t VLMCTRLA; /* Voltage level monitor Control */ + register8_t INTCTRL; /* Voltage level monitor interrupt Control */ + register8_t INTFLAGS; /* Voltage level monitor interrupt Flags */ + register8_t STATUS; /* Voltage level monitor status */ + register8_t reserved_2[4]; +} BOD_t; + +/* Operation in active mode select */ +typedef enum BOD_ACTIVE_enum +{ + BOD_ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + BOD_ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + BOD_ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + BOD_ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wakeup halt */ +} BOD_ACTIVE_t; + +/* Bod level select */ +typedef enum BOD_LVL_enum +{ + BOD_LVL_BODLEVEL0_gc = (0x00<<0), /* 1.8 V */ + BOD_LVL_BODLEVEL1_gc = (0x01<<0), /* 2.1 V */ + BOD_LVL_BODLEVEL2_gc = (0x02<<0), /* 2.6 V */ + BOD_LVL_BODLEVEL3_gc = (0x03<<0), /* 2.9 V */ + BOD_LVL_BODLEVEL4_gc = (0x04<<0), /* 3.3 V */ + BOD_LVL_BODLEVEL5_gc = (0x05<<0), /* 3.7 V */ + BOD_LVL_BODLEVEL6_gc = (0x06<<0), /* 4.0 V */ + BOD_LVL_BODLEVEL7_gc = (0x07<<0), /* 4.2 V */ +} BOD_LVL_t; + +/* Sample frequency select */ +typedef enum BOD_SAMPFREQ_enum +{ + BOD_SAMPFREQ_1KHZ_gc = (0x00<<4), /* 1kHz sampling */ + BOD_SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling */ +} BOD_SAMPFREQ_t; + +/* Operation in sleep mode select */ +typedef enum BOD_SLEEP_enum +{ + BOD_SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + BOD_SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + BOD_SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} BOD_SLEEP_t; + +/* Configuration select */ +typedef enum BOD_VLMCFG_enum +{ + BOD_VLMCFG_BELOW_gc = (0x00<<1), /* Interrupt when supply goes below VLM level */ + BOD_VLMCFG_ABOVE_gc = (0x01<<1), /* Interrupt when supply goes above VLM level */ + BOD_VLMCFG_CROSS_gc = (0x02<<1), /* Interrupt when supply crosses VLM level */ +} BOD_VLMCFG_t; + +/* voltage level monitor level select */ +typedef enum BOD_VLMLVL_enum +{ + BOD_VLMLVL_5ABOVE_gc = (0x00<<0), /* VLM threshold 5% above BOD level */ + BOD_VLMLVL_15ABOVE_gc = (0x01<<0), /* VLM threshold 15% above BOD level */ + BOD_VLMLVL_25ABOVE_gc = (0x02<<0), /* VLM threshold 25% above BOD level */ +} BOD_VLMLVL_t; + +/* +-------------------------------------------------------------------------- +CCL - Configurable Custom Logic +-------------------------------------------------------------------------- +*/ + +/* Configurable Custom Logic */ +typedef struct CCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t SEQCTRL0; /* Sequential Control 0 */ + register8_t reserved_1[3]; + register8_t LUT0CTRLA; /* LUT Control 0 A */ + register8_t LUT0CTRLB; /* LUT Control 0 B */ + register8_t LUT0CTRLC; /* LUT Control 0 C */ + register8_t TRUTH0; /* Truth 0 */ + register8_t LUT1CTRLA; /* LUT Control 1 A */ + register8_t LUT1CTRLB; /* LUT Control 1 B */ + register8_t LUT1CTRLC; /* LUT Control 1 C */ + register8_t TRUTH1; /* Truth 1 */ + register8_t reserved_2[3]; +} CCL_t; + +/* Edge Detection Enable select */ +typedef enum CCL_EDGEDET_enum +{ + CCL_EDGEDET_DIS_gc = (0x00<<7), /* Edge detector is disabled */ + CCL_EDGEDET_EN_gc = (0x01<<7), /* Edge detector is enabled */ +} CCL_EDGEDET_t; + +/* Filter Selection select */ +typedef enum CCL_FILTSEL_enum +{ + CCL_FILTSEL_DISABLE_gc = (0x00<<4), /* Filter disabled */ + CCL_FILTSEL_SYNCH_gc = (0x01<<4), /* Synchronizer enabled */ + CCL_FILTSEL_FILTER_gc = (0x02<<4), /* Filter enabled */ +} CCL_FILTSEL_t; + +/* LUT Input 0 Source Selection select */ +typedef enum CCL_INSEL0_enum +{ + CCL_INSEL0_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL0_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL0_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL0_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL0_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL0_IO_gc = (0x05<<0), /* IO pin LUTn-IN0 input source */ + CCL_INSEL0_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL0_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL0_TCA0_gc = (0x08<<0), /* TCA0 WO0 input source */ + CCL_INSEL0_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL0_USART0_gc = (0x0A<<0), /* USART0 XCK input source */ + CCL_INSEL0_SPI0_gc = (0x0B<<0), /* SPI0 SCK source */ +} CCL_INSEL0_t; + +/* LUT Input 1 Source Selection select */ +typedef enum CCL_INSEL1_enum +{ + CCL_INSEL1_MASK_gc = (0x00<<4), /* Masked input */ + CCL_INSEL1_FEEDBACK_gc = (0x01<<4), /* Feedback input source */ + CCL_INSEL1_LINK_gc = (0x02<<4), /* Linked LUT input source */ + CCL_INSEL1_EVENT0_gc = (0x03<<4), /* Event input source 0 */ + CCL_INSEL1_EVENT1_gc = (0x04<<4), /* Event input source 1 */ + CCL_INSEL1_IO_gc = (0x05<<4), /* IO pin LUTn-N1 input source */ + CCL_INSEL1_AC0_gc = (0x06<<4), /* AC0 OUT input source */ + CCL_INSEL1_TCB0_gc = (0x07<<4), /* TCB0 WO input source */ + CCL_INSEL1_TCA0_gc = (0x08<<4), /* TCA0 WO1 input source */ + CCL_INSEL1_TCD0_gc = (0x09<<4), /* TCD0 WOB input source */ + CCL_INSEL1_USART0_gc = (0x0A<<4), /* USART0 TXD input source */ + CCL_INSEL1_SPI0_gc = (0x0B<<4), /* SPI0 MOSI input source */ +} CCL_INSEL1_t; + +/* LUT Input 2 Source Selection select */ +typedef enum CCL_INSEL2_enum +{ + CCL_INSEL2_MASK_gc = (0x00<<0), /* Masked input */ + CCL_INSEL2_FEEDBACK_gc = (0x01<<0), /* Feedback input source */ + CCL_INSEL2_LINK_gc = (0x02<<0), /* Linked LUT input source */ + CCL_INSEL2_EVENT0_gc = (0x03<<0), /* Event input source 0 */ + CCL_INSEL2_EVENT1_gc = (0x04<<0), /* Event input source 1 */ + CCL_INSEL2_IO_gc = (0x05<<0), /* IO pin LUTn-IN2 input source */ + CCL_INSEL2_AC0_gc = (0x06<<0), /* AC0 OUT input source */ + CCL_INSEL2_TCB0_gc = (0x07<<0), /* TCB0 WO input source */ + CCL_INSEL2_TCA0_gc = (0x08<<0), /* TCA0 WO2 input source */ + CCL_INSEL2_TCD0_gc = (0x09<<0), /* TCD0 WOA input source */ + CCL_INSEL2_SPI0_gc = (0x0B<<0), /* SPI0 MISO source */ +} CCL_INSEL2_t; + +/* Sequential Selection select */ +typedef enum CCL_SEQSEL_enum +{ + CCL_SEQSEL_DISABLE_gc = (0x00<<0), /* Sequential logic disabled */ + CCL_SEQSEL_DFF_gc = (0x01<<0), /* D FlipFlop */ + CCL_SEQSEL_JK_gc = (0x02<<0), /* JK FlipFlop */ + CCL_SEQSEL_LATCH_gc = (0x03<<0), /* D Latch */ + CCL_SEQSEL_RS_gc = (0x04<<0), /* RS Latch */ +} CCL_SEQSEL_t; + +/* +-------------------------------------------------------------------------- +CLKCTRL - Clock controller +-------------------------------------------------------------------------- +*/ + +/* Clock controller */ +typedef struct CLKCTRL_struct +{ + register8_t MCLKCTRLA; /* MCLK Control A */ + register8_t MCLKCTRLB; /* MCLK Control B */ + register8_t MCLKLOCK; /* MCLK Lock */ + register8_t MCLKSTATUS; /* MCLK Status */ + register8_t reserved_1[12]; + register8_t OSC20MCTRLA; /* OSC20M Control A */ + register8_t OSC20MCALIBA; /* OSC20M Calibration A */ + register8_t OSC20MCALIBB; /* OSC20M Calibration B */ + register8_t reserved_2[5]; + register8_t OSC32KCTRLA; /* OSC32K Control A */ + register8_t reserved_3[3]; + register8_t XOSC32KCTRLA; /* XOSC32K Control A */ + register8_t reserved_4[3]; +} CLKCTRL_t; + +/* clock select select */ +typedef enum CLKCTRL_CLKSEL_enum +{ + CLKCTRL_CLKSEL_OSC20M_gc = (0x00<<0), /* 20MHz internal oscillator */ + CLKCTRL_CLKSEL_OSCULP32K_gc = (0x01<<0), /* 32KHz internal Ultra Low Power oscillator */ + CLKCTRL_CLKSEL_XOSC32K_gc = (0x02<<0), /* 32.768kHz external crystal oscillator */ + CLKCTRL_CLKSEL_EXTCLK_gc = (0x03<<0), /* External clock */ +} CLKCTRL_CLKSEL_t; + +/* Crystal startup time select */ +typedef enum CLKCTRL_CSUT_enum +{ + CLKCTRL_CSUT_1K_gc = (0x00<<4), /* 1K cycles */ + CLKCTRL_CSUT_16K_gc = (0x01<<4), /* 16K cycles */ + CLKCTRL_CSUT_32K_gc = (0x02<<4), /* 32K cycles */ + CLKCTRL_CSUT_64K_gc = (0x03<<4), /* 64K cycles */ +} CLKCTRL_CSUT_t; + +/* Prescaler division select */ +typedef enum CLKCTRL_PDIV_enum +{ + CLKCTRL_PDIV_2X_gc = (0x00<<1), /* 2X */ + CLKCTRL_PDIV_4X_gc = (0x01<<1), /* 4X */ + CLKCTRL_PDIV_8X_gc = (0x02<<1), /* 8X */ + CLKCTRL_PDIV_16X_gc = (0x03<<1), /* 16X */ + CLKCTRL_PDIV_32X_gc = (0x04<<1), /* 32X */ + CLKCTRL_PDIV_64X_gc = (0x05<<1), /* 64X */ + CLKCTRL_PDIV_6X_gc = (0x08<<1), /* 6X */ + CLKCTRL_PDIV_10X_gc = (0x09<<1), /* 10X */ + CLKCTRL_PDIV_12X_gc = (0x0A<<1), /* 12X */ + CLKCTRL_PDIV_24X_gc = (0x0B<<1), /* 24X */ + CLKCTRL_PDIV_48X_gc = (0x0C<<1), /* 48X */ +} CLKCTRL_PDIV_t; + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signature select */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + +/* +-------------------------------------------------------------------------- +CPUINT - Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Interrupt Controller */ +typedef struct CPUINT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t LVL0PRI; /* Interrupt Level 0 Priority */ + register8_t LVL1VEC; /* Interrupt Level 1 Priority Vector */ +} CPUINT_t; + + +/* +-------------------------------------------------------------------------- +CRCSCAN - CRCSCAN +-------------------------------------------------------------------------- +*/ + +/* CRCSCAN */ +typedef struct CRCSCAN_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t reserved_1[1]; +} CRCSCAN_t; + +/* CRC Flash Access Mode select */ +typedef enum CRCSCAN_MODE_enum +{ + CRCSCAN_MODE_PRIORITY_gc = (0x00<<4), /* Priority to flash */ + CRCSCAN_MODE_RESERVED_gc = (0x01<<4), /* Reserved */ + CRCSCAN_MODE_BACKGROUND_gc = (0x02<<4), /* Lowest priority to flash */ + CRCSCAN_MODE_CONTINUOUS_gc = (0x03<<4), /* Continuous checks in background */ +} CRCSCAN_MODE_t; + +/* CRC Source select */ +typedef enum CRCSCAN_SRC_enum +{ + CRCSCAN_SRC_FLASH_gc = (0x00<<0), /* CRC on entire flash */ + CRCSCAN_SRC_APPLICATION_gc = (0x01<<0), /* CRC on boot and appl section of flash */ + CRCSCAN_SRC_BOOT_gc = (0x02<<0), /* CRC on boot section of flash */ +} CRCSCAN_SRC_t; + +/* +-------------------------------------------------------------------------- +DAC - Digital to Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital to Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t DATA; /* DATA Register */ + register8_t reserved_1[2]; +} DAC_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t ASYNCSTROBE; /* Asynchronous Channel Strobe */ + register8_t SYNCSTROBE; /* Synchronous Channel Strobe */ + register8_t ASYNCCH0; /* Asynchronous Channel 0 Generator Selection */ + register8_t ASYNCCH1; /* Asynchronous Channel 1 Generator Selection */ + register8_t ASYNCCH2; /* Asynchronous Channel 2 Generator Selection */ + register8_t ASYNCCH3; /* Asynchronous Channel 3 Generator Selection */ + register8_t reserved_1[4]; + register8_t SYNCCH0; /* Synchronous Channel 0 Generator Selection */ + register8_t SYNCCH1; /* Synchronous Channel 1 Generator Selection */ + register8_t reserved_2[6]; + register8_t ASYNCUSER0; /* Asynchronous User Ch 0 Input Selection - TCB0 */ + register8_t ASYNCUSER1; /* Asynchronous User Ch 1 Input Selection - ADC0 */ + register8_t ASYNCUSER2; /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 */ + register8_t ASYNCUSER3; /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 */ + register8_t ASYNCUSER4; /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 */ + register8_t ASYNCUSER5; /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 */ + register8_t ASYNCUSER6; /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 */ + register8_t ASYNCUSER7; /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 */ + register8_t ASYNCUSER8; /* Asynchronous User Ch 8 Input Selection - Event Out 0 */ + register8_t ASYNCUSER9; /* Asynchronous User Ch 9 Input Selection - Event Out 1 */ + register8_t ASYNCUSER10; /* Asynchronous User Ch 10 Input Selection - Event Out 2 */ + register8_t reserved_3[5]; + register8_t SYNCUSER0; /* Synchronous User Ch 0 Input Selection - TCA0 */ + register8_t SYNCUSER1; /* Synchronous User Ch 1 Input Selection - USART0 */ + register8_t reserved_4[28]; +} EVSYS_t; + +/* Asynchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_ASYNCCH0_enum +{ + EVSYS_ASYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH0_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH0_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH0_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH0_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH0_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH0_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH0_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH0_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH0_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH0_PORTA_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PA0 */ + EVSYS_ASYNCCH0_PORTA_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PA1 */ + EVSYS_ASYNCCH0_PORTA_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PA2 */ + EVSYS_ASYNCCH0_PORTA_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PA3 */ + EVSYS_ASYNCCH0_PORTA_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PA4 */ + EVSYS_ASYNCCH0_PORTA_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PA5 */ + EVSYS_ASYNCCH0_PORTA_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PA6 */ + EVSYS_ASYNCCH0_PORTA_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PA7 */ + EVSYS_ASYNCCH0_UPDI_gc = (0x12<<0), /* Unified Program and debug interface */ +} EVSYS_ASYNCCH0_t; + +/* Asynchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_ASYNCCH1_enum +{ + EVSYS_ASYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH1_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH1_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH1_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH1_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH1_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH1_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH1_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH1_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH1_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH1_PORTB_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PB0 */ + EVSYS_ASYNCCH1_PORTB_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PB1 */ + EVSYS_ASYNCCH1_PORTB_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PB2 */ + EVSYS_ASYNCCH1_PORTB_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PB3 */ + EVSYS_ASYNCCH1_PORTB_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PB4 */ + EVSYS_ASYNCCH1_PORTB_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PB5 */ + EVSYS_ASYNCCH1_PORTB_PIN6_gc = (0x10<<0), /* Asynchronous Event from Pin PB6 */ + EVSYS_ASYNCCH1_PORTB_PIN7_gc = (0x11<<0), /* Asynchronous Event from Pin PB7 */ +} EVSYS_ASYNCCH1_t; + +/* Asynchronous Channel 2 Generator Selection select */ +typedef enum EVSYS_ASYNCCH2_enum +{ + EVSYS_ASYNCCH2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH2_CCL_LUT0_gc = (0x01<<0), /* Configurable Custom Logic LUT0 */ + EVSYS_ASYNCCH2_CCL_LUT1_gc = (0x02<<0), /* Configurable Custom Logic LUT1 */ + EVSYS_ASYNCCH2_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH2_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter D0 compare B clear */ + EVSYS_ASYNCCH2_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter D0 compare A set */ + EVSYS_ASYNCCH2_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter D0 compare B set */ + EVSYS_ASYNCCH2_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter D0 program event */ + EVSYS_ASYNCCH2_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH2_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH2_PORTC_PIN0_gc = (0x0A<<0), /* Asynchronous Event from Pin PC0 */ + EVSYS_ASYNCCH2_PORTC_PIN1_gc = (0x0B<<0), /* Asynchronous Event from Pin PC1 */ + EVSYS_ASYNCCH2_PORTC_PIN2_gc = (0x0C<<0), /* Asynchronous Event from Pin PC2 */ + EVSYS_ASYNCCH2_PORTC_PIN3_gc = (0x0D<<0), /* Asynchronous Event from Pin PC3 */ + EVSYS_ASYNCCH2_PORTC_PIN4_gc = (0x0E<<0), /* Asynchronous Event from Pin PC4 */ + EVSYS_ASYNCCH2_PORTC_PIN5_gc = (0x0F<<0), /* Asynchronous Event from Pin PC5 */ +} EVSYS_ASYNCCH2_t; + +/* Asynchronous Channel 3 Generator Selection select */ +typedef enum EVSYS_ASYNCCH3_enum +{ + EVSYS_ASYNCCH3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCCH3_CCL_LUT0_gc = (0x01<<0), /* Configurable custom logic LUT0 */ + EVSYS_ASYNCCH3_CCL_LUT1_gc = (0x02<<0), /* Configurable custom logic LUT1 */ + EVSYS_ASYNCCH3_AC0_OUT_gc = (0x03<<0), /* Analog Comparator 0 out */ + EVSYS_ASYNCCH3_TCD0_CMPBCLR_gc = (0x04<<0), /* Timer/Counter type D compare B clear */ + EVSYS_ASYNCCH3_TCD0_CMPASET_gc = (0x05<<0), /* Timer/Counter type D compare A set */ + EVSYS_ASYNCCH3_TCD0_CMPBSET_gc = (0x06<<0), /* Timer/Counter type D compare B set */ + EVSYS_ASYNCCH3_TCD0_PROGEV_gc = (0x07<<0), /* Timer/Counter type D program event */ + EVSYS_ASYNCCH3_RTC_OVF_gc = (0x08<<0), /* Real Time Counter overflow */ + EVSYS_ASYNCCH3_RTC_CMP_gc = (0x09<<0), /* Real Time Counter compare */ + EVSYS_ASYNCCH3_PIT_DIV8192_gc = (0x0A<<0), /* Periodic Interrupt CLK_RTC div 8192 */ + EVSYS_ASYNCCH3_PIT_DIV4096_gc = (0x0B<<0), /* Periodic Interrupt CLK_RTC div 4096 */ + EVSYS_ASYNCCH3_PIT_DIV2048_gc = (0x0C<<0), /* Periodic Interrupt CLK_RTC div 2048 */ + EVSYS_ASYNCCH3_PIT_DIV1024_gc = (0x0D<<0), /* Periodic Interrupt CLK_RTC div 1024 */ + EVSYS_ASYNCCH3_PIT_DIV512_gc = (0x0E<<0), /* Periodic Interrupt CLK_RTC div 512 */ + EVSYS_ASYNCCH3_PIT_DIV256_gc = (0x0F<<0), /* Periodic Interrupt CLK_RTC div 256 */ + EVSYS_ASYNCCH3_PIT_DIV128_gc = (0x10<<0), /* Periodic Interrupt CLK_RTC div 128 */ + EVSYS_ASYNCCH3_PIT_DIV64_gc = (0x11<<0), /* Periodic Interrupt CLK_RTC div 64 */ +} EVSYS_ASYNCCH3_t; + +/* Asynchronous User Ch 0 Input Selection - TCB0 select */ +typedef enum EVSYS_ASYNCUSER0_enum +{ + EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER0_t; + +/* Asynchronous User Ch 1 Input Selection - ADC0 select */ +typedef enum EVSYS_ASYNCUSER1_enum +{ + EVSYS_ASYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER1_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER1_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER1_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER1_t; + +/* Asynchronous User Ch 10 Input Selection - Event Out 2 select */ +typedef enum EVSYS_ASYNCUSER10_enum +{ + EVSYS_ASYNCUSER10_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER10_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER10_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER10_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER10_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER10_t; + +/* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER2_enum +{ + EVSYS_ASYNCUSER2_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER2_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER2_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER2_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER2_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER2_t; + +/* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 select */ +typedef enum EVSYS_ASYNCUSER3_enum +{ + EVSYS_ASYNCUSER3_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER3_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER3_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER3_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER3_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER3_t; + +/* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER4_enum +{ + EVSYS_ASYNCUSER4_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER4_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER4_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER4_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER4_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER4_t; + +/* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 select */ +typedef enum EVSYS_ASYNCUSER5_enum +{ + EVSYS_ASYNCUSER5_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER5_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER5_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER5_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER5_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER5_t; + +/* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 select */ +typedef enum EVSYS_ASYNCUSER6_enum +{ + EVSYS_ASYNCUSER6_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER6_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER6_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER6_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER6_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER6_t; + +/* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 select */ +typedef enum EVSYS_ASYNCUSER7_enum +{ + EVSYS_ASYNCUSER7_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER7_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER7_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER7_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER7_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER7_t; + +/* Asynchronous User Ch 8 Input Selection - Event Out 0 select */ +typedef enum EVSYS_ASYNCUSER8_enum +{ + EVSYS_ASYNCUSER8_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER8_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER8_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER8_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER8_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER8_t; + +/* Asynchronous User Ch 9 Input Selection - Event Out 1 select */ +typedef enum EVSYS_ASYNCUSER9_enum +{ + EVSYS_ASYNCUSER9_OFF_gc = (0x00<<0), /* Off */ + EVSYS_ASYNCUSER9_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH0_gc = (0x03<<0), /* Asynchronous Event Channel 0 */ + EVSYS_ASYNCUSER9_ASYNCCH1_gc = (0x04<<0), /* Asynchronous Event Channel 1 */ + EVSYS_ASYNCUSER9_ASYNCCH2_gc = (0x05<<0), /* Asynchronous Event Channel 2 */ + EVSYS_ASYNCUSER9_ASYNCCH3_gc = (0x06<<0), /* Asynchronous Event Channel 3 */ +} EVSYS_ASYNCUSER9_t; + +/* Synchronous Channel 0 Generator Selection select */ +typedef enum EVSYS_SYNCCH0_enum +{ + EVSYS_SYNCCH0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH0_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH0_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH0_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH0_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH0_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH0_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH0_PORTC_PIN0_gc = (0x07<<0), /* Synchronous Event from Pin PC0 */ + EVSYS_SYNCCH0_PORTC_PIN1_gc = (0x08<<0), /* Synchronous Event from Pin PC1 */ + EVSYS_SYNCCH0_PORTC_PIN2_gc = (0x09<<0), /* Synchronous Event from Pin PC2 */ + EVSYS_SYNCCH0_PORTC_PIN3_gc = (0x0A<<0), /* Synchronous Event from Pin PC3 */ + EVSYS_SYNCCH0_PORTC_PIN4_gc = (0x0B<<0), /* Synchronous Event from Pin PC4 */ + EVSYS_SYNCCH0_PORTC_PIN5_gc = (0x0C<<0), /* Synchronous Event from Pin PC5 */ + EVSYS_SYNCCH0_PORTA_PIN0_gc = (0x0D<<0), /* Synchronous Event from Pin PA0 */ + EVSYS_SYNCCH0_PORTA_PIN1_gc = (0x0E<<0), /* Synchronous Event from Pin PA1 */ + EVSYS_SYNCCH0_PORTA_PIN2_gc = (0x0F<<0), /* Synchronous Event from Pin PA2 */ + EVSYS_SYNCCH0_PORTA_PIN3_gc = (0x10<<0), /* Synchronous Event from Pin PA3 */ + EVSYS_SYNCCH0_PORTA_PIN4_gc = (0x11<<0), /* Synchronous Event from Pin PA4 */ + EVSYS_SYNCCH0_PORTA_PIN5_gc = (0x12<<0), /* Synchronous Event from Pin PA5 */ + EVSYS_SYNCCH0_PORTA_PIN6_gc = (0x13<<0), /* Synchronous Event from Pin PA6 */ + EVSYS_SYNCCH0_PORTA_PIN7_gc = (0x14<<0), /* Synchronous Event from Pin PA7 */ +} EVSYS_SYNCCH0_t; + +/* Synchronous Channel 1 Generator Selection select */ +typedef enum EVSYS_SYNCCH1_enum +{ + EVSYS_SYNCCH1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCCH1_TCB0_gc = (0x01<<0), /* Timer/Counter B0 */ + EVSYS_SYNCCH1_TCA0_OVF_LUNF_gc = (0x02<<0), /* Timer/Counter A0 overflow */ + EVSYS_SYNCCH1_TCA0_HUNF_gc = (0x03<<0), /* Timer/Counter A0 underflow high byte (split mode) */ + EVSYS_SYNCCH1_TCA0_CMP0_gc = (0x04<<0), /* Timer/Counter A0 compare 0 */ + EVSYS_SYNCCH1_TCA0_CMP1_gc = (0x05<<0), /* Timer/Counter A0 compare 1 */ + EVSYS_SYNCCH1_TCA0_CMP2_gc = (0x06<<0), /* Timer/Counter A0 compare 2 */ + EVSYS_SYNCCH1_PORTB_PIN0_gc = (0x08<<0), /* Synchronous Event from Pin PB0 */ + EVSYS_SYNCCH1_PORTB_PIN1_gc = (0x09<<0), /* Synchronous Event from Pin PB1 */ + EVSYS_SYNCCH1_PORTB_PIN2_gc = (0x0A<<0), /* Synchronous Event from Pin PB2 */ + EVSYS_SYNCCH1_PORTB_PIN3_gc = (0x0B<<0), /* Synchronous Event from Pin PB3 */ + EVSYS_SYNCCH1_PORTB_PIN4_gc = (0x0C<<0), /* Synchronous Event from Pin PB4 */ + EVSYS_SYNCCH1_PORTB_PIN5_gc = (0x0D<<0), /* Synchronous Event from Pin PB5 */ + EVSYS_SYNCCH1_PORTB_PIN6_gc = (0x0E<<0), /* Synchronous Event from Pin PB6 */ + EVSYS_SYNCCH1_PORTB_PIN7_gc = (0x0F<<0), /* Synchronous Event from Pin PB7 */ +} EVSYS_SYNCCH1_t; + +/* Synchronous User Ch 0 Input Selection - TCA0 select */ +typedef enum EVSYS_SYNCUSER0_enum +{ + EVSYS_SYNCUSER0_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER0_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER0_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER0_t; + +/* Synchronous User Ch 1 Input Selection - USART0 select */ +typedef enum EVSYS_SYNCUSER1_enum +{ + EVSYS_SYNCUSER1_OFF_gc = (0x00<<0), /* Off */ + EVSYS_SYNCUSER1_SYNCCH0_gc = (0x01<<0), /* Synchronous Event Channel 0 */ + EVSYS_SYNCUSER1_SYNCCH1_gc = (0x02<<0), /* Synchronous Event Channel 1 */ +} EVSYS_SYNCUSER1_t; + +/* +-------------------------------------------------------------------------- +FUSE - Fuses +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct FUSE_struct +{ + register8_t WDTCFG; /* Watchdog Configuration */ + register8_t BODCFG; /* BOD Configuration */ + register8_t OSCCFG; /* Oscillator Configuration */ + register8_t reserved_1[1]; + register8_t TCD0CFG; /* TCD0 Configuration */ + register8_t SYSCFG0; /* System Configuration 0 */ + register8_t SYSCFG1; /* System Configuration 1 */ + register8_t APPEND; /* Application Code Section End */ + register8_t BOOTEND; /* Boot Section End */ +} FUSE_t; + + +/* avr-libc typedef for avr/fuse.h */ +typedef FUSE_t NVM_FUSES_t; + +/* BOD Operation in Active Mode select */ +typedef enum ACTIVE_enum +{ + ACTIVE_DIS_gc = (0x00<<2), /* Disabled */ + ACTIVE_ENABLED_gc = (0x01<<2), /* Enabled */ + ACTIVE_SAMPLED_gc = (0x02<<2), /* Sampled */ + ACTIVE_ENWAKE_gc = (0x03<<2), /* Enabled with wake-up halted until BOD is ready */ +} ACTIVE_t; + +/* CRC Source select */ +typedef enum CRCSRC_enum +{ + CRCSRC_FLASH_gc = (0x00<<6), /* The CRC is performed on the entire Flash (boot, application code and application data section). */ + CRCSRC_BOOT_gc = (0x01<<6), /* The CRC is performed on the boot section of Flash */ + CRCSRC_BOOTAPP_gc = (0x02<<6), /* The CRC is performed on the boot and application code section of Flash */ + CRCSRC_NOCRC_gc = (0x03<<6), /* Disable CRC. */ +} CRCSRC_t; + +/* Frequency Select select */ +typedef enum FREQSEL_enum +{ + FREQSEL_16MHZ_gc = (0x01<<0), /* 16 MHz */ + FREQSEL_20MHZ_gc = (0x02<<0), /* 20 MHz */ +} FREQSEL_t; + +/* BOD Level select */ +typedef enum LVL_enum +{ + LVL_BODLEVEL0_gc = (0x00<<5), /* 1.8 V */ + LVL_BODLEVEL2_gc = (0x02<<5), /* 2.6 V */ + LVL_BODLEVEL7_gc = (0x07<<5), /* 4.2 V */ +} LVL_t; + +/* Watchdog Timeout Period select */ +typedef enum PERIOD_enum +{ + PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} PERIOD_t; + +/* Reset Pin Configuration select */ +typedef enum RSTPINCFG_enum +{ + RSTPINCFG_GPIO_gc = (0x00<<2), /* GPIO mode */ + RSTPINCFG_UPDI_gc = (0x01<<2), /* UPDI mode */ + RSTPINCFG_RST_gc = (0x02<<2), /* Reset mode */ +} RSTPINCFG_t; + +/* BOD Sample Frequency select */ +typedef enum SAMPFREQ_enum +{ + SAMPFREQ_1KHz_gc = (0x00<<4), /* 1kHz sampling frequency */ + SAMPFREQ_125Hz_gc = (0x01<<4), /* 125Hz sampling frequency */ +} SAMPFREQ_t; + +/* BOD Operation in Sleep Mode select */ +typedef enum SLEEP_enum +{ + SLEEP_DIS_gc = (0x00<<0), /* Disabled */ + SLEEP_ENABLED_gc = (0x01<<0), /* Enabled */ + SLEEP_SAMPLED_gc = (0x02<<0), /* Sampled */ +} SLEEP_t; + +/* Startup Time select */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x00<<0), /* 0 ms */ + SUT_1MS_gc = (0x01<<0), /* 1 ms */ + SUT_2MS_gc = (0x02<<0), /* 2 ms */ + SUT_4MS_gc = (0x03<<0), /* 4 ms */ + SUT_8MS_gc = (0x04<<0), /* 8 ms */ + SUT_16MS_gc = (0x05<<0), /* 16 ms */ + SUT_32MS_gc = (0x06<<0), /* 32 ms */ + SUT_64MS_gc = (0x07<<0), /* 64 ms */ +} SUT_t; + +/* Watchdog Window Timeout Period select */ +typedef enum WINDOW_enum +{ + WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WINDOW_t; + +/* +-------------------------------------------------------------------------- +LOCKBIT - Lockbit +-------------------------------------------------------------------------- +*/ + +/* Lockbit */ +typedef struct LOCKBIT_struct +{ + register8_t LOCKBIT; /* Lock bits */ +} LOCKBIT_t; + +/* Lock Bits select */ +typedef enum LB_enum +{ + LB_RWLOCK_gc = (0x3A<<0), /* Read and write lock */ + LB_NOLOCK_gc = (0xC5<<0), /* No locks */ +} LB_t; + +/* +-------------------------------------------------------------------------- +NVMCTRL - Non-volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVMCTRL_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[1]; + _WORDREGISTER(DATA); /* Data */ + _WORDREGISTER(ADDR); /* Address */ + register8_t reserved_2[6]; +} NVMCTRL_t; + +/* Command select */ +typedef enum NVMCTRL_CMD_enum +{ + NVMCTRL_CMD_NONE_gc = (0x00<<0), /* No Command */ + NVMCTRL_CMD_PAGEWRITE_gc = (0x01<<0), /* Write page */ + NVMCTRL_CMD_PAGEERASE_gc = (0x02<<0), /* Erase page */ + NVMCTRL_CMD_PAGEERASEWRITE_gc = (0x03<<0), /* Erase and write page */ + NVMCTRL_CMD_PAGEBUFCLR_gc = (0x04<<0), /* Page buffer clear */ + NVMCTRL_CMD_CHIPERASE_gc = (0x05<<0), /* Chip erase */ + NVMCTRL_CMD_EEERASE_gc = (0x06<<0), /* EEPROM erase */ + NVMCTRL_CMD_FUSEWRITE_gc = (0x07<<0), /* Write fuse (PDI only) */ +} NVMCTRL_CMD_t; + +/* +-------------------------------------------------------------------------- +PORT - I/O Ports +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t DIRSET; /* Data Direction Set */ + register8_t DIRCLR; /* Data Direction Clear */ + register8_t DIRTGL; /* Data Direction Toggle */ + register8_t OUT; /* Output Value */ + register8_t OUTSET; /* Output Value Set */ + register8_t OUTCLR; /* Output Value Clear */ + register8_t OUTTGL; /* Output Value Toggle */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_1[6]; + register8_t PIN0CTRL; /* Pin 0 Control */ + register8_t PIN1CTRL; /* Pin 1 Control */ + register8_t PIN2CTRL; /* Pin 2 Control */ + register8_t PIN3CTRL; /* Pin 3 Control */ + register8_t PIN4CTRL; /* Pin 4 Control */ + register8_t PIN5CTRL; /* Pin 5 Control */ + register8_t PIN6CTRL; /* Pin 6 Control */ + register8_t PIN7CTRL; /* Pin 7 Control */ + register8_t reserved_2[8]; +} PORT_t; + +/* Input/Sense Configuration select */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_INTDISABLE_gc = (0x00<<0), /* Interrupt disabled but input buffer enabled */ + PORT_ISC_BOTHEDGES_gc = (0x01<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x02<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x03<<0), /* Sense Falling Edge */ + PORT_ISC_INPUT_DISABLE_gc = (0x04<<0), /* Digital Input Buffer disabled */ + PORT_ISC_LEVEL_gc = (0x05<<0), /* Sense low Level */ +} PORT_ISC_t; + +/* +-------------------------------------------------------------------------- +PORTMUX - Port Multiplexer +-------------------------------------------------------------------------- +*/ + +/* Port Multiplexer */ +typedef struct PORTMUX_struct +{ + register8_t CTRLA; /* Port Multiplexer Control A */ + register8_t CTRLB; /* Port Multiplexer Control B */ + register8_t CTRLC; /* Port Multiplexer Control C */ + register8_t CTRLD; /* Port Multiplexer Control D */ + register8_t reserved_1[12]; +} PORTMUX_t; + +/* Configurable Custom Logic LUT0 select */ +typedef enum PORTMUX_LUT0_enum +{ + PORTMUX_LUT0_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_LUT0_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_LUT0_t; + +/* Configurable Custom Logic LUT1 select */ +typedef enum PORTMUX_LUT1_enum +{ + PORTMUX_LUT1_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_LUT1_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_LUT1_t; + +/* Port Multiplexer SPI0 select */ +typedef enum PORTMUX_SPI0_enum +{ + PORTMUX_SPI0_DEFAULT_gc = (0x00<<2), /* Default pins */ + PORTMUX_SPI0_ALTERNATE_gc = (0x01<<2), /* Alternate pins */ +} PORTMUX_SPI0_t; + +/* Port Multiplexer TCA0 Output 0 select */ +typedef enum PORTMUX_TCA00_enum +{ + PORTMUX_TCA00_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCA00_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCA00_t; + +/* Port Multiplexer TCA0 Output 1 select */ +typedef enum PORTMUX_TCA01_enum +{ + PORTMUX_TCA01_DEFAULT_gc = (0x00<<1), /* Default pin */ + PORTMUX_TCA01_ALTERNATE_gc = (0x01<<1), /* Alternate pin */ +} PORTMUX_TCA01_t; + +/* Port Multiplexer TCA0 Output 2 select */ +typedef enum PORTMUX_TCA02_enum +{ + PORTMUX_TCA02_DEFAULT_gc = (0x00<<2), /* Default pin */ + PORTMUX_TCA02_ALTERNATE_gc = (0x01<<2), /* Alternate pin */ +} PORTMUX_TCA02_t; + +/* Port Multiplexer TCA0 Output 3 select */ +typedef enum PORTMUX_TCA03_enum +{ + PORTMUX_TCA03_DEFAULT_gc = (0x00<<3), /* Default pin */ + PORTMUX_TCA03_ALTERNATE_gc = (0x01<<3), /* Alternate pin */ +} PORTMUX_TCA03_t; + +/* Port Multiplexer TCA0 Output 4 select */ +typedef enum PORTMUX_TCA04_enum +{ + PORTMUX_TCA04_DEFAULT_gc = (0x00<<4), /* Default pin */ + PORTMUX_TCA04_ALTERNATE_gc = (0x01<<4), /* Alternate pin */ +} PORTMUX_TCA04_t; + +/* Port Multiplexer TCA0 Output 5 select */ +typedef enum PORTMUX_TCA05_enum +{ + PORTMUX_TCA05_DEFAULT_gc = (0x00<<5), /* Default pin */ + PORTMUX_TCA05_ALTERNATE_gc = (0x01<<5), /* Alternate pin */ +} PORTMUX_TCA05_t; + +/* Port Multiplexer TCB select */ +typedef enum PORTMUX_TCB0_enum +{ + PORTMUX_TCB0_DEFAULT_gc = (0x00<<0), /* Default pin */ + PORTMUX_TCB0_ALTERNATE_gc = (0x01<<0), /* Alternate pin */ +} PORTMUX_TCB0_t; + +/* Port Multiplexer TWI0 select */ +typedef enum PORTMUX_TWI0_enum +{ + PORTMUX_TWI0_DEFAULT_gc = (0x00<<4), /* Default pins */ + PORTMUX_TWI0_ALTERNATE_gc = (0x01<<4), /* Alternate pins */ +} PORTMUX_TWI0_t; + +/* Port Multiplexer USART0 select */ +typedef enum PORTMUX_USART0_enum +{ + PORTMUX_USART0_DEFAULT_gc = (0x00<<0), /* Default pins */ + PORTMUX_USART0_ALTERNATE_gc = (0x01<<0), /* Alternate pins */ +} PORTMUX_USART0_t; + +/* +-------------------------------------------------------------------------- +RSTCTRL - Reset controller +-------------------------------------------------------------------------- +*/ + +/* Reset controller */ +typedef struct RSTCTRL_struct +{ + register8_t RSTFR; /* Reset Flags */ + register8_t SWRR; /* Software Reset */ + register8_t reserved_1[2]; +} RSTCTRL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary */ + register8_t DBGCTRL; /* Debug control */ + register8_t reserved_1[1]; + register8_t CLKSEL; /* Clock Select */ + _WORDREGISTER(CNT); /* Counter */ + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP); /* Compare */ + register8_t reserved_2[2]; + register8_t PITCTRLA; /* PIT Control A */ + register8_t PITSTATUS; /* PIT Status */ + register8_t PITINTCTRL; /* PIT Interrupt Control */ + register8_t PITINTFLAGS; /* PIT Interrupt Flags */ + register8_t reserved_3[1]; + register8_t PITDBGCTRL; /* PIT Debug control */ + register8_t reserved_4[10]; +} RTC_t; + +/* Clock Select select */ +typedef enum RTC_CLKSEL_enum +{ + RTC_CLKSEL_INT32K_gc = (0x00<<0), /* Internal 32kHz OSC */ + RTC_CLKSEL_INT1K_gc = (0x01<<0), /* Internal 1kHz OSC */ + RTC_CLKSEL_TOSC32K_gc = (0x02<<0), /* 32KHz Crystal OSC */ + RTC_CLKSEL_EXTCLK_gc = (0x03<<0), /* External Clock */ +} RTC_CLKSEL_t; + +/* Period select */ +typedef enum RTC_PERIOD_enum +{ + RTC_PERIOD_OFF_gc = (0x00<<3), /* Off */ + RTC_PERIOD_CYC4_gc = (0x01<<3), /* RTC Clock Cycles 4 */ + RTC_PERIOD_CYC8_gc = (0x02<<3), /* RTC Clock Cycles 8 */ + RTC_PERIOD_CYC16_gc = (0x03<<3), /* RTC Clock Cycles 16 */ + RTC_PERIOD_CYC32_gc = (0x04<<3), /* RTC Clock Cycles 32 */ + RTC_PERIOD_CYC64_gc = (0x05<<3), /* RTC Clock Cycles 64 */ + RTC_PERIOD_CYC128_gc = (0x06<<3), /* RTC Clock Cycles 128 */ + RTC_PERIOD_CYC256_gc = (0x07<<3), /* RTC Clock Cycles 256 */ + RTC_PERIOD_CYC512_gc = (0x08<<3), /* RTC Clock Cycles 512 */ + RTC_PERIOD_CYC1024_gc = (0x09<<3), /* RTC Clock Cycles 1024 */ + RTC_PERIOD_CYC2048_gc = (0x0A<<3), /* RTC Clock Cycles 2048 */ + RTC_PERIOD_CYC4096_gc = (0x0B<<3), /* RTC Clock Cycles 4096 */ + RTC_PERIOD_CYC8192_gc = (0x0C<<3), /* RTC Clock Cycles 8192 */ + RTC_PERIOD_CYC16384_gc = (0x0D<<3), /* RTC Clock Cycles 16384 */ + RTC_PERIOD_CYC32768_gc = (0x0E<<3), /* RTC Clock Cycles 32768 */ +} RTC_PERIOD_t; + +/* Prescaling Factor select */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_DIV1_gc = (0x00<<3), /* RTC Clock / 1 */ + RTC_PRESCALER_DIV2_gc = (0x01<<3), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV4_gc = (0x02<<3), /* RTC Clock / 4 */ + RTC_PRESCALER_DIV8_gc = (0x03<<3), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<3), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV32_gc = (0x05<<3), /* RTC Clock / 32 */ + RTC_PRESCALER_DIV64_gc = (0x06<<3), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV128_gc = (0x07<<3), /* RTC Clock / 128 */ + RTC_PRESCALER_DIV256_gc = (0x08<<3), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV512_gc = (0x09<<3), /* RTC Clock / 512 */ + RTC_PRESCALER_DIV1024_gc = (0x0A<<3), /* RTC Clock / 1024 */ + RTC_PRESCALER_DIV2048_gc = (0x0B<<3), /* RTC Clock / 2048 */ + RTC_PRESCALER_DIV4096_gc = (0x0C<<3), /* RTC Clock / 4096 */ + RTC_PRESCALER_DIV8192_gc = (0x0D<<3), /* RTC Clock / 8192 */ + RTC_PRESCALER_DIV16384_gc = (0x0E<<3), /* RTC Clock / 16384 */ + RTC_PRESCALER_DIV32768_gc = (0x0F<<3), /* RTC Clock / 32768 */ +} RTC_PRESCALER_t; + +/* +-------------------------------------------------------------------------- +SIGROW - Signature row +-------------------------------------------------------------------------- +*/ + +/* Signature row */ +typedef struct SIGROW_struct +{ + register8_t DEVICEID0; /* Device ID Byte 0 */ + register8_t DEVICEID1; /* Device ID Byte 1 */ + register8_t DEVICEID2; /* Device ID Byte 2 */ + register8_t SERNUM0; /* Serial Number Byte 0 */ + register8_t SERNUM1; /* Serial Number Byte 1 */ + register8_t SERNUM2; /* Serial Number Byte 2 */ + register8_t SERNUM3; /* Serial Number Byte 3 */ + register8_t SERNUM4; /* Serial Number Byte 4 */ + register8_t SERNUM5; /* Serial Number Byte 5 */ + register8_t SERNUM6; /* Serial Number Byte 6 */ + register8_t SERNUM7; /* Serial Number Byte 7 */ + register8_t SERNUM8; /* Serial Number Byte 8 */ + register8_t SERNUM9; /* Serial Number Byte 9 */ + register8_t reserved_1[19]; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t OSC16ERR3V; /* OSC16 error at 3V */ + register8_t OSC16ERR5V; /* OSC16 error at 5V */ + register8_t OSC20ERR3V; /* OSC20 error at 3V */ + register8_t OSC20ERR5V; /* OSC20 error at 5V */ + register8_t reserved_2[26]; +} SIGROW_t; + + +/* +-------------------------------------------------------------------------- +SLPCTRL - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLPCTRL_struct +{ + register8_t CTRLA; /* Control */ + register8_t reserved_1[1]; +} SLPCTRL_t; + +/* Sleep mode select */ +typedef enum SLPCTRL_SMODE_enum +{ + SLPCTRL_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLPCTRL_SMODE_STDBY_gc = (0x01<<1), /* Standby Mode */ + SLPCTRL_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +} SLPCTRL_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_STANDBY (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t DATA; /* Data */ + register8_t reserved_1[3]; +} SPI_t; + +/* SPI Mode select */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<0), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<0), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<0), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<0), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler select */ +typedef enum SPI_PRESC_enum +{ + SPI_PRESC_DIV4_gc = (0x00<<1), /* System Clock / 4 */ + SPI_PRESC_DIV16_gc = (0x01<<1), /* System Clock / 16 */ + SPI_PRESC_DIV64_gc = (0x02<<1), /* System Clock / 64 */ + SPI_PRESC_DIV128_gc = (0x03<<1), /* System Clock / 128 */ +} SPI_PRESC_t; + +/* +-------------------------------------------------------------------------- +SYSCFG - System Configuration Registers +-------------------------------------------------------------------------- +*/ + +/* System Configuration Registers */ +typedef struct SYSCFG_struct +{ + register8_t reserved_1[1]; + register8_t REVID; /* Revision ID */ + register8_t EXTBRK; /* External Break */ + register8_t reserved_2[29]; +} SYSCFG_t; + + +/* +-------------------------------------------------------------------------- +TCA - 16-bit Timer/Counter Type A +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter Type A - Single Mode */ +typedef struct TCA_SINGLE_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t CTRLFCLR; /* Control F Clear */ + register8_t CTRLFSET; /* Control F Set */ + register8_t reserved_1[1]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t TEMP; /* Temporary data for 16-bit Access */ + register8_t reserved_3[16]; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_4[4]; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CMP0); /* Compare 0 */ + _WORDREGISTER(CMP1); /* Compare 1 */ + _WORDREGISTER(CMP2); /* Compare 2 */ + register8_t reserved_5[8]; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ + _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ + _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ + register8_t reserved_6[2]; +} TCA_SINGLE_t; + + +/* 16-bit Timer/Counter Type A - Split Mode */ +typedef struct TCA_SPLIT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLECLR; /* Control E Clear */ + register8_t CTRLESET; /* Control E Set */ + register8_t reserved_1[4]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_2[2]; + register8_t DBGCTRL; /* Degbug Control */ + register8_t reserved_3[17]; + register8_t LCNT; /* Low Count */ + register8_t HCNT; /* High Count */ + register8_t reserved_4[4]; + register8_t LPER; /* Low Period */ + register8_t HPER; /* High Period */ + register8_t LCMP0; /* Low Compare */ + register8_t HCMP0; /* High Compare */ + register8_t LCMP1; /* Low Compare */ + register8_t HCMP1; /* High Compare */ + register8_t LCMP2; /* Low Compare */ + register8_t HCMP2; /* High Compare */ + register8_t reserved_5[18]; +} TCA_SPLIT_t; + + +/* 16-bit Timer/Counter Type A */ +typedef union TCA_union +{ + TCA_SINGLE_t SINGLE; /* 16-bit Timer/Counter Type A - Single Mode */ + TCA_SPLIT_t SPLIT; /* 16-bit Timer/Counter Type A - Split Mode */ +} TCA_t; + +/* Clock Selection select */ +typedef enum TCA_SINGLE_CLKSEL_enum +{ + TCA_SINGLE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SINGLE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SINGLE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SINGLE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SINGLE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SINGLE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SINGLE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SINGLE_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SINGLE_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SINGLE_CMD_enum +{ + TCA_SINGLE_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SINGLE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SINGLE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SINGLE_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SINGLE_CMD_t; + +/* Direction select */ +typedef enum TCA_SINGLE_DIR_enum +{ + TCA_SINGLE_DIR_UP_gc = (0x00<<0), /* Count up */ + TCA_SINGLE_DIR_DOWN_gc = (0x01<<0), /* Count down */ +} TCA_SINGLE_DIR_t; + +/* Event Action select */ +typedef enum TCA_SINGLE_EVACT_enum +{ + TCA_SINGLE_EVACT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ + TCA_SINGLE_EVACT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ + TCA_SINGLE_EVACT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ + TCA_SINGLE_EVACT_UPDOWN_gc = (0x03<<1), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ +} TCA_SINGLE_EVACT_t; + +/* Waveform generation mode select */ +typedef enum TCA_SINGLE_WGMODE_enum +{ + TCA_SINGLE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TCA_SINGLE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TCA_SINGLE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ + TCA_SINGLE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ + TCA_SINGLE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ + TCA_SINGLE_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope PWM, overflow on BOTTOM */ +} TCA_SINGLE_WGMODE_t; + +/* Clock Selection select */ +typedef enum TCA_SPLIT_CLKSEL_enum +{ + TCA_SPLIT_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ + TCA_SPLIT_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ + TCA_SPLIT_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ + TCA_SPLIT_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ + TCA_SPLIT_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ + TCA_SPLIT_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ + TCA_SPLIT_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ + TCA_SPLIT_CLKSEL_DIV1024_gc = (0x07<<1), /* System Clock / 1024 */ +} TCA_SPLIT_CLKSEL_t; + +/* Command select */ +typedef enum TCA_SPLIT_CMD_enum +{ + TCA_SPLIT_CMD_NONE_gc = (0x00<<2), /* No Command */ + TCA_SPLIT_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TCA_SPLIT_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TCA_SPLIT_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TCA_SPLIT_CMD_t; + +/* +-------------------------------------------------------------------------- +TCB - 16-bit Timer Type B +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer Type B */ +typedef struct TCB_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control Register B */ + register8_t reserved_1[2]; + register8_t EVCTRL; /* Event Control */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t DBGCTRL; /* Debug Control */ + register8_t TEMP; /* Temporary Value */ + _WORDREGISTER(CNT); /* Count */ + _WORDREGISTER(CCMP); /* Compare or Capture */ + register8_t reserved_2[2]; +} TCB_t; + +/* Clock Select select */ +typedef enum TCB_CLKSEL_enum +{ + TCB_CLKSEL_CLKDIV1_gc = (0x00<<1), /* CLK_PER (No Prescaling) */ + TCB_CLKSEL_CLKDIV2_gc = (0x01<<1), /* CLK_PER/2 (From Prescaler) */ + TCB_CLKSEL_CLKTCA_gc = (0x02<<1), /* Use Clock from TCA */ +} TCB_CLKSEL_t; + +/* Timer Mode select */ +typedef enum TCB_CNTMODE_enum +{ + TCB_CNTMODE_INT_gc = (0x00<<0), /* Periodic Interrupt */ + TCB_CNTMODE_TIMEOUT_gc = (0x01<<0), /* Periodic Timeout */ + TCB_CNTMODE_CAPT_gc = (0x02<<0), /* Input Capture Event */ + TCB_CNTMODE_FRQ_gc = (0x03<<0), /* Input Capture Frequency measurement */ + TCB_CNTMODE_PW_gc = (0x04<<0), /* Input Capture Pulse-Width measurement */ + TCB_CNTMODE_FRQPW_gc = (0x05<<0), /* Input Capture Frequency and Pulse-Width measurement */ + TCB_CNTMODE_SINGLE_gc = (0x06<<0), /* Single Shot */ + TCB_CNTMODE_PWM8_gc = (0x07<<0), /* 8-bit PWM */ +} TCB_CNTMODE_t; + +/* +-------------------------------------------------------------------------- +TCD - Timer Counter D +-------------------------------------------------------------------------- +*/ + +/* Timer Counter D */ +typedef struct TCD_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + register8_t CTRLD; /* Control D */ + register8_t CTRLE; /* Control E */ + register8_t reserved_1[3]; + register8_t EVCTRLA; /* EVCTRLA */ + register8_t EVCTRLB; /* EVCTRLB */ + register8_t reserved_2[2]; + register8_t INTCTRL; /* Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t STATUS; /* Status */ + register8_t reserved_3[1]; + register8_t INPUTCTRLA; /* Input Control A */ + register8_t INPUTCTRLB; /* Input Control B */ + register8_t FAULTCTRL; /* Fault Control */ + register8_t reserved_4[1]; + register8_t DLYCTRL; /* Delay Control */ + register8_t DLYVAL; /* Delay value */ + register8_t reserved_5[2]; + register8_t DITCTRL; /* Dither Control A */ + register8_t DITVAL; /* Dither value */ + register8_t reserved_6[4]; + register8_t DBGCTRL; /* Debug Control */ + register8_t reserved_7[3]; + _WORDREGISTER(CAPTUREA); /* Capture A */ + _WORDREGISTER(CAPTUREB); /* Capture B */ + register8_t reserved_8[2]; + _WORDREGISTER(CMPASET); /* Compare A Set */ + _WORDREGISTER(CMPACLR); /* Compare A Clear */ + _WORDREGISTER(CMPBSET); /* Compare B Set */ + _WORDREGISTER(CMPBCLR); /* Compare B Clear */ + register8_t reserved_9[16]; +} TCD_t; + +/* event action select */ +typedef enum TCD_ACTION_enum +{ + TCD_ACTION_FAULT_gc = (0x00<<2), /* Event trigger a fault */ + TCD_ACTION_CAPTURE_gc = (0x01<<2), /* Event trigger a fault and capture */ +} TCD_ACTION_t; + +/* event config select */ +typedef enum TCD_CFG_enum +{ + TCD_CFG_NEITHER_gc = (0x00<<6), /* Neither Filter nor Asynchronous Event is enabled */ + TCD_CFG_FILTER_gc = (0x01<<6), /* Input Capture Noise Cancellation Filter enabled */ + TCD_CFG_ASYNC_gc = (0x02<<6), /* Asynchronous Event output qualification enabled */ +} TCD_CFG_t; + +/* clock select select */ +typedef enum TCD_CLKSEL_enum +{ + TCD_CLKSEL_20MHZ_gc = (0x00<<5), /* 20 MHz oscillator */ + TCD_CLKSEL_EXTCLK_gc = (0x02<<5), /* External clock */ + TCD_CLKSEL_SYSCLK_gc = (0x03<<5), /* System clock */ +} TCD_CLKSEL_t; + +/* Compare C output select select */ +typedef enum TCD_CMPCSEL_enum +{ + TCD_CMPCSEL_PWMA_gc = (0x00<<6), /* PWM A output */ + TCD_CMPCSEL_PWMB_gc = (0x01<<6), /* PWM B output */ +} TCD_CMPCSEL_t; + +/* Compare D output select select */ +typedef enum TCD_CMPDSEL_enum +{ + TCD_CMPDSEL_PWMA_gc = (0x00<<7), /* PWM A output */ + TCD_CMPDSEL_PWMB_gc = (0x01<<7), /* PWM B output */ +} TCD_CMPDSEL_t; + +/* counter prescaler select */ +typedef enum TCD_CNTPRES_enum +{ + TCD_CNTPRES_DIV1_gc = (0x00<<3), /* Sync clock divided by 1 */ + TCD_CNTPRES_DIV4_gc = (0x01<<3), /* Sync clock divided by 4 */ + TCD_CNTPRES_DIV32_gc = (0x02<<3), /* Sync clock divided by 32 */ +} TCD_CNTPRES_t; + +/* dither select select */ +typedef enum TCD_DITHERSEL_enum +{ + TCD_DITHERSEL_ONTIMEB_gc = (0x00<<0), /* On-time ramp B */ + TCD_DITHERSEL_ONTIMEAB_gc = (0x01<<0), /* On-time ramp A and B */ + TCD_DITHERSEL_DEADTIMEB_gc = (0x02<<0), /* Dead-time rampB */ + TCD_DITHERSEL_DEADTIMEAB_gc = (0x03<<0), /* Dead-time ramp A and B */ +} TCD_DITHERSEL_t; + +/* Delay prescaler select */ +typedef enum TCD_DLYPRESC_enum +{ + TCD_DLYPRESC_DIV1_gc = (0x00<<4), /* No prescaling */ + TCD_DLYPRESC_DIV2_gc = (0x01<<4), /* Prescale with 2 */ + TCD_DLYPRESC_DIV4_gc = (0x02<<4), /* Prescale with 4 */ + TCD_DLYPRESC_DIV8_gc = (0x03<<4), /* Prescale with 8 */ +} TCD_DLYPRESC_t; + +/* Delay select select */ +typedef enum TCD_DLYSEL_enum +{ + TCD_DLYSEL_OFF_gc = (0x00<<0), /* No delay */ + TCD_DLYSEL_INBLANK_gc = (0x01<<0), /* Input blanking enabled */ + TCD_DLYSEL_EVENT_gc = (0x02<<0), /* Event delay enabled */ +} TCD_DLYSEL_t; + +/* Delay trigger select */ +typedef enum TCD_DLYTRIG_enum +{ + TCD_DLYTRIG_CMPASET_gc = (0x00<<2), /* Compare A set */ + TCD_DLYTRIG_CMPACLR_gc = (0x01<<2), /* Compare A clear */ + TCD_DLYTRIG_CMPBSET_gc = (0x02<<2), /* Compare B set */ + TCD_DLYTRIG_CMPBCLR_gc = (0x03<<2), /* Compare B clear */ +} TCD_DLYTRIG_t; + +/* edge select select */ +typedef enum TCD_EDGE_enum +{ + TCD_EDGE_FALL_LOW_gc = (0x00<<4), /* The falling edge or low level of event generates retrigger or fault action */ + TCD_EDGE_RISE_HIGH_gc = (0x01<<4), /* The rising edge or high level of event generates retrigger or fault action */ +} TCD_EDGE_t; + +/* Input mode select */ +typedef enum TCD_INPUTMODE_enum +{ + TCD_INPUTMODE_NONE_gc = (0x00<<0), /* Input has no actions */ + TCD_INPUTMODE_JMPWAIT_gc = (0x01<<0), /* Stop output, jump to opposite compare cycle and wait */ + TCD_INPUTMODE_EXECWAIT_gc = (0x02<<0), /* Stop output, execute opposite compare cycle and wait */ + TCD_INPUTMODE_EXECFAULT_gc = (0x03<<0), /* stop output, execute opposite compare cycle while fault active */ + TCD_INPUTMODE_FREQ_gc = (0x04<<0), /* Stop all outputs, maintain frequency */ + TCD_INPUTMODE_EXECDT_gc = (0x05<<0), /* Stop all outputs, execute dead time while fault active */ + TCD_INPUTMODE_WAIT_gc = (0x06<<0), /* Stop all outputs, jump to next compare cycle and wait */ + TCD_INPUTMODE_WAITSW_gc = (0x07<<0), /* Stop all outputs, wait for software action */ + TCD_INPUTMODE_EDGETRIG_gc = (0x08<<0), /* Stop output on edge, jump to next compare cycle */ + TCD_INPUTMODE_EDGETRIGFREQ_gc = (0x09<<0), /* Stop output on edge, maintain frequency */ + TCD_INPUTMODE_LVLTRIGFREQ_gc = (0x0A<<0), /* Stop output at level, maintain frequency */ +} TCD_INPUTMODE_t; + +/* Syncronization prescaler select */ +typedef enum TCD_SYNCPRES_enum +{ + TCD_SYNCPRES_DIV1_gc = (0x00<<1), /* Selevted clock source divided by 1 */ + TCD_SYNCPRES_DIV2_gc = (0x01<<1), /* Selevted clock source divided by 2 */ + TCD_SYNCPRES_DIV4_gc = (0x02<<1), /* Selevted clock source divided by 4 */ + TCD_SYNCPRES_DIV8_gc = (0x03<<1), /* Selevted clock source divided by 8 */ +} TCD_SYNCPRES_t; + +/* Waveform generation mode select */ +typedef enum TCD_WGMODE_enum +{ + TCD_WGMODE_ONERAMP_gc = (0x00<<0), /* One ramp mode */ + TCD_WGMODE_TWORAMP_gc = (0x01<<0), /* Two ramp mode */ + TCD_WGMODE_FOURRAMP_gc = (0x02<<0), /* Four ramp mode */ + TCD_WGMODE_DS_gc = (0x03<<0), /* Dual slope mode */ +} TCD_WGMODE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRLA; /* Control A */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control Register */ + register8_t MCTRLA; /* Master Control A */ + register8_t MCTRLB; /* Master Control B */ + register8_t MSTATUS; /* Master Status */ + register8_t MBAUD; /* Master Baurd Rate Control */ + register8_t MADDR; /* Master Address */ + register8_t MDATA; /* Master Data */ + register8_t SCTRLA; /* Slave Control A */ + register8_t SCTRLB; /* Slave Control B */ + register8_t SSTATUS; /* Slave Status */ + register8_t SADDR; /* Slave Address */ + register8_t SDATA; /* Slave Data */ + register8_t SADDRMASK; /* Slave Address Mask */ + register8_t reserved_2[1]; +} TWI_t; + +/* Acknowledge Action select */ +typedef enum TWI_ACKACT_enum +{ + TWI_ACKACT_ACK_gc = (0x00<<2), /* Send ACK */ + TWI_ACKACT_NACK_gc = (0x01<<2), /* Send NACK */ +} TWI_ACKACT_t; + +/* Slave Address or Stop select */ +typedef enum TWI_AP_enum +{ + TWI_AP_STOP_gc = (0x00<<0), /* Stop condition generated APIF */ + TWI_AP_ADR_gc = (0x01<<0), /* Address detection generated APIF */ +} TWI_AP_t; + +/* Bus State select */ +typedef enum TWI_BUSSTATE_enum +{ + TWI_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_BUSSTATE_t; + +/* Command select */ +typedef enum TWI_MCMD_enum +{ + TWI_MCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MCMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MCMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data, depending on DIR */ + TWI_MCMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MCMD_t; + +/* Command select */ +typedef enum TWI_SCMD_enum +{ + TWI_SCMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SCMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SCMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SCMD_t; + +/* SDA Hold Time select */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<2), /* SDA hold time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<2), /* Typical 50ns hold time */ + TWI_SDAHOLD_300NS_gc = (0x02<<2), /* Typical 300ns hold time */ + TWI_SDAHOLD_500NS_gc = (0x03<<2), /* Typical 500ns hold time */ +} TWI_SDAHOLD_t; + +/* SDA Setup Time select */ +typedef enum TWI_SDASETUP_enum +{ + TWI_SDASETUP_4CYC_gc = (0x00<<4), /* SDA setup time is 4 clock cycles */ + TWI_SDASETUP_8CYC_gc = (0x01<<4), /* SDA setup time is 8 clock cycles */ +} TWI_SDASETUP_t; + +/* Inactive Bus Timeout select */ +typedef enum TWI_TIMEOUT_enum +{ + TWI_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_TIMEOUT_t; + +/* +-------------------------------------------------------------------------- +USART - Universal Synchronous and Asynchronous Receiver and Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous and Asynchronous Receiver and Transmitter */ +typedef struct USART_struct +{ + register8_t RXDATAL; /* Receive Data Low Byte */ + register8_t RXDATAH; /* Receive Data High Byte */ + register8_t TXDATAL; /* Transmit Data Low Byte */ + register8_t TXDATAH; /* Transmit Data High Byte */ + register8_t STATUS; /* Status */ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ + register8_t CTRLC; /* Control C */ + _WORDREGISTER(BAUD); /* Baud Rate */ + register8_t reserved_1[1]; + register8_t DBGCTRL; /* Debug Control */ + register8_t EVCTRL; /* Event Control */ + register8_t TXPLCTRL; /* IRCOM Transmitter Pulse Length Control */ + register8_t RXPLCTRL; /* IRCOM Receiver Pulse Length Control */ + register8_t reserved_2[1]; +} USART_t; + +/* Character Size select */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BITL_gc = (0x06<<0), /* Character size: 9 bit read low byte first */ + USART_CHSIZE_9BITH_gc = (0x07<<0), /* Character size: 9 bit read high byte first */ +} USART_CHSIZE_t; + +/* Communication Mode select */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRCOM_gc = (0x02<<6), /* Infrared Communication */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode select */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* RS485 Mode internal transmitter select */ +typedef enum USART_RS485_enum +{ + USART_RS485_OFF_gc = (0x00<<0), /* RS485 Mode disabled */ + USART_RS485_EXT_gc = (0x01<<0), /* RS485 Mode External drive */ + USART_RS485_INT_gc = (0x02<<0), /* RS485 Mode Internal drive */ +} USART_RS485_t; + +/* Receiver Mode select */ +typedef enum USART_RXMODE_enum +{ + USART_RXMODE_NORMAL_gc = (0x00<<1), /* Normal mode */ + USART_RXMODE_CLK2X_gc = (0x01<<1), /* CLK2x mode */ + USART_RXMODE_GENAUTO_gc = (0x02<<1), /* Generic autobaud mode */ + USART_RXMODE_LINAUTO_gc = (0x03<<1), /* LIN constrained autobaud mode */ +} USART_RXMODE_t; + +/* Stop Bit Mode select */ +typedef enum USART_SBMODE_enum +{ + USART_SBMODE_1BIT_gc = (0x00<<3), /* 1 stop bit */ + USART_SBMODE_2BIT_gc = (0x01<<3), /* 2 stop bits */ +} USART_SBMODE_t; + +/* +-------------------------------------------------------------------------- +USERROW - User Row +-------------------------------------------------------------------------- +*/ + +/* User Row */ +typedef struct USERROW_struct +{ + register8_t USERROW0; /* User Row Byte 0 */ + register8_t USERROW1; /* User Row Byte 1 */ + register8_t USERROW2; /* User Row Byte 2 */ + register8_t USERROW3; /* User Row Byte 3 */ + register8_t USERROW4; /* User Row Byte 4 */ + register8_t USERROW5; /* User Row Byte 5 */ + register8_t USERROW6; /* User Row Byte 6 */ + register8_t USERROW7; /* User Row Byte 7 */ + register8_t USERROW8; /* User Row Byte 8 */ + register8_t USERROW9; /* User Row Byte 9 */ + register8_t USERROW10; /* User Row Byte 10 */ + register8_t USERROW11; /* User Row Byte 11 */ + register8_t USERROW12; /* User Row Byte 12 */ + register8_t USERROW13; /* User Row Byte 13 */ + register8_t USERROW14; /* User Row Byte 14 */ + register8_t USERROW15; /* User Row Byte 15 */ + register8_t USERROW16; /* User Row Byte 16 */ + register8_t USERROW17; /* User Row Byte 17 */ + register8_t USERROW18; /* User Row Byte 18 */ + register8_t USERROW19; /* User Row Byte 19 */ + register8_t USERROW20; /* User Row Byte 20 */ + register8_t USERROW21; /* User Row Byte 21 */ + register8_t USERROW22; /* User Row Byte 22 */ + register8_t USERROW23; /* User Row Byte 23 */ + register8_t USERROW24; /* User Row Byte 24 */ + register8_t USERROW25; /* User Row Byte 25 */ + register8_t USERROW26; /* User Row Byte 26 */ + register8_t USERROW27; /* User Row Byte 27 */ + register8_t USERROW28; /* User Row Byte 28 */ + register8_t USERROW29; /* User Row Byte 29 */ + register8_t USERROW30; /* User Row Byte 30 */ + register8_t USERROW31; /* User Row Byte 31 */ +} USERROW_t; + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Ports */ +typedef struct VPORT_struct +{ + register8_t DIR; /* Data Direction */ + register8_t OUT; /* Output Value */ + register8_t IN; /* Input Value */ + register8_t INTFLAGS; /* Interrupt Flags */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +VREF - Voltage reference +-------------------------------------------------------------------------- +*/ + +/* Voltage reference */ +typedef struct VREF_struct +{ + register8_t CTRLA; /* Control A */ + register8_t CTRLB; /* Control B */ +} VREF_t; + +/* ADC0 reference select select */ +typedef enum VREF_ADC0REFSEL_enum +{ + VREF_ADC0REFSEL_0V55_gc = (0x00<<4), /* Voltage reference at 0.55V */ + VREF_ADC0REFSEL_1V1_gc = (0x01<<4), /* Voltage reference at 1.1V */ + VREF_ADC0REFSEL_2V5_gc = (0x02<<4), /* Voltage reference at 2.5V */ + VREF_ADC0REFSEL_4V34_gc = (0x03<<4), /* Voltage reference at 4.34V */ + VREF_ADC0REFSEL_1V5_gc = (0x04<<4), /* Voltage reference at 1.5V */ +} VREF_ADC0REFSEL_t; + +/* DAC0/AC0 reference select select */ +typedef enum VREF_DAC0REFSEL_enum +{ + VREF_DAC0REFSEL_0V55_gc = (0x00<<0), /* Voltage reference at 0.55V */ + VREF_DAC0REFSEL_1V1_gc = (0x01<<0), /* Voltage reference at 1.1V */ + VREF_DAC0REFSEL_2V5_gc = (0x02<<0), /* Voltage reference at 2.5V */ + VREF_DAC0REFSEL_4V34_gc = (0x03<<0), /* Voltage reference at 4.34V */ + VREF_DAC0REFSEL_1V5_gc = (0x04<<0), /* Voltage reference at 1.5V */ +} VREF_DAC0REFSEL_t; + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRLA; /* Control A */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period select */ +typedef enum WDT_PERIOD_enum +{ + WDT_PERIOD_OFF_gc = (0x00<<0), /* Watch-Dog timer Off */ + WDT_PERIOD_8CLK_gc = (0x01<<0), /* 8 cycles (8ms) */ + WDT_PERIOD_16CLK_gc = (0x02<<0), /* 16 cycles (16ms) */ + WDT_PERIOD_32CLK_gc = (0x03<<0), /* 32 cycles (32ms) */ + WDT_PERIOD_64CLK_gc = (0x04<<0), /* 64 cycles (64ms) */ + WDT_PERIOD_128CLK_gc = (0x05<<0), /* 128 cycles (0.128s) */ + WDT_PERIOD_256CLK_gc = (0x06<<0), /* 256 cycles (0.256s) */ + WDT_PERIOD_512CLK_gc = (0x07<<0), /* 512 cycles (0.512s) */ + WDT_PERIOD_1KCLK_gc = (0x08<<0), /* 1K cycles (1.0s) */ + WDT_PERIOD_2KCLK_gc = (0x09<<0), /* 2K cycles (2.0s) */ + WDT_PERIOD_4KCLK_gc = (0x0A<<0), /* 4K cycles (4.1s) */ + WDT_PERIOD_8KCLK_gc = (0x0B<<0), /* 8K cycles (8.2s) */ +} WDT_PERIOD_t; + +/* Window select */ +typedef enum WDT_WINDOW_enum +{ + WDT_WINDOW_OFF_gc = (0x00<<4), /* Window mode off */ + WDT_WINDOW_8CLK_gc = (0x01<<4), /* 8 cycles (8ms) */ + WDT_WINDOW_16CLK_gc = (0x02<<4), /* 16 cycles (16ms) */ + WDT_WINDOW_32CLK_gc = (0x03<<4), /* 32 cycles (32ms) */ + WDT_WINDOW_64CLK_gc = (0x04<<4), /* 64 cycles (64ms) */ + WDT_WINDOW_128CLK_gc = (0x05<<4), /* 128 cycles (0.128s) */ + WDT_WINDOW_256CLK_gc = (0x06<<4), /* 256 cycles (0.256s) */ + WDT_WINDOW_512CLK_gc = (0x07<<4), /* 512 cycles (0.512s) */ + WDT_WINDOW_1KCLK_gc = (0x08<<4), /* 1K cycles (1.0s) */ + WDT_WINDOW_2KCLK_gc = (0x09<<4), /* 2K cycles (2.0s) */ + WDT_WINDOW_4KCLK_gc = (0x0A<<4), /* 4K cycles (4.1s) */ + WDT_WINDOW_8KCLK_gc = (0x0B<<4), /* 8K cycles (8.2s) */ +} WDT_WINDOW_t; +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORTA (*(VPORT_t *) 0x0000) /* Virtual Ports */ +#define VPORTB (*(VPORT_t *) 0x0004) /* Virtual Ports */ +#define VPORTC (*(VPORT_t *) 0x0008) /* Virtual Ports */ +#define RSTCTRL (*(RSTCTRL_t *) 0x0040) /* Reset controller */ +#define SLPCTRL (*(SLPCTRL_t *) 0x0050) /* Sleep Controller */ +#define CLKCTRL (*(CLKCTRL_t *) 0x0060) /* Clock controller */ +#define BOD (*(BOD_t *) 0x0080) /* Bod interface */ +#define VREF (*(VREF_t *) 0x00A0) /* Voltage reference */ +#define WDT (*(WDT_t *) 0x0100) /* Watch-Dog Timer */ +#define CPUINT (*(CPUINT_t *) 0x0110) /* Interrupt Controller */ +#define CRCSCAN (*(CRCSCAN_t *) 0x0120) /* CRCSCAN */ +#define RTC (*(RTC_t *) 0x0140) /* Real-Time Counter */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define CCL (*(CCL_t *) 0x01C0) /* Configurable Custom Logic */ +#define PORTMUX (*(PORTMUX_t *) 0x0200) /* Port Multiplexer */ +#define PORTA (*(PORT_t *) 0x0400) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0420) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0440) /* I/O Ports */ +#define ADC0 (*(ADC_t *) 0x0600) /* Analog to Digital Converter */ +#define AC0 (*(AC_t *) 0x0670) /* Analog Comparator */ +#define DAC0 (*(DAC_t *) 0x0680) /* Digital to Analog Converter */ +#define USART0 (*(USART_t *) 0x0800) /* Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define TWI0 (*(TWI_t *) 0x0810) /* Two-Wire Interface */ +#define SPI0 (*(SPI_t *) 0x0820) /* Serial Peripheral Interface */ +#define TCA0 (*(TCA_t *) 0x0A00) /* 16-bit Timer/Counter Type A */ +#define TCB0 (*(TCB_t *) 0x0A40) /* 16-bit Timer Type B */ +#define TCD0 (*(TCD_t *) 0x0A80) /* Timer Counter D */ +#define SYSCFG (*(SYSCFG_t *) 0x0F00) /* System Configuration Registers */ +#define NVMCTRL (*(NVMCTRL_t *) 0x1000) /* Non-volatile Memory Controller */ +#define SIGROW (*(SIGROW_t *) 0x1100) /* Signature row */ +#define FUSE (*(FUSE_t *) 0x1280) /* Fuses */ +#define LOCKBIT (*(LOCKBIT_t *) 0x128A) /* Lockbit */ +#define USERROW (*(USERROW_t *) 0x1300) /* User Row */ + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + + +/* VPORT (VPORTA) - Virtual Ports */ +#define VPORTA_DIR _SFR_MEM8(0x0000) +#define VPORTA_OUT _SFR_MEM8(0x0001) +#define VPORTA_IN _SFR_MEM8(0x0002) +#define VPORTA_INTFLAGS _SFR_MEM8(0x0003) + + +/* VPORT (VPORTB) - Virtual Ports */ +#define VPORTB_DIR _SFR_MEM8(0x0004) +#define VPORTB_OUT _SFR_MEM8(0x0005) +#define VPORTB_IN _SFR_MEM8(0x0006) +#define VPORTB_INTFLAGS _SFR_MEM8(0x0007) + + +/* VPORT (VPORTC) - Virtual Ports */ +#define VPORTC_DIR _SFR_MEM8(0x0008) +#define VPORTC_OUT _SFR_MEM8(0x0009) +#define VPORTC_IN _SFR_MEM8(0x000A) +#define VPORTC_INTFLAGS _SFR_MEM8(0x000B) + + +/* GPIO - General Purpose IO */ +#define GPIO_GPIOR0 _SFR_MEM8(0x001C) +#define GPIO_GPIOR1 _SFR_MEM8(0x001D) +#define GPIO_GPIOR2 _SFR_MEM8(0x001E) +#define GPIO_GPIOR3 _SFR_MEM8(0x001F) + + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x001C) +#define GPIO_GPIO1 _SFR_MEM8(0x001D) +#define GPIO_GPIO2 _SFR_MEM8(0x001E) +#define GPIO_GPIO3 _SFR_MEM8(0x001F) + + +/* CPU - CPU */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + + +/* RSTCTRL - Reset controller */ +#define RSTCTRL_RSTFR _SFR_MEM8(0x0040) +#define RSTCTRL_SWRR _SFR_MEM8(0x0041) + + +/* SLPCTRL - Sleep Controller */ +#define SLPCTRL_CTRLA _SFR_MEM8(0x0050) + + +/* CLKCTRL - Clock controller */ +#define CLKCTRL_MCLKCTRLA _SFR_MEM8(0x0060) +#define CLKCTRL_MCLKCTRLB _SFR_MEM8(0x0061) +#define CLKCTRL_MCLKLOCK _SFR_MEM8(0x0062) +#define CLKCTRL_MCLKSTATUS _SFR_MEM8(0x0063) +#define CLKCTRL_OSC20MCTRLA _SFR_MEM8(0x0070) +#define CLKCTRL_OSC20MCALIBA _SFR_MEM8(0x0071) +#define CLKCTRL_OSC20MCALIBB _SFR_MEM8(0x0072) +#define CLKCTRL_OSC32KCTRLA _SFR_MEM8(0x0078) +#define CLKCTRL_XOSC32KCTRLA _SFR_MEM8(0x007C) + + +/* BOD - Bod interface */ +#define BOD_CTRLA _SFR_MEM8(0x0080) +#define BOD_CTRLB _SFR_MEM8(0x0081) +#define BOD_VLMCTRLA _SFR_MEM8(0x0088) +#define BOD_INTCTRL _SFR_MEM8(0x0089) +#define BOD_INTFLAGS _SFR_MEM8(0x008A) +#define BOD_STATUS _SFR_MEM8(0x008B) + + +/* VREF - Voltage reference */ +#define VREF_CTRLA _SFR_MEM8(0x00A0) +#define VREF_CTRLB _SFR_MEM8(0x00A1) + + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRLA _SFR_MEM8(0x0100) +#define WDT_STATUS _SFR_MEM8(0x0101) + + +/* CPUINT - Interrupt Controller */ +#define CPUINT_CTRLA _SFR_MEM8(0x0110) +#define CPUINT_STATUS _SFR_MEM8(0x0111) +#define CPUINT_LVL0PRI _SFR_MEM8(0x0112) +#define CPUINT_LVL1VEC _SFR_MEM8(0x0113) + + +/* CRCSCAN - CRCSCAN */ +#define CRCSCAN_CTRLA _SFR_MEM8(0x0120) +#define CRCSCAN_CTRLB _SFR_MEM8(0x0121) +#define CRCSCAN_STATUS _SFR_MEM8(0x0122) + + +/* RTC - Real-Time Counter */ +#define RTC_CTRLA _SFR_MEM8(0x0140) +#define RTC_STATUS _SFR_MEM8(0x0141) +#define RTC_INTCTRL _SFR_MEM8(0x0142) +#define RTC_INTFLAGS _SFR_MEM8(0x0143) +#define RTC_TEMP _SFR_MEM8(0x0144) +#define RTC_DBGCTRL _SFR_MEM8(0x0145) +#define RTC_CLKSEL _SFR_MEM8(0x0147) +#define RTC_CNT _SFR_MEM16(0x0148) +#define RTC_CNTL _SFR_MEM8(0x0148) +#define RTC_CNTH _SFR_MEM8(0x0149) +#define RTC_PER _SFR_MEM16(0x014A) +#define RTC_PERL _SFR_MEM8(0x014A) +#define RTC_PERH _SFR_MEM8(0x014B) +#define RTC_CMP _SFR_MEM16(0x014C) +#define RTC_CMPL _SFR_MEM8(0x014C) +#define RTC_CMPH _SFR_MEM8(0x014D) +#define RTC_PITCTRLA _SFR_MEM8(0x0150) +#define RTC_PITSTATUS _SFR_MEM8(0x0151) +#define RTC_PITINTCTRL _SFR_MEM8(0x0152) +#define RTC_PITINTFLAGS _SFR_MEM8(0x0153) +#define RTC_PITDBGCTRL _SFR_MEM8(0x0155) + + +/* EVSYS - Event System */ +#define EVSYS_ASYNCSTROBE _SFR_MEM8(0x0180) +#define EVSYS_SYNCSTROBE _SFR_MEM8(0x0181) +#define EVSYS_ASYNCCH0 _SFR_MEM8(0x0182) +#define EVSYS_ASYNCCH1 _SFR_MEM8(0x0183) +#define EVSYS_ASYNCCH2 _SFR_MEM8(0x0184) +#define EVSYS_ASYNCCH3 _SFR_MEM8(0x0185) +#define EVSYS_SYNCCH0 _SFR_MEM8(0x018A) +#define EVSYS_SYNCCH1 _SFR_MEM8(0x018B) +#define EVSYS_ASYNCUSER0 _SFR_MEM8(0x0192) +#define EVSYS_ASYNCUSER1 _SFR_MEM8(0x0193) +#define EVSYS_ASYNCUSER2 _SFR_MEM8(0x0194) +#define EVSYS_ASYNCUSER3 _SFR_MEM8(0x0195) +#define EVSYS_ASYNCUSER4 _SFR_MEM8(0x0196) +#define EVSYS_ASYNCUSER5 _SFR_MEM8(0x0197) +#define EVSYS_ASYNCUSER6 _SFR_MEM8(0x0198) +#define EVSYS_ASYNCUSER7 _SFR_MEM8(0x0199) +#define EVSYS_ASYNCUSER8 _SFR_MEM8(0x019A) +#define EVSYS_ASYNCUSER9 _SFR_MEM8(0x019B) +#define EVSYS_ASYNCUSER10 _SFR_MEM8(0x019C) +#define EVSYS_SYNCUSER0 _SFR_MEM8(0x01A2) +#define EVSYS_SYNCUSER1 _SFR_MEM8(0x01A3) + + +/* CCL - Configurable Custom Logic */ +#define CCL_CTRLA _SFR_MEM8(0x01C0) +#define CCL_SEQCTRL0 _SFR_MEM8(0x01C1) +#define CCL_LUT0CTRLA _SFR_MEM8(0x01C5) +#define CCL_LUT0CTRLB _SFR_MEM8(0x01C6) +#define CCL_LUT0CTRLC _SFR_MEM8(0x01C7) +#define CCL_TRUTH0 _SFR_MEM8(0x01C8) +#define CCL_LUT1CTRLA _SFR_MEM8(0x01C9) +#define CCL_LUT1CTRLB _SFR_MEM8(0x01CA) +#define CCL_LUT1CTRLC _SFR_MEM8(0x01CB) +#define CCL_TRUTH1 _SFR_MEM8(0x01CC) + + +/* PORTMUX - Port Multiplexer */ +#define PORTMUX_CTRLA _SFR_MEM8(0x0200) +#define PORTMUX_CTRLB _SFR_MEM8(0x0201) +#define PORTMUX_CTRLC _SFR_MEM8(0x0202) +#define PORTMUX_CTRLD _SFR_MEM8(0x0203) + + +/* PORT (PORTA) - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0400) +#define PORTA_DIRSET _SFR_MEM8(0x0401) +#define PORTA_DIRCLR _SFR_MEM8(0x0402) +#define PORTA_DIRTGL _SFR_MEM8(0x0403) +#define PORTA_OUT _SFR_MEM8(0x0404) +#define PORTA_OUTSET _SFR_MEM8(0x0405) +#define PORTA_OUTCLR _SFR_MEM8(0x0406) +#define PORTA_OUTTGL _SFR_MEM8(0x0407) +#define PORTA_IN _SFR_MEM8(0x0408) +#define PORTA_INTFLAGS _SFR_MEM8(0x0409) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0410) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0411) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0412) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0413) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0414) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0415) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0416) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0417) + + +/* PORT (PORTB) - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0420) +#define PORTB_DIRSET _SFR_MEM8(0x0421) +#define PORTB_DIRCLR _SFR_MEM8(0x0422) +#define PORTB_DIRTGL _SFR_MEM8(0x0423) +#define PORTB_OUT _SFR_MEM8(0x0424) +#define PORTB_OUTSET _SFR_MEM8(0x0425) +#define PORTB_OUTCLR _SFR_MEM8(0x0426) +#define PORTB_OUTTGL _SFR_MEM8(0x0427) +#define PORTB_IN _SFR_MEM8(0x0428) +#define PORTB_INTFLAGS _SFR_MEM8(0x0429) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0430) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0431) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0432) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0433) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0434) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0435) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0436) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0437) + + +/* PORT (PORTC) - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0440) +#define PORTC_DIRSET _SFR_MEM8(0x0441) +#define PORTC_DIRCLR _SFR_MEM8(0x0442) +#define PORTC_DIRTGL _SFR_MEM8(0x0443) +#define PORTC_OUT _SFR_MEM8(0x0444) +#define PORTC_OUTSET _SFR_MEM8(0x0445) +#define PORTC_OUTCLR _SFR_MEM8(0x0446) +#define PORTC_OUTTGL _SFR_MEM8(0x0447) +#define PORTC_IN _SFR_MEM8(0x0448) +#define PORTC_INTFLAGS _SFR_MEM8(0x0449) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0450) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0451) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0452) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0453) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0454) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0455) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0456) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0457) + + +/* ADC (ADC0) - Analog to Digital Converter */ +#define ADC0_CTRLA _SFR_MEM8(0x0600) +#define ADC0_CTRLB _SFR_MEM8(0x0601) +#define ADC0_CTRLC _SFR_MEM8(0x0602) +#define ADC0_CTRLD _SFR_MEM8(0x0603) +#define ADC0_CTRLE _SFR_MEM8(0x0604) +#define ADC0_SAMPCTRL _SFR_MEM8(0x0605) +#define ADC0_MUXPOS _SFR_MEM8(0x0606) +#define ADC0_COMMAND _SFR_MEM8(0x0608) +#define ADC0_EVCTRL _SFR_MEM8(0x0609) +#define ADC0_INTCTRL _SFR_MEM8(0x060A) +#define ADC0_INTFLAGS _SFR_MEM8(0x060B) +#define ADC0_DBGCTRL _SFR_MEM8(0x060C) +#define ADC0_TEMP _SFR_MEM8(0x060D) +#define ADC0_RES _SFR_MEM16(0x0610) +#define ADC0_RESL _SFR_MEM8(0x0610) +#define ADC0_RESH _SFR_MEM8(0x0611) +#define ADC0_WINLT _SFR_MEM16(0x0612) +#define ADC0_WINLTL _SFR_MEM8(0x0612) +#define ADC0_WINLTH _SFR_MEM8(0x0613) +#define ADC0_WINHT _SFR_MEM16(0x0614) +#define ADC0_WINHTL _SFR_MEM8(0x0614) +#define ADC0_WINHTH _SFR_MEM8(0x0615) +#define ADC0_CALIB _SFR_MEM8(0x0616) + + +/* AC (AC0) - Analog Comparator */ +#define AC0_CTRLA _SFR_MEM8(0x0670) +#define AC0_MUXCTRLA _SFR_MEM8(0x0672) +#define AC0_INTCTRL _SFR_MEM8(0x0676) +#define AC0_STATUS _SFR_MEM8(0x0677) + + +/* DAC (DAC0) - Digital to Analog Converter */ +#define DAC0_CTRLA _SFR_MEM8(0x0680) +#define DAC0_DATA _SFR_MEM8(0x0681) + + +/* USART (USART0) - Universal Synchronous and Asynchronous Receiver and Transmitter */ +#define USART0_RXDATAL _SFR_MEM8(0x0800) +#define USART0_RXDATAH _SFR_MEM8(0x0801) +#define USART0_TXDATAL _SFR_MEM8(0x0802) +#define USART0_TXDATAH _SFR_MEM8(0x0803) +#define USART0_STATUS _SFR_MEM8(0x0804) +#define USART0_CTRLA _SFR_MEM8(0x0805) +#define USART0_CTRLB _SFR_MEM8(0x0806) +#define USART0_CTRLC _SFR_MEM8(0x0807) +#define USART0_BAUD _SFR_MEM16(0x0808) +#define USART0_BAUDL _SFR_MEM8(0x0808) +#define USART0_BAUDH _SFR_MEM8(0x0809) +#define USART0_DBGCTRL _SFR_MEM8(0x080B) +#define USART0_EVCTRL _SFR_MEM8(0x080C) +#define USART0_TXPLCTRL _SFR_MEM8(0x080D) +#define USART0_RXPLCTRL _SFR_MEM8(0x080E) + + +/* TWI (TWI0) - Two-Wire Interface */ +#define TWI0_CTRLA _SFR_MEM8(0x0810) +#define TWI0_DBGCTRL _SFR_MEM8(0x0812) +#define TWI0_MCTRLA _SFR_MEM8(0x0813) +#define TWI0_MCTRLB _SFR_MEM8(0x0814) +#define TWI0_MSTATUS _SFR_MEM8(0x0815) +#define TWI0_MBAUD _SFR_MEM8(0x0816) +#define TWI0_MADDR _SFR_MEM8(0x0817) +#define TWI0_MDATA _SFR_MEM8(0x0818) +#define TWI0_SCTRLA _SFR_MEM8(0x0819) +#define TWI0_SCTRLB _SFR_MEM8(0x081A) +#define TWI0_SSTATUS _SFR_MEM8(0x081B) +#define TWI0_SADDR _SFR_MEM8(0x081C) +#define TWI0_SDATA _SFR_MEM8(0x081D) +#define TWI0_SADDRMASK _SFR_MEM8(0x081E) + + +/* SPI (SPI0) - Serial Peripheral Interface */ +#define SPI0_CTRLA _SFR_MEM8(0x0820) +#define SPI0_CTRLB _SFR_MEM8(0x0821) +#define SPI0_INTCTRL _SFR_MEM8(0x0822) +#define SPI0_INTFLAGS _SFR_MEM8(0x0823) +#define SPI0_DATA _SFR_MEM8(0x0824) + + +/* TCA (TCA0) - 16-bit Timer/Counter Type A */ +#define TCA0_SINGLE_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SINGLE_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SINGLE_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SINGLE_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SINGLE_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SINGLE_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SINGLE_CTRLFCLR _SFR_MEM8(0x0A06) +#define TCA0_SINGLE_CTRLFSET _SFR_MEM8(0x0A07) +#define TCA0_SINGLE_EVCTRL _SFR_MEM8(0x0A09) +#define TCA0_SINGLE_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SINGLE_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SINGLE_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SINGLE_TEMP _SFR_MEM8(0x0A0F) +#define TCA0_SINGLE_CNT _SFR_MEM16(0x0A20) +#define TCA0_SINGLE_PER _SFR_MEM16(0x0A26) +#define TCA0_SINGLE_CMP0 _SFR_MEM16(0x0A28) +#define TCA0_SINGLE_CMP1 _SFR_MEM16(0x0A2A) +#define TCA0_SINGLE_CMP2 _SFR_MEM16(0x0A2C) +#define TCA0_SINGLE_PERBUF _SFR_MEM16(0x0A36) +#define TCA0_SINGLE_CMP0BUF _SFR_MEM16(0x0A38) +#define TCA0_SINGLE_CMP1BUF _SFR_MEM16(0x0A3A) +#define TCA0_SINGLE_CMP2BUF _SFR_MEM16(0x0A3C) + + +#define TCA0_SPLIT_CTRLA _SFR_MEM8(0x0A00) +#define TCA0_SPLIT_CTRLB _SFR_MEM8(0x0A01) +#define TCA0_SPLIT_CTRLC _SFR_MEM8(0x0A02) +#define TCA0_SPLIT_CTRLD _SFR_MEM8(0x0A03) +#define TCA0_SPLIT_CTRLECLR _SFR_MEM8(0x0A04) +#define TCA0_SPLIT_CTRLESET _SFR_MEM8(0x0A05) +#define TCA0_SPLIT_INTCTRL _SFR_MEM8(0x0A0A) +#define TCA0_SPLIT_INTFLAGS _SFR_MEM8(0x0A0B) +#define TCA0_SPLIT_DBGCTRL _SFR_MEM8(0x0A0E) +#define TCA0_SPLIT_LCNT _SFR_MEM8(0x0A20) +#define TCA0_SPLIT_HCNT _SFR_MEM8(0x0A21) +#define TCA0_SPLIT_LPER _SFR_MEM8(0x0A26) +#define TCA0_SPLIT_HPER _SFR_MEM8(0x0A27) +#define TCA0_SPLIT_LCMP0 _SFR_MEM8(0x0A28) +#define TCA0_SPLIT_HCMP0 _SFR_MEM8(0x0A29) +#define TCA0_SPLIT_LCMP1 _SFR_MEM8(0x0A2A) +#define TCA0_SPLIT_HCMP1 _SFR_MEM8(0x0A2B) +#define TCA0_SPLIT_LCMP2 _SFR_MEM8(0x0A2C) +#define TCA0_SPLIT_HCMP2 _SFR_MEM8(0x0A2D) + + + + +/* TCB (TCB0) - 16-bit Timer Type B */ +#define TCB0_CTRLA _SFR_MEM8(0x0A40) +#define TCB0_CTRLB _SFR_MEM8(0x0A41) +#define TCB0_EVCTRL _SFR_MEM8(0x0A44) +#define TCB0_INTCTRL _SFR_MEM8(0x0A45) +#define TCB0_INTFLAGS _SFR_MEM8(0x0A46) +#define TCB0_STATUS _SFR_MEM8(0x0A47) +#define TCB0_DBGCTRL _SFR_MEM8(0x0A48) +#define TCB0_TEMP _SFR_MEM8(0x0A49) +#define TCB0_CNT _SFR_MEM16(0x0A4A) +#define TCB0_CNTL _SFR_MEM8(0x0A4A) +#define TCB0_CNTH _SFR_MEM8(0x0A4B) +#define TCB0_CCMP _SFR_MEM16(0x0A4C) +#define TCB0_CCMPL _SFR_MEM8(0x0A4C) +#define TCB0_CCMPH _SFR_MEM8(0x0A4D) + + +/* TCD (TCD0) - Timer Counter D */ +#define TCD0_CTRLA _SFR_MEM8(0x0A80) +#define TCD0_CTRLB _SFR_MEM8(0x0A81) +#define TCD0_CTRLC _SFR_MEM8(0x0A82) +#define TCD0_CTRLD _SFR_MEM8(0x0A83) +#define TCD0_CTRLE _SFR_MEM8(0x0A84) +#define TCD0_EVCTRLA _SFR_MEM8(0x0A88) +#define TCD0_EVCTRLB _SFR_MEM8(0x0A89) +#define TCD0_INTCTRL _SFR_MEM8(0x0A8C) +#define TCD0_INTFLAGS _SFR_MEM8(0x0A8D) +#define TCD0_STATUS _SFR_MEM8(0x0A8E) +#define TCD0_INPUTCTRLA _SFR_MEM8(0x0A90) +#define TCD0_INPUTCTRLB _SFR_MEM8(0x0A91) +#define TCD0_FAULTCTRL _SFR_MEM8(0x0A92) +#define TCD0_DLYCTRL _SFR_MEM8(0x0A94) +#define TCD0_DLYVAL _SFR_MEM8(0x0A95) +#define TCD0_DITCTRL _SFR_MEM8(0x0A98) +#define TCD0_DITVAL _SFR_MEM8(0x0A99) +#define TCD0_DBGCTRL _SFR_MEM8(0x0A9E) +#define TCD0_CAPTUREA _SFR_MEM16(0x0AA2) +#define TCD0_CAPTUREAL _SFR_MEM8(0x0AA2) +#define TCD0_CAPTUREAH _SFR_MEM8(0x0AA3) +#define TCD0_CAPTUREB _SFR_MEM16(0x0AA4) +#define TCD0_CAPTUREBL _SFR_MEM8(0x0AA4) +#define TCD0_CAPTUREBH _SFR_MEM8(0x0AA5) +#define TCD0_CMPASET _SFR_MEM16(0x0AA8) +#define TCD0_CMPASETL _SFR_MEM8(0x0AA8) +#define TCD0_CMPASETH _SFR_MEM8(0x0AA9) +#define TCD0_CMPACLR _SFR_MEM16(0x0AAA) +#define TCD0_CMPACLRL _SFR_MEM8(0x0AAA) +#define TCD0_CMPACLRH _SFR_MEM8(0x0AAB) +#define TCD0_CMPBSET _SFR_MEM16(0x0AAC) +#define TCD0_CMPBSETL _SFR_MEM8(0x0AAC) +#define TCD0_CMPBSETH _SFR_MEM8(0x0AAD) +#define TCD0_CMPBCLR _SFR_MEM16(0x0AAE) +#define TCD0_CMPBCLRL _SFR_MEM8(0x0AAE) +#define TCD0_CMPBCLRH _SFR_MEM8(0x0AAF) + + +/* SYSCFG - System Configuration Registers */ +#define SYSCFG_REVID _SFR_MEM8(0x0F01) +#define SYSCFG_EXTBRK _SFR_MEM8(0x0F02) + + +/* NVMCTRL - Non-volatile Memory Controller */ +#define NVMCTRL_CTRLA _SFR_MEM8(0x1000) +#define NVMCTRL_CTRLB _SFR_MEM8(0x1001) +#define NVMCTRL_STATUS _SFR_MEM8(0x1002) +#define NVMCTRL_INTCTRL _SFR_MEM8(0x1003) +#define NVMCTRL_INTFLAGS _SFR_MEM8(0x1004) +#define NVMCTRL_DATA _SFR_MEM16(0x1006) +#define NVMCTRL_DATAL _SFR_MEM8(0x1006) +#define NVMCTRL_DATAH _SFR_MEM8(0x1007) +#define NVMCTRL_ADDR _SFR_MEM16(0x1008) +#define NVMCTRL_ADDRL _SFR_MEM8(0x1008) +#define NVMCTRL_ADDRH _SFR_MEM8(0x1009) + + +/* SIGROW - Signature row */ +#define SIGROW_DEVICEID0 _SFR_MEM8(0x1100) +#define SIGROW_DEVICEID1 _SFR_MEM8(0x1101) +#define SIGROW_DEVICEID2 _SFR_MEM8(0x1102) +#define SIGROW_SERNUM0 _SFR_MEM8(0x1103) +#define SIGROW_SERNUM1 _SFR_MEM8(0x1104) +#define SIGROW_SERNUM2 _SFR_MEM8(0x1105) +#define SIGROW_SERNUM3 _SFR_MEM8(0x1106) +#define SIGROW_SERNUM4 _SFR_MEM8(0x1107) +#define SIGROW_SERNUM5 _SFR_MEM8(0x1108) +#define SIGROW_SERNUM6 _SFR_MEM8(0x1109) +#define SIGROW_SERNUM7 _SFR_MEM8(0x110A) +#define SIGROW_SERNUM8 _SFR_MEM8(0x110B) +#define SIGROW_SERNUM9 _SFR_MEM8(0x110C) +#define SIGROW_TEMPSENSE0 _SFR_MEM8(0x1120) +#define SIGROW_TEMPSENSE1 _SFR_MEM8(0x1121) +#define SIGROW_OSC16ERR3V _SFR_MEM8(0x1122) +#define SIGROW_OSC16ERR5V _SFR_MEM8(0x1123) +#define SIGROW_OSC20ERR3V _SFR_MEM8(0x1124) +#define SIGROW_OSC20ERR5V _SFR_MEM8(0x1125) + + +/* FUSE - Fuses */ +#define FUSE_WDTCFG _SFR_MEM8(0x1280) +#define FUSE_BODCFG _SFR_MEM8(0x1281) +#define FUSE_OSCCFG _SFR_MEM8(0x1282) +#define FUSE_TCD0CFG _SFR_MEM8(0x1284) +#define FUSE_SYSCFG0 _SFR_MEM8(0x1285) +#define FUSE_SYSCFG1 _SFR_MEM8(0x1286) +#define FUSE_APPEND _SFR_MEM8(0x1287) +#define FUSE_BOOTEND _SFR_MEM8(0x1288) + + +/* LOCKBIT - Lockbit */ +#define LOCKBIT_LOCKBIT _SFR_MEM8(0x128A) + + +/* USERROW - User Row */ +#define USERROW_USERROW0 _SFR_MEM8(0x1300) +#define USERROW_USERROW1 _SFR_MEM8(0x1301) +#define USERROW_USERROW2 _SFR_MEM8(0x1302) +#define USERROW_USERROW3 _SFR_MEM8(0x1303) +#define USERROW_USERROW4 _SFR_MEM8(0x1304) +#define USERROW_USERROW5 _SFR_MEM8(0x1305) +#define USERROW_USERROW6 _SFR_MEM8(0x1306) +#define USERROW_USERROW7 _SFR_MEM8(0x1307) +#define USERROW_USERROW8 _SFR_MEM8(0x1308) +#define USERROW_USERROW9 _SFR_MEM8(0x1309) +#define USERROW_USERROW10 _SFR_MEM8(0x130A) +#define USERROW_USERROW11 _SFR_MEM8(0x130B) +#define USERROW_USERROW12 _SFR_MEM8(0x130C) +#define USERROW_USERROW13 _SFR_MEM8(0x130D) +#define USERROW_USERROW14 _SFR_MEM8(0x130E) +#define USERROW_USERROW15 _SFR_MEM8(0x130F) +#define USERROW_USERROW16 _SFR_MEM8(0x1310) +#define USERROW_USERROW17 _SFR_MEM8(0x1311) +#define USERROW_USERROW18 _SFR_MEM8(0x1312) +#define USERROW_USERROW19 _SFR_MEM8(0x1313) +#define USERROW_USERROW20 _SFR_MEM8(0x1314) +#define USERROW_USERROW21 _SFR_MEM8(0x1315) +#define USERROW_USERROW22 _SFR_MEM8(0x1316) +#define USERROW_USERROW23 _SFR_MEM8(0x1317) +#define USERROW_USERROW24 _SFR_MEM8(0x1318) +#define USERROW_USERROW25 _SFR_MEM8(0x1319) +#define USERROW_USERROW26 _SFR_MEM8(0x131A) +#define USERROW_USERROW27 _SFR_MEM8(0x131B) +#define USERROW_USERROW28 _SFR_MEM8(0x131C) +#define USERROW_USERROW29 _SFR_MEM8(0x131D) +#define USERROW_USERROW30 _SFR_MEM8(0x131E) +#define USERROW_USERROW31 _SFR_MEM8(0x131F) + + + +/*================== Bitfield Definitions ================== */ + +/* AC - Analog Comparator */ +/* AC.CTRLA bit masks and bit positions */ +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +#define AC_LPMODE_bm 0x08 /* Low Power Mode bit mask. */ +#define AC_LPMODE_bp 3 /* Low Power Mode bit position. */ +#define AC_INTMODE_gm 0x30 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 4 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<4) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 4 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<5) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 5 /* Interrupt Mode bit 1 position. */ +#define AC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define AC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define AC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define AC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + +/* AC.MUXCTRLA bit masks and bit positions */ +#define AC_MUXNEG_gm 0x03 /* Negative Input MUX Selection group mask. */ +#define AC_MUXNEG_gp 0 /* Negative Input MUX Selection group position. */ +#define AC_MUXNEG0_bm (1<<0) /* Negative Input MUX Selection bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* Negative Input MUX Selection bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* Negative Input MUX Selection bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* Negative Input MUX Selection bit 1 position. */ +#define AC_MUXPOS_bm 0x08 /* Positive Input MUX Selection bit mask. */ +#define AC_MUXPOS_bp 3 /* Positive Input MUX Selection bit position. */ +#define AC_INVERT_bm 0x80 /* Invert AC Output bit mask. */ +#define AC_INVERT_bp 7 /* Invert AC Output bit position. */ + +/* AC.INTCTRL bit masks and bit positions */ +#define AC_CMP_bm 0x01 /* Analog Comparator 0 Interrupt Enable bit mask. */ +#define AC_CMP_bp 0 /* Analog Comparator 0 Interrupt Enable bit position. */ + +/* AC.STATUS bit masks and bit positions */ +/* AC_CMP is already defined. */ +#define AC_STATE_bm 0x10 /* Analog Comparator State bit mask. */ +#define AC_STATE_bp 4 /* Analog Comparator State bit position. */ + +/* ADC - Analog to Digital Converter */ +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_ENABLE_bm 0x01 /* ADC Enable bit mask. */ +#define ADC_ENABLE_bp 0 /* ADC Enable bit position. */ +#define ADC_FREERUN_bm 0x02 /* ADC Freerun mode bit mask. */ +#define ADC_FREERUN_bp 1 /* ADC Freerun mode bit position. */ +#define ADC_RESSEL_bm 0x04 /* ADC Resolution bit mask. */ +#define ADC_RESSEL_bp 2 /* ADC Resolution bit position. */ +#define ADC_RUNSTBY_bm 0x80 /* Run standby mode bit mask. */ +#define ADC_RUNSTBY_bp 7 /* Run standby mode bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_SAMPNUM_gm 0x07 /* Accumulation Samples group mask. */ +#define ADC_SAMPNUM_gp 0 /* Accumulation Samples group position. */ +#define ADC_SAMPNUM0_bm (1<<0) /* Accumulation Samples bit 0 mask. */ +#define ADC_SAMPNUM0_bp 0 /* Accumulation Samples bit 0 position. */ +#define ADC_SAMPNUM1_bm (1<<1) /* Accumulation Samples bit 1 mask. */ +#define ADC_SAMPNUM1_bp 1 /* Accumulation Samples bit 1 position. */ +#define ADC_SAMPNUM2_bm (1<<2) /* Accumulation Samples bit 2 mask. */ +#define ADC_SAMPNUM2_bp 2 /* Accumulation Samples bit 2 position. */ + +/* ADC.CTRLC bit masks and bit positions */ +#define ADC_PRESC_gm 0x07 /* Clock Pre-scaler group mask. */ +#define ADC_PRESC_gp 0 /* Clock Pre-scaler group position. */ +#define ADC_PRESC0_bm (1<<0) /* Clock Pre-scaler bit 0 mask. */ +#define ADC_PRESC0_bp 0 /* Clock Pre-scaler bit 0 position. */ +#define ADC_PRESC1_bm (1<<1) /* Clock Pre-scaler bit 1 mask. */ +#define ADC_PRESC1_bp 1 /* Clock Pre-scaler bit 1 position. */ +#define ADC_PRESC2_bm (1<<2) /* Clock Pre-scaler bit 2 mask. */ +#define ADC_PRESC2_bp 2 /* Clock Pre-scaler bit 2 position. */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_SAMPCAP_bm 0x40 /* Sample Capacitance Selection bit mask. */ +#define ADC_SAMPCAP_bp 6 /* Sample Capacitance Selection bit position. */ + +/* ADC.CTRLD bit masks and bit positions */ +#define ADC_SAMPDLY_gm 0x0F /* Sampling Delay Selection group mask. */ +#define ADC_SAMPDLY_gp 0 /* Sampling Delay Selection group position. */ +#define ADC_SAMPDLY0_bm (1<<0) /* Sampling Delay Selection bit 0 mask. */ +#define ADC_SAMPDLY0_bp 0 /* Sampling Delay Selection bit 0 position. */ +#define ADC_SAMPDLY1_bm (1<<1) /* Sampling Delay Selection bit 1 mask. */ +#define ADC_SAMPDLY1_bp 1 /* Sampling Delay Selection bit 1 position. */ +#define ADC_SAMPDLY2_bm (1<<2) /* Sampling Delay Selection bit 2 mask. */ +#define ADC_SAMPDLY2_bp 2 /* Sampling Delay Selection bit 2 position. */ +#define ADC_SAMPDLY3_bm (1<<3) /* Sampling Delay Selection bit 3 mask. */ +#define ADC_SAMPDLY3_bp 3 /* Sampling Delay Selection bit 3 position. */ +#define ADC_ASDV_bm 0x10 /* Automatic Sampling Delay Variation bit mask. */ +#define ADC_ASDV_bp 4 /* Automatic Sampling Delay Variation bit position. */ +#define ADC_INITDLY_gm 0xE0 /* Initial Delay Selection group mask. */ +#define ADC_INITDLY_gp 5 /* Initial Delay Selection group position. */ +#define ADC_INITDLY0_bm (1<<5) /* Initial Delay Selection bit 0 mask. */ +#define ADC_INITDLY0_bp 5 /* Initial Delay Selection bit 0 position. */ +#define ADC_INITDLY1_bm (1<<6) /* Initial Delay Selection bit 1 mask. */ +#define ADC_INITDLY1_bp 6 /* Initial Delay Selection bit 1 position. */ +#define ADC_INITDLY2_bm (1<<7) /* Initial Delay Selection bit 2 mask. */ +#define ADC_INITDLY2_bp 7 /* Initial Delay Selection bit 2 position. */ + +/* ADC.CTRLE bit masks and bit positions */ +#define ADC_WINCM_gm 0x07 /* Window Comparator Mode group mask. */ +#define ADC_WINCM_gp 0 /* Window Comparator Mode group position. */ +#define ADC_WINCM0_bm (1<<0) /* Window Comparator Mode bit 0 mask. */ +#define ADC_WINCM0_bp 0 /* Window Comparator Mode bit 0 position. */ +#define ADC_WINCM1_bm (1<<1) /* Window Comparator Mode bit 1 mask. */ +#define ADC_WINCM1_bp 1 /* Window Comparator Mode bit 1 position. */ +#define ADC_WINCM2_bm (1<<2) /* Window Comparator Mode bit 2 mask. */ +#define ADC_WINCM2_bp 2 /* Window Comparator Mode bit 2 position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPLEN_gm 0x1F /* Sample lenght group mask. */ +#define ADC_SAMPLEN_gp 0 /* Sample lenght group position. */ +#define ADC_SAMPLEN0_bm (1<<0) /* Sample lenght bit 0 mask. */ +#define ADC_SAMPLEN0_bp 0 /* Sample lenght bit 0 position. */ +#define ADC_SAMPLEN1_bm (1<<1) /* Sample lenght bit 1 mask. */ +#define ADC_SAMPLEN1_bp 1 /* Sample lenght bit 1 position. */ +#define ADC_SAMPLEN2_bm (1<<2) /* Sample lenght bit 2 mask. */ +#define ADC_SAMPLEN2_bp 2 /* Sample lenght bit 2 position. */ +#define ADC_SAMPLEN3_bm (1<<3) /* Sample lenght bit 3 mask. */ +#define ADC_SAMPLEN3_bp 3 /* Sample lenght bit 3 position. */ +#define ADC_SAMPLEN4_bm (1<<4) /* Sample lenght bit 4 mask. */ +#define ADC_SAMPLEN4_bp 4 /* Sample lenght bit 4 position. */ + +/* ADC.MUXPOS bit masks and bit positions */ +#define ADC_MUXPOS_gm 0x1F /* Analog Channel Selection Bits group mask. */ +#define ADC_MUXPOS_gp 0 /* Analog Channel Selection Bits group position. */ +#define ADC_MUXPOS0_bm (1<<0) /* Analog Channel Selection Bits bit 0 mask. */ +#define ADC_MUXPOS0_bp 0 /* Analog Channel Selection Bits bit 0 position. */ +#define ADC_MUXPOS1_bm (1<<1) /* Analog Channel Selection Bits bit 1 mask. */ +#define ADC_MUXPOS1_bp 1 /* Analog Channel Selection Bits bit 1 position. */ +#define ADC_MUXPOS2_bm (1<<2) /* Analog Channel Selection Bits bit 2 mask. */ +#define ADC_MUXPOS2_bp 2 /* Analog Channel Selection Bits bit 2 position. */ +#define ADC_MUXPOS3_bm (1<<3) /* Analog Channel Selection Bits bit 3 mask. */ +#define ADC_MUXPOS3_bp 3 /* Analog Channel Selection Bits bit 3 position. */ +#define ADC_MUXPOS4_bm (1<<4) /* Analog Channel Selection Bits bit 4 mask. */ +#define ADC_MUXPOS4_bp 4 /* Analog Channel Selection Bits bit 4 position. */ + +/* ADC.COMMAND bit masks and bit positions */ +#define ADC_STCONV_bm 0x01 /* Start Conversion Operation bit mask. */ +#define ADC_STCONV_bp 0 /* Start Conversion Operation bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_STARTEI_bm 0x01 /* Start Event Input Enable bit mask. */ +#define ADC_STARTEI_bp 0 /* Start Event Input Enable bit position. */ + +/* ADC.INTCTRL bit masks and bit positions */ +#define ADC_RESRDY_bm 0x01 /* Result Ready Interrupt Enable bit mask. */ +#define ADC_RESRDY_bp 0 /* Result Ready Interrupt Enable bit position. */ +#define ADC_WCMP_bm 0x02 /* Window Comparator Interrupt Enable bit mask. */ +#define ADC_WCMP_bp 1 /* Window Comparator Interrupt Enable bit position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +/* ADC_RESRDY is already defined. */ +/* ADC_WCMP is already defined. */ + +/* ADC.DBGCTRL bit masks and bit positions */ +#define ADC_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define ADC_DBGRUN_bp 0 /* Debug run bit position. */ + +/* ADC.TEMP bit masks and bit positions */ +#define ADC_TEMP_gm 0xFF /* Temporary group mask. */ +#define ADC_TEMP_gp 0 /* Temporary group position. */ +#define ADC_TEMP0_bm (1<<0) /* Temporary bit 0 mask. */ +#define ADC_TEMP0_bp 0 /* Temporary bit 0 position. */ +#define ADC_TEMP1_bm (1<<1) /* Temporary bit 1 mask. */ +#define ADC_TEMP1_bp 1 /* Temporary bit 1 position. */ +#define ADC_TEMP2_bm (1<<2) /* Temporary bit 2 mask. */ +#define ADC_TEMP2_bp 2 /* Temporary bit 2 position. */ +#define ADC_TEMP3_bm (1<<3) /* Temporary bit 3 mask. */ +#define ADC_TEMP3_bp 3 /* Temporary bit 3 position. */ +#define ADC_TEMP4_bm (1<<4) /* Temporary bit 4 mask. */ +#define ADC_TEMP4_bp 4 /* Temporary bit 4 position. */ +#define ADC_TEMP5_bm (1<<5) /* Temporary bit 5 mask. */ +#define ADC_TEMP5_bp 5 /* Temporary bit 5 position. */ +#define ADC_TEMP6_bm (1<<6) /* Temporary bit 6 mask. */ +#define ADC_TEMP6_bp 6 /* Temporary bit 6 position. */ +#define ADC_TEMP7_bm (1<<7) /* Temporary bit 7 mask. */ +#define ADC_TEMP7_bp 7 /* Temporary bit 7 position. */ + + + + +/* ADC.CALIB bit masks and bit positions */ +#define ADC_DUTYCYC_bm 0x01 /* Duty Cycle bit mask. */ +#define ADC_DUTYCYC_bp 0 /* Duty Cycle bit position. */ + +/* BOD - Bod interface */ +/* BOD.CTRLA bit masks and bit positions */ +#define BOD_SLEEP_gm 0x03 /* Operation in sleep mode group mask. */ +#define BOD_SLEEP_gp 0 /* Operation in sleep mode group position. */ +#define BOD_SLEEP0_bm (1<<0) /* Operation in sleep mode bit 0 mask. */ +#define BOD_SLEEP0_bp 0 /* Operation in sleep mode bit 0 position. */ +#define BOD_SLEEP1_bm (1<<1) /* Operation in sleep mode bit 1 mask. */ +#define BOD_SLEEP1_bp 1 /* Operation in sleep mode bit 1 position. */ +#define BOD_ACTIVE_gm 0x0C /* Operation in active mode group mask. */ +#define BOD_ACTIVE_gp 2 /* Operation in active mode group position. */ +#define BOD_ACTIVE0_bm (1<<2) /* Operation in active mode bit 0 mask. */ +#define BOD_ACTIVE0_bp 2 /* Operation in active mode bit 0 position. */ +#define BOD_ACTIVE1_bm (1<<3) /* Operation in active mode bit 1 mask. */ +#define BOD_ACTIVE1_bp 3 /* Operation in active mode bit 1 position. */ +#define BOD_SAMPFREQ_bm 0x10 /* Sample frequency bit mask. */ +#define BOD_SAMPFREQ_bp 4 /* Sample frequency bit position. */ + +/* BOD.CTRLB bit masks and bit positions */ +#define BOD_LVL_gm 0x07 /* Bod level group mask. */ +#define BOD_LVL_gp 0 /* Bod level group position. */ +#define BOD_LVL0_bm (1<<0) /* Bod level bit 0 mask. */ +#define BOD_LVL0_bp 0 /* Bod level bit 0 position. */ +#define BOD_LVL1_bm (1<<1) /* Bod level bit 1 mask. */ +#define BOD_LVL1_bp 1 /* Bod level bit 1 position. */ +#define BOD_LVL2_bm (1<<2) /* Bod level bit 2 mask. */ +#define BOD_LVL2_bp 2 /* Bod level bit 2 position. */ + +/* BOD.VLMCTRLA bit masks and bit positions */ +#define BOD_VLMLVL_gm 0x03 /* voltage level monitor level group mask. */ +#define BOD_VLMLVL_gp 0 /* voltage level monitor level group position. */ +#define BOD_VLMLVL0_bm (1<<0) /* voltage level monitor level bit 0 mask. */ +#define BOD_VLMLVL0_bp 0 /* voltage level monitor level bit 0 position. */ +#define BOD_VLMLVL1_bm (1<<1) /* voltage level monitor level bit 1 mask. */ +#define BOD_VLMLVL1_bp 1 /* voltage level monitor level bit 1 position. */ + +/* BOD.INTCTRL bit masks and bit positions */ +#define BOD_VLMIE_bm 0x01 /* voltage level monitor interrrupt enable bit mask. */ +#define BOD_VLMIE_bp 0 /* voltage level monitor interrrupt enable bit position. */ +#define BOD_VLMCFG_gm 0x06 /* Configuration group mask. */ +#define BOD_VLMCFG_gp 1 /* Configuration group position. */ +#define BOD_VLMCFG0_bm (1<<1) /* Configuration bit 0 mask. */ +#define BOD_VLMCFG0_bp 1 /* Configuration bit 0 position. */ +#define BOD_VLMCFG1_bm (1<<2) /* Configuration bit 1 mask. */ +#define BOD_VLMCFG1_bp 2 /* Configuration bit 1 position. */ + +/* BOD.INTFLAGS bit masks and bit positions */ +#define BOD_VLMIF_bm 0x01 /* Voltage level monitor interrupt flag bit mask. */ +#define BOD_VLMIF_bp 0 /* Voltage level monitor interrupt flag bit position. */ + +/* BOD.STATUS bit masks and bit positions */ +#define BOD_VLMS_bm 0x01 /* Voltage level monitor status bit mask. */ +#define BOD_VLMS_bp 0 /* Voltage level monitor status bit position. */ + +/* CCL - Configurable Custom Logic */ +/* CCL.CTRLA bit masks and bit positions */ +#define CCL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CCL_ENABLE_bp 0 /* Enable bit position. */ +#define CCL_RUNSTDBY_bm 0x40 /* Run in Standby bit mask. */ +#define CCL_RUNSTDBY_bp 6 /* Run in Standby bit position. */ + +/* CCL.SEQCTRL0 bit masks and bit positions */ +#define CCL_SEQSEL_gm 0x07 /* Sequential Selection group mask. */ +#define CCL_SEQSEL_gp 0 /* Sequential Selection group position. */ +#define CCL_SEQSEL0_bm (1<<0) /* Sequential Selection bit 0 mask. */ +#define CCL_SEQSEL0_bp 0 /* Sequential Selection bit 0 position. */ +#define CCL_SEQSEL1_bm (1<<1) /* Sequential Selection bit 1 mask. */ +#define CCL_SEQSEL1_bp 1 /* Sequential Selection bit 1 position. */ +#define CCL_SEQSEL2_bm (1<<2) /* Sequential Selection bit 2 mask. */ +#define CCL_SEQSEL2_bp 2 /* Sequential Selection bit 2 position. */ + +/* CCL.LUT0CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +#define CCL_OUTEN_bm 0x08 /* Output Enable bit mask. */ +#define CCL_OUTEN_bp 3 /* Output Enable bit position. */ +#define CCL_FILTSEL_gm 0x30 /* Filter Selection group mask. */ +#define CCL_FILTSEL_gp 4 /* Filter Selection group position. */ +#define CCL_FILTSEL0_bm (1<<4) /* Filter Selection bit 0 mask. */ +#define CCL_FILTSEL0_bp 4 /* Filter Selection bit 0 position. */ +#define CCL_FILTSEL1_bm (1<<5) /* Filter Selection bit 1 mask. */ +#define CCL_FILTSEL1_bp 5 /* Filter Selection bit 1 position. */ +#define CCL_CLKSRC_bm 0x40 /* Clock Source Selection bit mask. */ +#define CCL_CLKSRC_bp 6 /* Clock Source Selection bit position. */ +#define CCL_EDGEDET_bm 0x80 /* Edge Detection Enable bit mask. */ +#define CCL_EDGEDET_bp 7 /* Edge Detection Enable bit position. */ + +/* CCL.LUT0CTRLB bit masks and bit positions */ +#define CCL_INSEL0_gm 0x0F /* LUT Input 0 Source Selection group mask. */ +#define CCL_INSEL0_gp 0 /* LUT Input 0 Source Selection group position. */ +#define CCL_INSEL00_bm (1<<0) /* LUT Input 0 Source Selection bit 0 mask. */ +#define CCL_INSEL00_bp 0 /* LUT Input 0 Source Selection bit 0 position. */ +#define CCL_INSEL01_bm (1<<1) /* LUT Input 0 Source Selection bit 1 mask. */ +#define CCL_INSEL01_bp 1 /* LUT Input 0 Source Selection bit 1 position. */ +#define CCL_INSEL02_bm (1<<2) /* LUT Input 0 Source Selection bit 2 mask. */ +#define CCL_INSEL02_bp 2 /* LUT Input 0 Source Selection bit 2 position. */ +#define CCL_INSEL03_bm (1<<3) /* LUT Input 0 Source Selection bit 3 mask. */ +#define CCL_INSEL03_bp 3 /* LUT Input 0 Source Selection bit 3 position. */ +#define CCL_INSEL1_gm 0xF0 /* LUT Input 1 Source Selection group mask. */ +#define CCL_INSEL1_gp 4 /* LUT Input 1 Source Selection group position. */ +#define CCL_INSEL10_bm (1<<4) /* LUT Input 1 Source Selection bit 0 mask. */ +#define CCL_INSEL10_bp 4 /* LUT Input 1 Source Selection bit 0 position. */ +#define CCL_INSEL11_bm (1<<5) /* LUT Input 1 Source Selection bit 1 mask. */ +#define CCL_INSEL11_bp 5 /* LUT Input 1 Source Selection bit 1 position. */ +#define CCL_INSEL12_bm (1<<6) /* LUT Input 1 Source Selection bit 2 mask. */ +#define CCL_INSEL12_bp 6 /* LUT Input 1 Source Selection bit 2 position. */ +#define CCL_INSEL13_bm (1<<7) /* LUT Input 1 Source Selection bit 3 mask. */ +#define CCL_INSEL13_bp 7 /* LUT Input 1 Source Selection bit 3 position. */ + +/* CCL.LUT0CTRLC bit masks and bit positions */ +#define CCL_INSEL2_gm 0x0F /* LUT Input 2 Source Selection group mask. */ +#define CCL_INSEL2_gp 0 /* LUT Input 2 Source Selection group position. */ +#define CCL_INSEL20_bm (1<<0) /* LUT Input 2 Source Selection bit 0 mask. */ +#define CCL_INSEL20_bp 0 /* LUT Input 2 Source Selection bit 0 position. */ +#define CCL_INSEL21_bm (1<<1) /* LUT Input 2 Source Selection bit 1 mask. */ +#define CCL_INSEL21_bp 1 /* LUT Input 2 Source Selection bit 1 position. */ +#define CCL_INSEL22_bm (1<<2) /* LUT Input 2 Source Selection bit 2 mask. */ +#define CCL_INSEL22_bp 2 /* LUT Input 2 Source Selection bit 2 position. */ +#define CCL_INSEL23_bm (1<<3) /* LUT Input 2 Source Selection bit 3 mask. */ +#define CCL_INSEL23_bp 3 /* LUT Input 2 Source Selection bit 3 position. */ + + +/* CCL.LUT1CTRLA bit masks and bit positions */ +/* CCL_ENABLE is already defined. */ +/* CCL_OUTEN is already defined. */ +/* CCL_FILTSEL is already defined. */ +/* CCL_CLKSRC is already defined. */ +/* CCL_EDGEDET is already defined. */ + +/* CCL.LUT1CTRLB bit masks and bit positions */ +/* CCL_INSEL0 is already defined. */ +/* CCL_INSEL1 is already defined. */ + +/* CCL.LUT1CTRLC bit masks and bit positions */ +/* CCL_INSEL2 is already defined. */ + + +/* CLKCTRL - Clock controller */ +/* CLKCTRL.MCLKCTRLA bit masks and bit positions */ +#define CLKCTRL_CLKSEL_gm 0x03 /* clock select group mask. */ +#define CLKCTRL_CLKSEL_gp 0 /* clock select group position. */ +#define CLKCTRL_CLKSEL0_bm (1<<0) /* clock select bit 0 mask. */ +#define CLKCTRL_CLKSEL0_bp 0 /* clock select bit 0 position. */ +#define CLKCTRL_CLKSEL1_bm (1<<1) /* clock select bit 1 mask. */ +#define CLKCTRL_CLKSEL1_bp 1 /* clock select bit 1 position. */ +#define CLKCTRL_CLKOUT_bm 0x80 /* System clock out bit mask. */ +#define CLKCTRL_CLKOUT_bp 7 /* System clock out bit position. */ + +/* CLKCTRL.MCLKCTRLB bit masks and bit positions */ +#define CLKCTRL_PEN_bm 0x01 /* Prescaler enable bit mask. */ +#define CLKCTRL_PEN_bp 0 /* Prescaler enable bit position. */ +#define CLKCTRL_PDIV_gm 0x1E /* Prescaler division group mask. */ +#define CLKCTRL_PDIV_gp 1 /* Prescaler division group position. */ +#define CLKCTRL_PDIV0_bm (1<<1) /* Prescaler division bit 0 mask. */ +#define CLKCTRL_PDIV0_bp 1 /* Prescaler division bit 0 position. */ +#define CLKCTRL_PDIV1_bm (1<<2) /* Prescaler division bit 1 mask. */ +#define CLKCTRL_PDIV1_bp 2 /* Prescaler division bit 1 position. */ +#define CLKCTRL_PDIV2_bm (1<<3) /* Prescaler division bit 2 mask. */ +#define CLKCTRL_PDIV2_bp 3 /* Prescaler division bit 2 position. */ +#define CLKCTRL_PDIV3_bm (1<<4) /* Prescaler division bit 3 mask. */ +#define CLKCTRL_PDIV3_bp 4 /* Prescaler division bit 3 position. */ + +/* CLKCTRL.MCLKLOCK bit masks and bit positions */ +#define CLKCTRL_LOCKEN_bm 0x01 /* lock ebable bit mask. */ +#define CLKCTRL_LOCKEN_bp 0 /* lock ebable bit position. */ + +/* CLKCTRL.MCLKSTATUS bit masks and bit positions */ +#define CLKCTRL_SOSC_bm 0x01 /* System Oscillator changing bit mask. */ +#define CLKCTRL_SOSC_bp 0 /* System Oscillator changing bit position. */ +#define CLKCTRL_OSC20MS_bm 0x10 /* 20MHz oscillator status bit mask. */ +#define CLKCTRL_OSC20MS_bp 4 /* 20MHz oscillator status bit position. */ +#define CLKCTRL_OSC32KS_bm 0x20 /* 32KHz oscillator status bit mask. */ +#define CLKCTRL_OSC32KS_bp 5 /* 32KHz oscillator status bit position. */ +#define CLKCTRL_XOSC32KS_bm 0x40 /* 32.768 kHz Crystal Oscillator status bit mask. */ +#define CLKCTRL_XOSC32KS_bp 6 /* 32.768 kHz Crystal Oscillator status bit position. */ +#define CLKCTRL_EXTS_bm 0x80 /* External Clock status bit mask. */ +#define CLKCTRL_EXTS_bp 7 /* External Clock status bit position. */ + +/* CLKCTRL.OSC20MCTRLA bit masks and bit positions */ +#define CLKCTRL_RUNSTDBY_bm 0x02 /* Run standby bit mask. */ +#define CLKCTRL_RUNSTDBY_bp 1 /* Run standby bit position. */ + +/* CLKCTRL.OSC20MCALIBA bit masks and bit positions */ +#define CLKCTRL_CAL20M_gm 0x3F /* Calibration group mask. */ +#define CLKCTRL_CAL20M_gp 0 /* Calibration group position. */ +#define CLKCTRL_CAL20M0_bm (1<<0) /* Calibration bit 0 mask. */ +#define CLKCTRL_CAL20M0_bp 0 /* Calibration bit 0 position. */ +#define CLKCTRL_CAL20M1_bm (1<<1) /* Calibration bit 1 mask. */ +#define CLKCTRL_CAL20M1_bp 1 /* Calibration bit 1 position. */ +#define CLKCTRL_CAL20M2_bm (1<<2) /* Calibration bit 2 mask. */ +#define CLKCTRL_CAL20M2_bp 2 /* Calibration bit 2 position. */ +#define CLKCTRL_CAL20M3_bm (1<<3) /* Calibration bit 3 mask. */ +#define CLKCTRL_CAL20M3_bp 3 /* Calibration bit 3 position. */ +#define CLKCTRL_CAL20M4_bm (1<<4) /* Calibration bit 4 mask. */ +#define CLKCTRL_CAL20M4_bp 4 /* Calibration bit 4 position. */ +#define CLKCTRL_CAL20M5_bm (1<<5) /* Calibration bit 5 mask. */ +#define CLKCTRL_CAL20M5_bp 5 /* Calibration bit 5 position. */ + +/* CLKCTRL.OSC20MCALIBB bit masks and bit positions */ +#define CLKCTRL_TEMPCAL20M_gm 0x0F /* Oscillator temperature coefficient group mask. */ +#define CLKCTRL_TEMPCAL20M_gp 0 /* Oscillator temperature coefficient group position. */ +#define CLKCTRL_TEMPCAL20M0_bm (1<<0) /* Oscillator temperature coefficient bit 0 mask. */ +#define CLKCTRL_TEMPCAL20M0_bp 0 /* Oscillator temperature coefficient bit 0 position. */ +#define CLKCTRL_TEMPCAL20M1_bm (1<<1) /* Oscillator temperature coefficient bit 1 mask. */ +#define CLKCTRL_TEMPCAL20M1_bp 1 /* Oscillator temperature coefficient bit 1 position. */ +#define CLKCTRL_TEMPCAL20M2_bm (1<<2) /* Oscillator temperature coefficient bit 2 mask. */ +#define CLKCTRL_TEMPCAL20M2_bp 2 /* Oscillator temperature coefficient bit 2 position. */ +#define CLKCTRL_TEMPCAL20M3_bm (1<<3) /* Oscillator temperature coefficient bit 3 mask. */ +#define CLKCTRL_TEMPCAL20M3_bp 3 /* Oscillator temperature coefficient bit 3 position. */ +#define CLKCTRL_LOCK_bm 0x80 /* Lock bit mask. */ +#define CLKCTRL_LOCK_bp 7 /* Lock bit position. */ + +/* CLKCTRL.OSC32KCTRLA bit masks and bit positions */ +/* CLKCTRL_RUNSTDBY is already defined. */ + +/* CLKCTRL.XOSC32KCTRLA bit masks and bit positions */ +#define CLKCTRL_ENABLE_bm 0x01 /* Enable bit mask. */ +#define CLKCTRL_ENABLE_bp 0 /* Enable bit position. */ +/* CLKCTRL_RUNSTDBY is already defined. */ +#define CLKCTRL_SEL_bm 0x04 /* Select bit mask. */ +#define CLKCTRL_SEL_bp 2 /* Select bit position. */ +#define CLKCTRL_CSUT_gm 0x30 /* Crystal startup time group mask. */ +#define CLKCTRL_CSUT_gp 4 /* Crystal startup time group position. */ +#define CLKCTRL_CSUT0_bm (1<<4) /* Crystal startup time bit 0 mask. */ +#define CLKCTRL_CSUT0_bp 4 /* Crystal startup time bit 0 position. */ +#define CLKCTRL_CSUT1_bm (1<<5) /* Crystal startup time bit 1 mask. */ +#define CLKCTRL_CSUT1_bp 5 /* Crystal startup time bit 1 position. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +/* CPUINT - Interrupt Controller */ +/* CPUINT.CTRLA bit masks and bit positions */ +#define CPUINT_LVL0RR_bm 0x01 /* Round-robin Scheduling Enable bit mask. */ +#define CPUINT_LVL0RR_bp 0 /* Round-robin Scheduling Enable bit position. */ +#define CPUINT_CVT_bm 0x20 /* Compact Vector Table bit mask. */ +#define CPUINT_CVT_bp 5 /* Compact Vector Table bit position. */ +#define CPUINT_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define CPUINT_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +/* CPUINT.STATUS bit masks and bit positions */ +#define CPUINT_LVL0EX_bm 0x01 /* Level 0 Interrupt Executing bit mask. */ +#define CPUINT_LVL0EX_bp 0 /* Level 0 Interrupt Executing bit position. */ +#define CPUINT_LVL1EX_bm 0x02 /* Level 1 Interrupt Executing bit mask. */ +#define CPUINT_LVL1EX_bp 1 /* Level 1 Interrupt Executing bit position. */ +#define CPUINT_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define CPUINT_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +/* CPUINT.LVL0PRI bit masks and bit positions */ +#define CPUINT_LVL0PRI_gm 0xFF /* Interrupt Level Priority group mask. */ +#define CPUINT_LVL0PRI_gp 0 /* Interrupt Level Priority group position. */ +#define CPUINT_LVL0PRI0_bm (1<<0) /* Interrupt Level Priority bit 0 mask. */ +#define CPUINT_LVL0PRI0_bp 0 /* Interrupt Level Priority bit 0 position. */ +#define CPUINT_LVL0PRI1_bm (1<<1) /* Interrupt Level Priority bit 1 mask. */ +#define CPUINT_LVL0PRI1_bp 1 /* Interrupt Level Priority bit 1 position. */ +#define CPUINT_LVL0PRI2_bm (1<<2) /* Interrupt Level Priority bit 2 mask. */ +#define CPUINT_LVL0PRI2_bp 2 /* Interrupt Level Priority bit 2 position. */ +#define CPUINT_LVL0PRI3_bm (1<<3) /* Interrupt Level Priority bit 3 mask. */ +#define CPUINT_LVL0PRI3_bp 3 /* Interrupt Level Priority bit 3 position. */ +#define CPUINT_LVL0PRI4_bm (1<<4) /* Interrupt Level Priority bit 4 mask. */ +#define CPUINT_LVL0PRI4_bp 4 /* Interrupt Level Priority bit 4 position. */ +#define CPUINT_LVL0PRI5_bm (1<<5) /* Interrupt Level Priority bit 5 mask. */ +#define CPUINT_LVL0PRI5_bp 5 /* Interrupt Level Priority bit 5 position. */ +#define CPUINT_LVL0PRI6_bm (1<<6) /* Interrupt Level Priority bit 6 mask. */ +#define CPUINT_LVL0PRI6_bp 6 /* Interrupt Level Priority bit 6 position. */ +#define CPUINT_LVL0PRI7_bm (1<<7) /* Interrupt Level Priority bit 7 mask. */ +#define CPUINT_LVL0PRI7_bp 7 /* Interrupt Level Priority bit 7 position. */ + +/* CPUINT.LVL1VEC bit masks and bit positions */ +#define CPUINT_LVL1VEC_gm 0xFF /* Interrupt Vector with High Priority group mask. */ +#define CPUINT_LVL1VEC_gp 0 /* Interrupt Vector with High Priority group position. */ +#define CPUINT_LVL1VEC0_bm (1<<0) /* Interrupt Vector with High Priority bit 0 mask. */ +#define CPUINT_LVL1VEC0_bp 0 /* Interrupt Vector with High Priority bit 0 position. */ +#define CPUINT_LVL1VEC1_bm (1<<1) /* Interrupt Vector with High Priority bit 1 mask. */ +#define CPUINT_LVL1VEC1_bp 1 /* Interrupt Vector with High Priority bit 1 position. */ +#define CPUINT_LVL1VEC2_bm (1<<2) /* Interrupt Vector with High Priority bit 2 mask. */ +#define CPUINT_LVL1VEC2_bp 2 /* Interrupt Vector with High Priority bit 2 position. */ +#define CPUINT_LVL1VEC3_bm (1<<3) /* Interrupt Vector with High Priority bit 3 mask. */ +#define CPUINT_LVL1VEC3_bp 3 /* Interrupt Vector with High Priority bit 3 position. */ +#define CPUINT_LVL1VEC4_bm (1<<4) /* Interrupt Vector with High Priority bit 4 mask. */ +#define CPUINT_LVL1VEC4_bp 4 /* Interrupt Vector with High Priority bit 4 position. */ +#define CPUINT_LVL1VEC5_bm (1<<5) /* Interrupt Vector with High Priority bit 5 mask. */ +#define CPUINT_LVL1VEC5_bp 5 /* Interrupt Vector with High Priority bit 5 position. */ +#define CPUINT_LVL1VEC6_bm (1<<6) /* Interrupt Vector with High Priority bit 6 mask. */ +#define CPUINT_LVL1VEC6_bp 6 /* Interrupt Vector with High Priority bit 6 position. */ +#define CPUINT_LVL1VEC7_bm (1<<7) /* Interrupt Vector with High Priority bit 7 mask. */ +#define CPUINT_LVL1VEC7_bp 7 /* Interrupt Vector with High Priority bit 7 position. */ + +/* CRCSCAN - CRCSCAN */ +/* CRCSCAN.CTRLA bit masks and bit positions */ +#define CRCSCAN_ENABLE_bm 0x01 /* Enable CRC scan bit mask. */ +#define CRCSCAN_ENABLE_bp 0 /* Enable CRC scan bit position. */ +#define CRCSCAN_NMIEN_bm 0x02 /* Enable NMI Trigger bit mask. */ +#define CRCSCAN_NMIEN_bp 1 /* Enable NMI Trigger bit position. */ +#define CRCSCAN_RESET_bm 0x80 /* Reset CRC scan bit mask. */ +#define CRCSCAN_RESET_bp 7 /* Reset CRC scan bit position. */ + +/* CRCSCAN.CTRLB bit masks and bit positions */ +#define CRCSCAN_SRC_gm 0x03 /* CRC Source group mask. */ +#define CRCSCAN_SRC_gp 0 /* CRC Source group position. */ +#define CRCSCAN_SRC0_bm (1<<0) /* CRC Source bit 0 mask. */ +#define CRCSCAN_SRC0_bp 0 /* CRC Source bit 0 position. */ +#define CRCSCAN_SRC1_bm (1<<1) /* CRC Source bit 1 mask. */ +#define CRCSCAN_SRC1_bp 1 /* CRC Source bit 1 position. */ +#define CRCSCAN_MODE_gm 0x30 /* CRC Flash Access Mode group mask. */ +#define CRCSCAN_MODE_gp 4 /* CRC Flash Access Mode group position. */ +#define CRCSCAN_MODE0_bm (1<<4) /* CRC Flash Access Mode bit 0 mask. */ +#define CRCSCAN_MODE0_bp 4 /* CRC Flash Access Mode bit 0 position. */ +#define CRCSCAN_MODE1_bm (1<<5) /* CRC Flash Access Mode bit 1 mask. */ +#define CRCSCAN_MODE1_bp 5 /* CRC Flash Access Mode bit 1 position. */ + +/* CRCSCAN.STATUS bit masks and bit positions */ +#define CRCSCAN_BUSY_bm 0x01 /* CRC Busy bit mask. */ +#define CRCSCAN_BUSY_bp 0 /* CRC Busy bit position. */ +#define CRCSCAN_OK_bm 0x02 /* CRC Ok bit mask. */ +#define CRCSCAN_OK_bp 1 /* CRC Ok bit position. */ + +/* DAC - Digital to Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_ENABLE_bm 0x01 /* DAC Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* DAC Enable bit position. */ +#define DAC_OUTEN_bm 0x40 /* Output Buffer Enable bit mask. */ +#define DAC_OUTEN_bp 6 /* Output Buffer Enable bit position. */ +#define DAC_RUNSTDBY_bm 0x80 /* Run in Standby Mode bit mask. */ +#define DAC_RUNSTDBY_bp 7 /* Run in Standby Mode bit position. */ + + + + +/* EVSYS - Event System */ +/* EVSYS.ASYNCCH0 bit masks and bit positions */ +#define EVSYS_ASYNCCH0_gm 0xFF /* Asynchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_ASYNCCH0_gp 0 /* Asynchronous Channel 0 Generator Selection group position. */ +#define EVSYS_ASYNCCH00_bm (1<<0) /* Asynchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH00_bp 0 /* Asynchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH01_bm (1<<1) /* Asynchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH01_bp 1 /* Asynchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH02_bm (1<<2) /* Asynchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH02_bp 2 /* Asynchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH03_bm (1<<3) /* Asynchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH03_bp 3 /* Asynchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH04_bm (1<<4) /* Asynchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH04_bp 4 /* Asynchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH05_bm (1<<5) /* Asynchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH05_bp 5 /* Asynchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH06_bm (1<<6) /* Asynchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH06_bp 6 /* Asynchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH07_bm (1<<7) /* Asynchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH07_bp 7 /* Asynchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH1 bit masks and bit positions */ +#define EVSYS_ASYNCCH1_gm 0xFF /* Asynchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_ASYNCCH1_gp 0 /* Asynchronous Channel 1 Generator Selection group position. */ +#define EVSYS_ASYNCCH10_bm (1<<0) /* Asynchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH10_bp 0 /* Asynchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH11_bm (1<<1) /* Asynchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH11_bp 1 /* Asynchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH12_bm (1<<2) /* Asynchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH12_bp 2 /* Asynchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH13_bm (1<<3) /* Asynchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH13_bp 3 /* Asynchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH14_bm (1<<4) /* Asynchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH14_bp 4 /* Asynchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH15_bm (1<<5) /* Asynchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH15_bp 5 /* Asynchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH16_bm (1<<6) /* Asynchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH16_bp 6 /* Asynchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH17_bm (1<<7) /* Asynchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH17_bp 7 /* Asynchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH2 bit masks and bit positions */ +#define EVSYS_ASYNCCH2_gm 0xFF /* Asynchronous Channel 2 Generator Selection group mask. */ +#define EVSYS_ASYNCCH2_gp 0 /* Asynchronous Channel 2 Generator Selection group position. */ +#define EVSYS_ASYNCCH20_bm (1<<0) /* Asynchronous Channel 2 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH20_bp 0 /* Asynchronous Channel 2 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH21_bm (1<<1) /* Asynchronous Channel 2 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH21_bp 1 /* Asynchronous Channel 2 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH22_bm (1<<2) /* Asynchronous Channel 2 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH22_bp 2 /* Asynchronous Channel 2 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH23_bm (1<<3) /* Asynchronous Channel 2 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH23_bp 3 /* Asynchronous Channel 2 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH24_bm (1<<4) /* Asynchronous Channel 2 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH24_bp 4 /* Asynchronous Channel 2 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH25_bm (1<<5) /* Asynchronous Channel 2 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH25_bp 5 /* Asynchronous Channel 2 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH26_bm (1<<6) /* Asynchronous Channel 2 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH26_bp 6 /* Asynchronous Channel 2 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH27_bm (1<<7) /* Asynchronous Channel 2 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH27_bp 7 /* Asynchronous Channel 2 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCCH3 bit masks and bit positions */ +#define EVSYS_ASYNCCH3_gm 0xFF /* Asynchronous Channel 3 Generator Selection group mask. */ +#define EVSYS_ASYNCCH3_gp 0 /* Asynchronous Channel 3 Generator Selection group position. */ +#define EVSYS_ASYNCCH30_bm (1<<0) /* Asynchronous Channel 3 Generator Selection bit 0 mask. */ +#define EVSYS_ASYNCCH30_bp 0 /* Asynchronous Channel 3 Generator Selection bit 0 position. */ +#define EVSYS_ASYNCCH31_bm (1<<1) /* Asynchronous Channel 3 Generator Selection bit 1 mask. */ +#define EVSYS_ASYNCCH31_bp 1 /* Asynchronous Channel 3 Generator Selection bit 1 position. */ +#define EVSYS_ASYNCCH32_bm (1<<2) /* Asynchronous Channel 3 Generator Selection bit 2 mask. */ +#define EVSYS_ASYNCCH32_bp 2 /* Asynchronous Channel 3 Generator Selection bit 2 position. */ +#define EVSYS_ASYNCCH33_bm (1<<3) /* Asynchronous Channel 3 Generator Selection bit 3 mask. */ +#define EVSYS_ASYNCCH33_bp 3 /* Asynchronous Channel 3 Generator Selection bit 3 position. */ +#define EVSYS_ASYNCCH34_bm (1<<4) /* Asynchronous Channel 3 Generator Selection bit 4 mask. */ +#define EVSYS_ASYNCCH34_bp 4 /* Asynchronous Channel 3 Generator Selection bit 4 position. */ +#define EVSYS_ASYNCCH35_bm (1<<5) /* Asynchronous Channel 3 Generator Selection bit 5 mask. */ +#define EVSYS_ASYNCCH35_bp 5 /* Asynchronous Channel 3 Generator Selection bit 5 position. */ +#define EVSYS_ASYNCCH36_bm (1<<6) /* Asynchronous Channel 3 Generator Selection bit 6 mask. */ +#define EVSYS_ASYNCCH36_bp 6 /* Asynchronous Channel 3 Generator Selection bit 6 position. */ +#define EVSYS_ASYNCCH37_bm (1<<7) /* Asynchronous Channel 3 Generator Selection bit 7 mask. */ +#define EVSYS_ASYNCCH37_bp 7 /* Asynchronous Channel 3 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH0 bit masks and bit positions */ +#define EVSYS_SYNCCH0_gm 0xFF /* Synchronous Channel 0 Generator Selection group mask. */ +#define EVSYS_SYNCCH0_gp 0 /* Synchronous Channel 0 Generator Selection group position. */ +#define EVSYS_SYNCCH00_bm (1<<0) /* Synchronous Channel 0 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH00_bp 0 /* Synchronous Channel 0 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH01_bm (1<<1) /* Synchronous Channel 0 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH01_bp 1 /* Synchronous Channel 0 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH02_bm (1<<2) /* Synchronous Channel 0 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH02_bp 2 /* Synchronous Channel 0 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH03_bm (1<<3) /* Synchronous Channel 0 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH03_bp 3 /* Synchronous Channel 0 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH04_bm (1<<4) /* Synchronous Channel 0 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH04_bp 4 /* Synchronous Channel 0 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH05_bm (1<<5) /* Synchronous Channel 0 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH05_bp 5 /* Synchronous Channel 0 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH06_bm (1<<6) /* Synchronous Channel 0 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH06_bp 6 /* Synchronous Channel 0 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH07_bm (1<<7) /* Synchronous Channel 0 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH07_bp 7 /* Synchronous Channel 0 Generator Selection bit 7 position. */ + +/* EVSYS.SYNCCH1 bit masks and bit positions */ +#define EVSYS_SYNCCH1_gm 0xFF /* Synchronous Channel 1 Generator Selection group mask. */ +#define EVSYS_SYNCCH1_gp 0 /* Synchronous Channel 1 Generator Selection group position. */ +#define EVSYS_SYNCCH10_bm (1<<0) /* Synchronous Channel 1 Generator Selection bit 0 mask. */ +#define EVSYS_SYNCCH10_bp 0 /* Synchronous Channel 1 Generator Selection bit 0 position. */ +#define EVSYS_SYNCCH11_bm (1<<1) /* Synchronous Channel 1 Generator Selection bit 1 mask. */ +#define EVSYS_SYNCCH11_bp 1 /* Synchronous Channel 1 Generator Selection bit 1 position. */ +#define EVSYS_SYNCCH12_bm (1<<2) /* Synchronous Channel 1 Generator Selection bit 2 mask. */ +#define EVSYS_SYNCCH12_bp 2 /* Synchronous Channel 1 Generator Selection bit 2 position. */ +#define EVSYS_SYNCCH13_bm (1<<3) /* Synchronous Channel 1 Generator Selection bit 3 mask. */ +#define EVSYS_SYNCCH13_bp 3 /* Synchronous Channel 1 Generator Selection bit 3 position. */ +#define EVSYS_SYNCCH14_bm (1<<4) /* Synchronous Channel 1 Generator Selection bit 4 mask. */ +#define EVSYS_SYNCCH14_bp 4 /* Synchronous Channel 1 Generator Selection bit 4 position. */ +#define EVSYS_SYNCCH15_bm (1<<5) /* Synchronous Channel 1 Generator Selection bit 5 mask. */ +#define EVSYS_SYNCCH15_bp 5 /* Synchronous Channel 1 Generator Selection bit 5 position. */ +#define EVSYS_SYNCCH16_bm (1<<6) /* Synchronous Channel 1 Generator Selection bit 6 mask. */ +#define EVSYS_SYNCCH16_bp 6 /* Synchronous Channel 1 Generator Selection bit 6 position. */ +#define EVSYS_SYNCCH17_bm (1<<7) /* Synchronous Channel 1 Generator Selection bit 7 mask. */ +#define EVSYS_SYNCCH17_bp 7 /* Synchronous Channel 1 Generator Selection bit 7 position. */ + +/* EVSYS.ASYNCUSER0 bit masks and bit positions */ +#define EVSYS_ASYNCUSER0_gm 0xFF /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */ +#define EVSYS_ASYNCUSER0_gp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */ +#define EVSYS_ASYNCUSER00_bm (1<<0) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */ +#define EVSYS_ASYNCUSER00_bp 0 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */ +#define EVSYS_ASYNCUSER01_bm (1<<1) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */ +#define EVSYS_ASYNCUSER01_bp 1 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */ +#define EVSYS_ASYNCUSER02_bm (1<<2) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */ +#define EVSYS_ASYNCUSER02_bp 2 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */ +#define EVSYS_ASYNCUSER03_bm (1<<3) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */ +#define EVSYS_ASYNCUSER03_bp 3 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */ +#define EVSYS_ASYNCUSER04_bm (1<<4) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */ +#define EVSYS_ASYNCUSER04_bp 4 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */ +#define EVSYS_ASYNCUSER05_bm (1<<5) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */ +#define EVSYS_ASYNCUSER05_bp 5 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */ +#define EVSYS_ASYNCUSER06_bm (1<<6) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */ +#define EVSYS_ASYNCUSER06_bp 6 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */ +#define EVSYS_ASYNCUSER07_bm (1<<7) /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */ +#define EVSYS_ASYNCUSER07_bp 7 /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */ + +/* EVSYS.ASYNCUSER1 bit masks and bit positions */ +#define EVSYS_ASYNCUSER1_gm 0xFF /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */ +#define EVSYS_ASYNCUSER1_gp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */ +#define EVSYS_ASYNCUSER10_bm (1<<0) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */ +#define EVSYS_ASYNCUSER10_bp 0 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */ +#define EVSYS_ASYNCUSER11_bm (1<<1) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */ +#define EVSYS_ASYNCUSER11_bp 1 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */ +#define EVSYS_ASYNCUSER12_bm (1<<2) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */ +#define EVSYS_ASYNCUSER12_bp 2 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */ +#define EVSYS_ASYNCUSER13_bm (1<<3) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */ +#define EVSYS_ASYNCUSER13_bp 3 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */ +#define EVSYS_ASYNCUSER14_bm (1<<4) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */ +#define EVSYS_ASYNCUSER14_bp 4 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */ +#define EVSYS_ASYNCUSER15_bm (1<<5) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */ +#define EVSYS_ASYNCUSER15_bp 5 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */ +#define EVSYS_ASYNCUSER16_bm (1<<6) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */ +#define EVSYS_ASYNCUSER16_bp 6 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */ +#define EVSYS_ASYNCUSER17_bm (1<<7) /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */ +#define EVSYS_ASYNCUSER17_bp 7 /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */ + +/* EVSYS.ASYNCUSER2 bit masks and bit positions */ +#define EVSYS_ASYNCUSER2_gm 0xFF /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER2_gp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */ +#define EVSYS_ASYNCUSER20_bm (1<<0) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER20_bp 0 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER21_bm (1<<1) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER21_bp 1 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER22_bm (1<<2) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER22_bp 2 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER23_bm (1<<3) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER23_bp 3 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER24_bm (1<<4) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER24_bp 4 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER25_bm (1<<5) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER25_bp 5 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER26_bm (1<<6) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER26_bp 6 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER27_bm (1<<7) /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER27_bp 7 /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER3 bit masks and bit positions */ +#define EVSYS_ASYNCUSER3_gm 0xFF /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */ +#define EVSYS_ASYNCUSER3_gp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */ +#define EVSYS_ASYNCUSER30_bm (1<<0) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER30_bp 0 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER31_bm (1<<1) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER31_bp 1 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER32_bm (1<<2) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER32_bp 2 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER33_bm (1<<3) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER33_bp 3 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER34_bm (1<<4) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER34_bp 4 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER35_bm (1<<5) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER35_bp 5 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER36_bm (1<<6) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER36_bp 6 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER37_bm (1<<7) /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER37_bp 7 /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER4 bit masks and bit positions */ +#define EVSYS_ASYNCUSER4_gm 0xFF /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER4_gp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */ +#define EVSYS_ASYNCUSER40_bm (1<<0) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER40_bp 0 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER41_bm (1<<1) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER41_bp 1 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER42_bm (1<<2) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER42_bp 2 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER43_bm (1<<3) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER43_bp 3 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER44_bm (1<<4) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER44_bp 4 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER45_bm (1<<5) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER45_bp 5 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER46_bm (1<<6) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER46_bp 6 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER47_bm (1<<7) /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER47_bp 7 /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER5 bit masks and bit positions */ +#define EVSYS_ASYNCUSER5_gm 0xFF /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */ +#define EVSYS_ASYNCUSER5_gp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */ +#define EVSYS_ASYNCUSER50_bm (1<<0) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER50_bp 0 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER51_bm (1<<1) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER51_bp 1 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER52_bm (1<<2) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER52_bp 2 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER53_bm (1<<3) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER53_bp 3 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER54_bm (1<<4) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER54_bp 4 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER55_bm (1<<5) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER55_bp 5 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER56_bm (1<<6) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER56_bp 6 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER57_bm (1<<7) /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER57_bp 7 /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER6 bit masks and bit positions */ +#define EVSYS_ASYNCUSER6_gm 0xFF /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */ +#define EVSYS_ASYNCUSER6_gp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */ +#define EVSYS_ASYNCUSER60_bm (1<<0) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER60_bp 0 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */ +#define EVSYS_ASYNCUSER61_bm (1<<1) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER61_bp 1 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */ +#define EVSYS_ASYNCUSER62_bm (1<<2) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER62_bp 2 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */ +#define EVSYS_ASYNCUSER63_bm (1<<3) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER63_bp 3 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */ +#define EVSYS_ASYNCUSER64_bm (1<<4) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER64_bp 4 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */ +#define EVSYS_ASYNCUSER65_bm (1<<5) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER65_bp 5 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */ +#define EVSYS_ASYNCUSER66_bm (1<<6) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER66_bp 6 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */ +#define EVSYS_ASYNCUSER67_bm (1<<7) /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER67_bp 7 /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER7 bit masks and bit positions */ +#define EVSYS_ASYNCUSER7_gm 0xFF /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */ +#define EVSYS_ASYNCUSER7_gp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */ +#define EVSYS_ASYNCUSER70_bm (1<<0) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER70_bp 0 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */ +#define EVSYS_ASYNCUSER71_bm (1<<1) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER71_bp 1 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */ +#define EVSYS_ASYNCUSER72_bm (1<<2) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER72_bp 2 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */ +#define EVSYS_ASYNCUSER73_bm (1<<3) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER73_bp 3 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */ +#define EVSYS_ASYNCUSER74_bm (1<<4) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER74_bp 4 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */ +#define EVSYS_ASYNCUSER75_bm (1<<5) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER75_bp 5 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */ +#define EVSYS_ASYNCUSER76_bm (1<<6) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER76_bp 6 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */ +#define EVSYS_ASYNCUSER77_bm (1<<7) /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER77_bp 7 /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER8 bit masks and bit positions */ +#define EVSYS_ASYNCUSER8_gm 0xFF /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */ +#define EVSYS_ASYNCUSER8_gp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */ +#define EVSYS_ASYNCUSER80_bm (1<<0) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */ +#define EVSYS_ASYNCUSER80_bp 0 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */ +#define EVSYS_ASYNCUSER81_bm (1<<1) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */ +#define EVSYS_ASYNCUSER81_bp 1 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */ +#define EVSYS_ASYNCUSER82_bm (1<<2) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */ +#define EVSYS_ASYNCUSER82_bp 2 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */ +#define EVSYS_ASYNCUSER83_bm (1<<3) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */ +#define EVSYS_ASYNCUSER83_bp 3 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */ +#define EVSYS_ASYNCUSER84_bm (1<<4) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */ +#define EVSYS_ASYNCUSER84_bp 4 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */ +#define EVSYS_ASYNCUSER85_bm (1<<5) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */ +#define EVSYS_ASYNCUSER85_bp 5 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */ +#define EVSYS_ASYNCUSER86_bm (1<<6) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */ +#define EVSYS_ASYNCUSER86_bp 6 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */ +#define EVSYS_ASYNCUSER87_bm (1<<7) /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */ +#define EVSYS_ASYNCUSER87_bp 7 /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */ + +/* EVSYS.ASYNCUSER9 bit masks and bit positions */ +#define EVSYS_ASYNCUSER9_gm 0xFF /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */ +#define EVSYS_ASYNCUSER9_gp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */ +#define EVSYS_ASYNCUSER90_bm (1<<0) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */ +#define EVSYS_ASYNCUSER90_bp 0 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */ +#define EVSYS_ASYNCUSER91_bm (1<<1) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */ +#define EVSYS_ASYNCUSER91_bp 1 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */ +#define EVSYS_ASYNCUSER92_bm (1<<2) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */ +#define EVSYS_ASYNCUSER92_bp 2 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */ +#define EVSYS_ASYNCUSER93_bm (1<<3) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */ +#define EVSYS_ASYNCUSER93_bp 3 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */ +#define EVSYS_ASYNCUSER94_bm (1<<4) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */ +#define EVSYS_ASYNCUSER94_bp 4 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */ +#define EVSYS_ASYNCUSER95_bm (1<<5) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */ +#define EVSYS_ASYNCUSER95_bp 5 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */ +#define EVSYS_ASYNCUSER96_bm (1<<6) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */ +#define EVSYS_ASYNCUSER96_bp 6 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */ +#define EVSYS_ASYNCUSER97_bm (1<<7) /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */ +#define EVSYS_ASYNCUSER97_bp 7 /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */ + +/* EVSYS.ASYNCUSER10 bit masks and bit positions */ +#define EVSYS_ASYNCUSER10_gm 0xFF /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */ +#define EVSYS_ASYNCUSER10_gp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */ +#define EVSYS_ASYNCUSER100_bm (1<<0) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */ +#define EVSYS_ASYNCUSER100_bp 0 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */ +#define EVSYS_ASYNCUSER101_bm (1<<1) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */ +#define EVSYS_ASYNCUSER101_bp 1 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */ +#define EVSYS_ASYNCUSER102_bm (1<<2) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */ +#define EVSYS_ASYNCUSER102_bp 2 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */ +#define EVSYS_ASYNCUSER103_bm (1<<3) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */ +#define EVSYS_ASYNCUSER103_bp 3 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */ +#define EVSYS_ASYNCUSER104_bm (1<<4) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */ +#define EVSYS_ASYNCUSER104_bp 4 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */ +#define EVSYS_ASYNCUSER105_bm (1<<5) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */ +#define EVSYS_ASYNCUSER105_bp 5 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */ +#define EVSYS_ASYNCUSER106_bm (1<<6) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */ +#define EVSYS_ASYNCUSER106_bp 6 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */ +#define EVSYS_ASYNCUSER107_bm (1<<7) /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */ +#define EVSYS_ASYNCUSER107_bp 7 /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */ + +/* EVSYS.SYNCUSER0 bit masks and bit positions */ +#define EVSYS_SYNCUSER0_gm 0xFF /* Synchronous User Ch 0 Input Selection - TCA0 group mask. */ +#define EVSYS_SYNCUSER0_gp 0 /* Synchronous User Ch 0 Input Selection - TCA0 group position. */ +#define EVSYS_SYNCUSER00_bm (1<<0) /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 mask. */ +#define EVSYS_SYNCUSER00_bp 0 /* Synchronous User Ch 0 Input Selection - TCA0 bit 0 position. */ +#define EVSYS_SYNCUSER01_bm (1<<1) /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 mask. */ +#define EVSYS_SYNCUSER01_bp 1 /* Synchronous User Ch 0 Input Selection - TCA0 bit 1 position. */ +#define EVSYS_SYNCUSER02_bm (1<<2) /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 mask. */ +#define EVSYS_SYNCUSER02_bp 2 /* Synchronous User Ch 0 Input Selection - TCA0 bit 2 position. */ +#define EVSYS_SYNCUSER03_bm (1<<3) /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 mask. */ +#define EVSYS_SYNCUSER03_bp 3 /* Synchronous User Ch 0 Input Selection - TCA0 bit 3 position. */ +#define EVSYS_SYNCUSER04_bm (1<<4) /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 mask. */ +#define EVSYS_SYNCUSER04_bp 4 /* Synchronous User Ch 0 Input Selection - TCA0 bit 4 position. */ +#define EVSYS_SYNCUSER05_bm (1<<5) /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 mask. */ +#define EVSYS_SYNCUSER05_bp 5 /* Synchronous User Ch 0 Input Selection - TCA0 bit 5 position. */ +#define EVSYS_SYNCUSER06_bm (1<<6) /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 mask. */ +#define EVSYS_SYNCUSER06_bp 6 /* Synchronous User Ch 0 Input Selection - TCA0 bit 6 position. */ +#define EVSYS_SYNCUSER07_bm (1<<7) /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 mask. */ +#define EVSYS_SYNCUSER07_bp 7 /* Synchronous User Ch 0 Input Selection - TCA0 bit 7 position. */ + +/* EVSYS.SYNCUSER1 bit masks and bit positions */ +#define EVSYS_SYNCUSER1_gm 0xFF /* Synchronous User Ch 1 Input Selection - USART0 group mask. */ +#define EVSYS_SYNCUSER1_gp 0 /* Synchronous User Ch 1 Input Selection - USART0 group position. */ +#define EVSYS_SYNCUSER10_bm (1<<0) /* Synchronous User Ch 1 Input Selection - USART0 bit 0 mask. */ +#define EVSYS_SYNCUSER10_bp 0 /* Synchronous User Ch 1 Input Selection - USART0 bit 0 position. */ +#define EVSYS_SYNCUSER11_bm (1<<1) /* Synchronous User Ch 1 Input Selection - USART0 bit 1 mask. */ +#define EVSYS_SYNCUSER11_bp 1 /* Synchronous User Ch 1 Input Selection - USART0 bit 1 position. */ +#define EVSYS_SYNCUSER12_bm (1<<2) /* Synchronous User Ch 1 Input Selection - USART0 bit 2 mask. */ +#define EVSYS_SYNCUSER12_bp 2 /* Synchronous User Ch 1 Input Selection - USART0 bit 2 position. */ +#define EVSYS_SYNCUSER13_bm (1<<3) /* Synchronous User Ch 1 Input Selection - USART0 bit 3 mask. */ +#define EVSYS_SYNCUSER13_bp 3 /* Synchronous User Ch 1 Input Selection - USART0 bit 3 position. */ +#define EVSYS_SYNCUSER14_bm (1<<4) /* Synchronous User Ch 1 Input Selection - USART0 bit 4 mask. */ +#define EVSYS_SYNCUSER14_bp 4 /* Synchronous User Ch 1 Input Selection - USART0 bit 4 position. */ +#define EVSYS_SYNCUSER15_bm (1<<5) /* Synchronous User Ch 1 Input Selection - USART0 bit 5 mask. */ +#define EVSYS_SYNCUSER15_bp 5 /* Synchronous User Ch 1 Input Selection - USART0 bit 5 position. */ +#define EVSYS_SYNCUSER16_bm (1<<6) /* Synchronous User Ch 1 Input Selection - USART0 bit 6 mask. */ +#define EVSYS_SYNCUSER16_bp 6 /* Synchronous User Ch 1 Input Selection - USART0 bit 6 position. */ +#define EVSYS_SYNCUSER17_bm (1<<7) /* Synchronous User Ch 1 Input Selection - USART0 bit 7 mask. */ +#define EVSYS_SYNCUSER17_bp 7 /* Synchronous User Ch 1 Input Selection - USART0 bit 7 position. */ + +/* FUSE - Fuses */ +/* FUSE.WDTCFG bit masks and bit positions */ +#define FUSE_PERIOD_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define FUSE_PERIOD_gp 0 /* Watchdog Timeout Period group position. */ +#define FUSE_PERIOD0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define FUSE_PERIOD0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define FUSE_PERIOD1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define FUSE_PERIOD1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define FUSE_PERIOD2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define FUSE_PERIOD2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define FUSE_PERIOD3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define FUSE_PERIOD3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +#define FUSE_WINDOW_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define FUSE_WINDOW_gp 4 /* Watchdog Window Timeout Period group position. */ +#define FUSE_WINDOW0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define FUSE_WINDOW0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define FUSE_WINDOW1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define FUSE_WINDOW1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define FUSE_WINDOW2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define FUSE_WINDOW2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define FUSE_WINDOW3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define FUSE_WINDOW3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +/* FUSE.BODCFG bit masks and bit positions */ +#define FUSE_SLEEP_gm 0x03 /* BOD Operation in Sleep Mode group mask. */ +#define FUSE_SLEEP_gp 0 /* BOD Operation in Sleep Mode group position. */ +#define FUSE_SLEEP0_bm (1<<0) /* BOD Operation in Sleep Mode bit 0 mask. */ +#define FUSE_SLEEP0_bp 0 /* BOD Operation in Sleep Mode bit 0 position. */ +#define FUSE_SLEEP1_bm (1<<1) /* BOD Operation in Sleep Mode bit 1 mask. */ +#define FUSE_SLEEP1_bp 1 /* BOD Operation in Sleep Mode bit 1 position. */ +#define FUSE_ACTIVE_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define FUSE_ACTIVE_gp 2 /* BOD Operation in Active Mode group position. */ +#define FUSE_ACTIVE0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define FUSE_ACTIVE0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define FUSE_ACTIVE1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define FUSE_ACTIVE1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +#define FUSE_SAMPFREQ_bm 0x10 /* BOD Sample Frequency bit mask. */ +#define FUSE_SAMPFREQ_bp 4 /* BOD Sample Frequency bit position. */ +#define FUSE_LVL_gm 0xE0 /* BOD Level group mask. */ +#define FUSE_LVL_gp 5 /* BOD Level group position. */ +#define FUSE_LVL0_bm (1<<5) /* BOD Level bit 0 mask. */ +#define FUSE_LVL0_bp 5 /* BOD Level bit 0 position. */ +#define FUSE_LVL1_bm (1<<6) /* BOD Level bit 1 mask. */ +#define FUSE_LVL1_bp 6 /* BOD Level bit 1 position. */ +#define FUSE_LVL2_bm (1<<7) /* BOD Level bit 2 mask. */ +#define FUSE_LVL2_bp 7 /* BOD Level bit 2 position. */ + +/* FUSE.OSCCFG bit masks and bit positions */ +#define FUSE_FREQSEL_gm 0x03 /* Frequency Select group mask. */ +#define FUSE_FREQSEL_gp 0 /* Frequency Select group position. */ +#define FUSE_FREQSEL0_bm (1<<0) /* Frequency Select bit 0 mask. */ +#define FUSE_FREQSEL0_bp 0 /* Frequency Select bit 0 position. */ +#define FUSE_FREQSEL1_bm (1<<1) /* Frequency Select bit 1 mask. */ +#define FUSE_FREQSEL1_bp 1 /* Frequency Select bit 1 position. */ +#define FUSE_OSCLOCK_bm 0x80 /* Oscillator Lock bit mask. */ +#define FUSE_OSCLOCK_bp 7 /* Oscillator Lock bit position. */ + +/* FUSE.TCD0CFG bit masks and bit positions */ +#define FUSE_CMPA_bm 0x01 /* Compare A Default Output Value bit mask. */ +#define FUSE_CMPA_bp 0 /* Compare A Default Output Value bit position. */ +#define FUSE_CMPB_bm 0x02 /* Compare B Default Output Value bit mask. */ +#define FUSE_CMPB_bp 1 /* Compare B Default Output Value bit position. */ +#define FUSE_CMPC_bm 0x04 /* Compare C Default Output Value bit mask. */ +#define FUSE_CMPC_bp 2 /* Compare C Default Output Value bit position. */ +#define FUSE_CMPD_bm 0x08 /* Compare D Default Output Value bit mask. */ +#define FUSE_CMPD_bp 3 /* Compare D Default Output Value bit position. */ +#define FUSE_CMPAEN_bm 0x10 /* Compare A Output Enable bit mask. */ +#define FUSE_CMPAEN_bp 4 /* Compare A Output Enable bit position. */ +#define FUSE_CMPBEN_bm 0x20 /* Compare B Output Enable bit mask. */ +#define FUSE_CMPBEN_bp 5 /* Compare B Output Enable bit position. */ +#define FUSE_CMPCEN_bm 0x40 /* Compare C Output Enable bit mask. */ +#define FUSE_CMPCEN_bp 6 /* Compare C Output Enable bit position. */ +#define FUSE_CMPDEN_bm 0x80 /* Compare D Output Enable bit mask. */ +#define FUSE_CMPDEN_bp 7 /* Compare D Output Enable bit position. */ + +/* FUSE.SYSCFG0 bit masks and bit positions */ +#define FUSE_EESAVE_bm 0x01 /* EEPROM Save bit mask. */ +#define FUSE_EESAVE_bp 0 /* EEPROM Save bit position. */ +#define FUSE_RSTPINCFG_gm 0x0C /* Reset Pin Configuration group mask. */ +#define FUSE_RSTPINCFG_gp 2 /* Reset Pin Configuration group position. */ +#define FUSE_RSTPINCFG0_bm (1<<2) /* Reset Pin Configuration bit 0 mask. */ +#define FUSE_RSTPINCFG0_bp 2 /* Reset Pin Configuration bit 0 position. */ +#define FUSE_RSTPINCFG1_bm (1<<3) /* Reset Pin Configuration bit 1 mask. */ +#define FUSE_RSTPINCFG1_bp 3 /* Reset Pin Configuration bit 1 position. */ +#define FUSE_CRCSRC_gm 0xC0 /* CRC Source group mask. */ +#define FUSE_CRCSRC_gp 6 /* CRC Source group position. */ +#define FUSE_CRCSRC0_bm (1<<6) /* CRC Source bit 0 mask. */ +#define FUSE_CRCSRC0_bp 6 /* CRC Source bit 0 position. */ +#define FUSE_CRCSRC1_bm (1<<7) /* CRC Source bit 1 mask. */ +#define FUSE_CRCSRC1_bp 7 /* CRC Source bit 1 position. */ + +/* FUSE.SYSCFG1 bit masks and bit positions */ +#define FUSE_SUT_gm 0x07 /* Startup Time group mask. */ +#define FUSE_SUT_gp 0 /* Startup Time group position. */ +#define FUSE_SUT0_bm (1<<0) /* Startup Time bit 0 mask. */ +#define FUSE_SUT0_bp 0 /* Startup Time bit 0 position. */ +#define FUSE_SUT1_bm (1<<1) /* Startup Time bit 1 mask. */ +#define FUSE_SUT1_bp 1 /* Startup Time bit 1 position. */ +#define FUSE_SUT2_bm (1<<2) /* Startup Time bit 2 mask. */ +#define FUSE_SUT2_bp 2 /* Startup Time bit 2 position. */ + + + + + + + +/* LOCKBIT - Lockbit */ +/* LOCKBIT.LOCKBIT bit masks and bit positions */ +#define LOCKBIT_LB_gm 0xFF /* Lock Bits group mask. */ +#define LOCKBIT_LB_gp 0 /* Lock Bits group position. */ +#define LOCKBIT_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define LOCKBIT_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define LOCKBIT_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define LOCKBIT_LB1_bp 1 /* Lock Bits bit 1 position. */ +#define LOCKBIT_LB2_bm (1<<2) /* Lock Bits bit 2 mask. */ +#define LOCKBIT_LB2_bp 2 /* Lock Bits bit 2 position. */ +#define LOCKBIT_LB3_bm (1<<3) /* Lock Bits bit 3 mask. */ +#define LOCKBIT_LB3_bp 3 /* Lock Bits bit 3 position. */ +#define LOCKBIT_LB4_bm (1<<4) /* Lock Bits bit 4 mask. */ +#define LOCKBIT_LB4_bp 4 /* Lock Bits bit 4 position. */ +#define LOCKBIT_LB5_bm (1<<5) /* Lock Bits bit 5 mask. */ +#define LOCKBIT_LB5_bp 5 /* Lock Bits bit 5 position. */ +#define LOCKBIT_LB6_bm (1<<6) /* Lock Bits bit 6 mask. */ +#define LOCKBIT_LB6_bp 6 /* Lock Bits bit 6 position. */ +#define LOCKBIT_LB7_bm (1<<7) /* Lock Bits bit 7 mask. */ +#define LOCKBIT_LB7_bp 7 /* Lock Bits bit 7 position. */ + +/* NVMCTRL - Non-volatile Memory Controller */ +/* NVMCTRL.CTRLA bit masks and bit positions */ +#define NVMCTRL_CMD_gm 0x07 /* Command group mask. */ +#define NVMCTRL_CMD_gp 0 /* Command group position. */ +#define NVMCTRL_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVMCTRL_CMD0_bp 0 /* Command bit 0 position. */ +#define NVMCTRL_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVMCTRL_CMD1_bp 1 /* Command bit 1 position. */ +#define NVMCTRL_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVMCTRL_CMD2_bp 2 /* Command bit 2 position. */ + +/* NVMCTRL.CTRLB bit masks and bit positions */ +#define NVMCTRL_APCWP_bm 0x01 /* Application code write protect bit mask. */ +#define NVMCTRL_APCWP_bp 0 /* Application code write protect bit position. */ +#define NVMCTRL_BOOTLOCK_bm 0x02 /* Boot Lock bit mask. */ +#define NVMCTRL_BOOTLOCK_bp 1 /* Boot Lock bit position. */ + +/* NVMCTRL.STATUS bit masks and bit positions */ +#define NVMCTRL_FBUSY_bm 0x01 /* Flash busy bit mask. */ +#define NVMCTRL_FBUSY_bp 0 /* Flash busy bit position. */ +#define NVMCTRL_EEBUSY_bm 0x02 /* EEPROM busy bit mask. */ +#define NVMCTRL_EEBUSY_bp 1 /* EEPROM busy bit position. */ +#define NVMCTRL_WRERROR_bm 0x04 /* Write error bit mask. */ +#define NVMCTRL_WRERROR_bp 2 /* Write error bit position. */ + +/* NVMCTRL.INTCTRL bit masks and bit positions */ +#define NVMCTRL_EEREADY_bm 0x01 /* EEPROM Ready bit mask. */ +#define NVMCTRL_EEREADY_bp 0 /* EEPROM Ready bit position. */ + +/* NVMCTRL.INTFLAGS bit masks and bit positions */ +/* NVMCTRL_EEREADY is already defined. */ + + + + + + + + + + + + +/* PORT - I/O Ports */ +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define PORT_INT_gp 0 /* Pin Interrupt group position. */ +#define PORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define PORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define PORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define PORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define PORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define PORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define PORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define PORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define PORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define PORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define PORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define PORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define PORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define PORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define PORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define PORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +#define PORT_PULLUPEN_bm 0x08 /* Pullup enable bit mask. */ +#define PORT_PULLUPEN_bp 3 /* Pullup enable bit position. */ +#define PORT_INVEN_bm 0x80 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 7 /* Inverted I/O Enable bit position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_ISC is already defined. */ +/* PORT_PULLUPEN is already defined. */ +/* PORT_INVEN is already defined. */ + +/* PORTMUX - Port Multiplexer */ +/* PORTMUX.CTRLA bit masks and bit positions */ +#define PORTMUX_EVOUT0_bm 0x01 /* Event Output 0 bit mask. */ +#define PORTMUX_EVOUT0_bp 0 /* Event Output 0 bit position. */ +#define PORTMUX_EVOUT1_bm 0x02 /* Event Output 1 bit mask. */ +#define PORTMUX_EVOUT1_bp 1 /* Event Output 1 bit position. */ +#define PORTMUX_EVOUT2_bm 0x04 /* Event Output 2 bit mask. */ +#define PORTMUX_EVOUT2_bp 2 /* Event Output 2 bit position. */ +#define PORTMUX_LUT0_bm 0x10 /* Configurable Custom Logic LUT0 bit mask. */ +#define PORTMUX_LUT0_bp 4 /* Configurable Custom Logic LUT0 bit position. */ +#define PORTMUX_LUT1_bm 0x20 /* Configurable Custom Logic LUT1 bit mask. */ +#define PORTMUX_LUT1_bp 5 /* Configurable Custom Logic LUT1 bit position. */ + +/* PORTMUX.CTRLB bit masks and bit positions */ +#define PORTMUX_USART0_bm 0x01 /* Port Multiplexer USART0 bit mask. */ +#define PORTMUX_USART0_bp 0 /* Port Multiplexer USART0 bit position. */ +#define PORTMUX_SPI0_bm 0x04 /* Port Multiplexer SPI0 bit mask. */ +#define PORTMUX_SPI0_bp 2 /* Port Multiplexer SPI0 bit position. */ +#define PORTMUX_TWI0_bm 0x10 /* Port Multiplexer TWI0 bit mask. */ +#define PORTMUX_TWI0_bp 4 /* Port Multiplexer TWI0 bit position. */ + +/* PORTMUX.CTRLC bit masks and bit positions */ +#define PORTMUX_TCA00_bm 0x01 /* Port Multiplexer TCA0 Output 0 bit mask. */ +#define PORTMUX_TCA00_bp 0 /* Port Multiplexer TCA0 Output 0 bit position. */ +#define PORTMUX_TCA01_bm 0x02 /* Port Multiplexer TCA0 Output 1 bit mask. */ +#define PORTMUX_TCA01_bp 1 /* Port Multiplexer TCA0 Output 1 bit position. */ +#define PORTMUX_TCA02_bm 0x04 /* Port Multiplexer TCA0 Output 2 bit mask. */ +#define PORTMUX_TCA02_bp 2 /* Port Multiplexer TCA0 Output 2 bit position. */ +#define PORTMUX_TCA03_bm 0x08 /* Port Multiplexer TCA0 Output 3 bit mask. */ +#define PORTMUX_TCA03_bp 3 /* Port Multiplexer TCA0 Output 3 bit position. */ +#define PORTMUX_TCA04_bm 0x10 /* Port Multiplexer TCA0 Output 4 bit mask. */ +#define PORTMUX_TCA04_bp 4 /* Port Multiplexer TCA0 Output 4 bit position. */ +#define PORTMUX_TCA05_bm 0x20 /* Port Multiplexer TCA0 Output 5 bit mask. */ +#define PORTMUX_TCA05_bp 5 /* Port Multiplexer TCA0 Output 5 bit position. */ + +/* PORTMUX.CTRLD bit masks and bit positions */ +#define PORTMUX_TCB0_bm 0x01 /* Port Multiplexer TCB bit mask. */ +#define PORTMUX_TCB0_bp 0 /* Port Multiplexer TCB bit position. */ + +/* RSTCTRL - Reset controller */ +/* RSTCTRL.RSTFR bit masks and bit positions */ +#define RSTCTRL_PORF_bm 0x01 /* Power on Reset flag bit mask. */ +#define RSTCTRL_PORF_bp 0 /* Power on Reset flag bit position. */ +#define RSTCTRL_BORF_bm 0x02 /* Brown out detector Reset flag bit mask. */ +#define RSTCTRL_BORF_bp 1 /* Brown out detector Reset flag bit position. */ +#define RSTCTRL_EXTRF_bm 0x04 /* External Reset flag bit mask. */ +#define RSTCTRL_EXTRF_bp 2 /* External Reset flag bit position. */ +#define RSTCTRL_WDRF_bm 0x08 /* Watch dog Reset flag bit mask. */ +#define RSTCTRL_WDRF_bp 3 /* Watch dog Reset flag bit position. */ +#define RSTCTRL_SWRF_bm 0x10 /* Software Reset flag bit mask. */ +#define RSTCTRL_SWRF_bp 4 /* Software Reset flag bit position. */ +#define RSTCTRL_UPDIRF_bm 0x20 /* UPDI Reset flag bit mask. */ +#define RSTCTRL_UPDIRF_bp 5 /* UPDI Reset flag bit position. */ + +/* RSTCTRL.SWRR bit masks and bit positions */ +#define RSTCTRL_SWRE_bm 0x01 /* Software reset enable bit mask. */ +#define RSTCTRL_SWRE_bp 0 /* Software reset enable bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRLA bit masks and bit positions */ +#define RTC_RTCEN_bm 0x01 /* Enable bit mask. */ +#define RTC_RTCEN_bp 0 /* Enable bit position. */ +#define RTC_PRESCALER_gm 0x78 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 3 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<3) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 3 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<4) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 4 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<5) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 5 /* Prescaling Factor bit 2 position. */ +#define RTC_PRESCALER3_bm (1<<6) /* Prescaling Factor bit 3 mask. */ +#define RTC_PRESCALER3_bp 6 /* Prescaling Factor bit 3 position. */ +#define RTC_RUNSTDBY_bm 0x80 /* Run In Standby bit mask. */ +#define RTC_RUNSTDBY_bp 7 /* Run In Standby bit position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_CTRLABUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLABUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ +#define RTC_CNTBUSY_bm 0x02 /* Count Synchronization Busy Flag bit mask. */ +#define RTC_CNTBUSY_bp 1 /* Count Synchronization Busy Flag bit position. */ +#define RTC_PERBUSY_bm 0x04 /* Period Synchronization Busy Flag bit mask. */ +#define RTC_PERBUSY_bp 2 /* Period Synchronization Busy Flag bit position. */ +#define RTC_CMPBUSY_bm 0x08 /* Comparator Synchronization Busy Flag bit mask. */ +#define RTC_CMPBUSY_bp 3 /* Comparator Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_OVF_bm 0x01 /* Overflow Interrupt enable bit mask. */ +#define RTC_OVF_bp 0 /* Overflow Interrupt enable bit position. */ +#define RTC_CMP_bm 0x02 /* Compare Match Interrupt enable bit mask. */ +#define RTC_CMP_bp 1 /* Compare Match Interrupt enable bit position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +/* RTC_OVF is already defined. */ +/* RTC_CMP is already defined. */ + + +/* RTC.DBGCTRL bit masks and bit positions */ +#define RTC_DBGRUN_bm 0x01 /* Run in debug bit mask. */ +#define RTC_DBGRUN_bp 0 /* Run in debug bit position. */ + +/* RTC.CLKSEL bit masks and bit positions */ +#define RTC_CLKSEL_gm 0x03 /* Clock Select group mask. */ +#define RTC_CLKSEL_gp 0 /* Clock Select group position. */ +#define RTC_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define RTC_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define RTC_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define RTC_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ + + + + +/* RTC.PITCTRLA bit masks and bit positions */ +#define RTC_PITEN_bm 0x01 /* Enable bit mask. */ +#define RTC_PITEN_bp 0 /* Enable bit position. */ +#define RTC_PERIOD_gm 0x78 /* Period group mask. */ +#define RTC_PERIOD_gp 3 /* Period group position. */ +#define RTC_PERIOD0_bm (1<<3) /* Period bit 0 mask. */ +#define RTC_PERIOD0_bp 3 /* Period bit 0 position. */ +#define RTC_PERIOD1_bm (1<<4) /* Period bit 1 mask. */ +#define RTC_PERIOD1_bp 4 /* Period bit 1 position. */ +#define RTC_PERIOD2_bm (1<<5) /* Period bit 2 mask. */ +#define RTC_PERIOD2_bp 5 /* Period bit 2 position. */ +#define RTC_PERIOD3_bm (1<<6) /* Period bit 3 mask. */ +#define RTC_PERIOD3_bp 6 /* Period bit 3 position. */ + +/* RTC.PITSTATUS bit masks and bit positions */ +#define RTC_CTRLBUSY_bm 0x01 /* CTRLA Synchronization Busy Flag bit mask. */ +#define RTC_CTRLBUSY_bp 0 /* CTRLA Synchronization Busy Flag bit position. */ + +/* RTC.PITINTCTRL bit masks and bit positions */ +#define RTC_PI_bm 0x01 /* Periodic Interrupt bit mask. */ +#define RTC_PI_bp 0 /* Periodic Interrupt bit position. */ + +/* RTC.PITINTFLAGS bit masks and bit positions */ +/* RTC_PI is already defined. */ + +/* RTC.PITDBGCTRL bit masks and bit positions */ +/* RTC_DBGRUN is already defined. */ + + + + + + + + + + + + + + + + + + + + +/* SLPCTRL - Sleep Controller */ +/* SLPCTRL.CTRLA bit masks and bit positions */ +#define SLPCTRL_SEN_bm 0x01 /* Sleep enable bit mask. */ +#define SLPCTRL_SEN_bp 0 /* Sleep enable bit position. */ +#define SLPCTRL_SMODE_gm 0x06 /* Sleep mode group mask. */ +#define SLPCTRL_SMODE_gp 1 /* Sleep mode group position. */ +#define SLPCTRL_SMODE0_bm (1<<1) /* Sleep mode bit 0 mask. */ +#define SLPCTRL_SMODE0_bp 1 /* Sleep mode bit 0 position. */ +#define SLPCTRL_SMODE1_bm (1<<2) /* Sleep mode bit 1 mask. */ +#define SLPCTRL_SMODE1_bp 2 /* Sleep mode bit 1 position. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRLA bit masks and bit positions */ +#define SPI_ENABLE_bm 0x01 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 0 /* Enable Module bit position. */ +#define SPI_PRESC_gm 0x06 /* Prescaler group mask. */ +#define SPI_PRESC_gp 1 /* Prescaler group position. */ +#define SPI_PRESC0_bm (1<<1) /* Prescaler bit 0 mask. */ +#define SPI_PRESC0_bp 1 /* Prescaler bit 0 position. */ +#define SPI_PRESC1_bm (1<<2) /* Prescaler bit 1 mask. */ +#define SPI_PRESC1_bp 2 /* Prescaler bit 1 position. */ +#define SPI_CLK2X_bm 0x10 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 4 /* Enable Double Speed bit position. */ +#define SPI_MASTER_bm 0x20 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 5 /* Master Operation Enable bit position. */ +#define SPI_DORD_bm 0x40 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 6 /* Data Order Setting bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_MODE_gm 0x03 /* SPI Mode group mask. */ +#define SPI_MODE_gp 0 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<0) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 0 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<1) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 1 /* SPI Mode bit 1 position. */ +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ +#define SPI_BUFWR_bm 0x40 /* Buffer Write Mode bit mask. */ +#define SPI_BUFWR_bp 6 /* Buffer Write Mode bit position. */ +#define SPI_BUFEN_bm 0x80 /* Buffer Mode Enable bit mask. */ +#define SPI_BUFEN_bp 7 /* Buffer Mode Enable bit position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_IE_bm 0x01 /* Interrupt Enable bit mask. */ +#define SPI_IE_bp 0 /* Interrupt Enable bit position. */ +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable bit position. */ +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define SPI_TXCIE_bm 0x40 /* Transfer Complete Interrupt Enable bit mask. */ +#define SPI_TXCIE_bp 6 /* Transfer Complete Interrupt Enable bit position. */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* SPI.INTFLAGS bit masks and bit positions */ +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow bit position. */ +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag bit position. */ +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag bit position. */ +#define SPI_TXCIF_bm 0x40 /* Transfer Complete Interrupt Flag bit mask. */ +#define SPI_TXCIF_bp 6 /* Transfer Complete Interrupt Flag bit position. */ +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + + + +/* SYSCFG - System Configuration Registers */ +/* SYSCFG.EXTBRK bit masks and bit positions */ +#define SYSCFG_ENEXTBRK_bm 0x01 /* External break enable bit mask. */ +#define SYSCFG_ENEXTBRK_bp 0 /* External break enable bit position. */ + +/* TCA - 16-bit Timer/Counter Type A */ +/* TCA_SINGLE.CTRLA bit masks and bit positions */ +#define TCA_SINGLE_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SINGLE_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SINGLE_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SINGLE_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SINGLE_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SINGLE_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SINGLE_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SINGLE_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SINGLE_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SINGLE_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SINGLE.CTRLB bit masks and bit positions */ +#define TCA_SINGLE_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TCA_SINGLE_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCA_SINGLE_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCA_SINGLE_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCA_SINGLE_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCA_SINGLE_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TCA_SINGLE_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TCA_SINGLE_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +#define TCA_SINGLE_ALUPD_bm 0x08 /* Auto Lock Update bit mask. */ +#define TCA_SINGLE_ALUPD_bp 3 /* Auto Lock Update bit position. */ +#define TCA_SINGLE_CMP0EN_bm 0x10 /* Compare 0 Enable bit mask. */ +#define TCA_SINGLE_CMP0EN_bp 4 /* Compare 0 Enable bit position. */ +#define TCA_SINGLE_CMP1EN_bm 0x20 /* Compare 1 Enable bit mask. */ +#define TCA_SINGLE_CMP1EN_bp 5 /* Compare 1 Enable bit position. */ +#define TCA_SINGLE_CMP2EN_bm 0x40 /* Compare 2 Enable bit mask. */ +#define TCA_SINGLE_CMP2EN_bp 6 /* Compare 2 Enable bit position. */ + +/* TCA_SINGLE.CTRLC bit masks and bit positions */ +#define TCA_SINGLE_CMP0OV_bm 0x01 /* Compare 0 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP0OV_bp 0 /* Compare 0 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP1OV_bm 0x02 /* Compare 1 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP1OV_bp 1 /* Compare 1 Waveform Output Value bit position. */ +#define TCA_SINGLE_CMP2OV_bm 0x04 /* Compare 2 Waveform Output Value bit mask. */ +#define TCA_SINGLE_CMP2OV_bp 2 /* Compare 2 Waveform Output Value bit position. */ + +/* TCA_SINGLE.CTRLD bit masks and bit positions */ +#define TCA_SINGLE_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SINGLE_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SINGLE.CTRLECLR bit masks and bit positions */ +#define TCA_SINGLE_DIR_bm 0x01 /* Direction bit mask. */ +#define TCA_SINGLE_DIR_bp 0 /* Direction bit position. */ +#define TCA_SINGLE_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TCA_SINGLE_LUPD_bp 1 /* Lock Update bit position. */ +#define TCA_SINGLE_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SINGLE_CMD_gp 2 /* Command group position. */ +#define TCA_SINGLE_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SINGLE_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SINGLE_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SINGLE_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SINGLE.CTRLESET bit masks and bit positions */ +/* TCA_SINGLE_DIR is already defined. */ +/* TCA_SINGLE_LUPD is already defined. */ +/* TCA_SINGLE_CMD is already defined. */ + +/* TCA_SINGLE.CTRLFCLR bit masks and bit positions */ +#define TCA_SINGLE_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TCA_SINGLE_PERBV_bp 0 /* Period Buffer Valid bit position. */ +#define TCA_SINGLE_CMP0BV_bm 0x02 /* Compare 0 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP0BV_bp 1 /* Compare 0 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP1BV_bm 0x04 /* Compare 1 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP1BV_bp 2 /* Compare 1 Buffer Valid bit position. */ +#define TCA_SINGLE_CMP2BV_bm 0x08 /* Compare 2 Buffer Valid bit mask. */ +#define TCA_SINGLE_CMP2BV_bp 3 /* Compare 2 Buffer Valid bit position. */ + +/* TCA_SINGLE.CTRLFSET bit masks and bit positions */ +/* TCA_SINGLE_PERBV is already defined. */ +/* TCA_SINGLE_CMP0BV is already defined. */ +/* TCA_SINGLE_CMP1BV is already defined. */ +/* TCA_SINGLE_CMP2BV is already defined. */ + +/* TCA_SINGLE.EVCTRL bit masks and bit positions */ +#define TCA_SINGLE_CNTEI_bm 0x01 /* Count on Event Input bit mask. */ +#define TCA_SINGLE_CNTEI_bp 0 /* Count on Event Input bit position. */ +#define TCA_SINGLE_EVACT_gm 0x06 /* Event Action group mask. */ +#define TCA_SINGLE_EVACT_gp 1 /* Event Action group position. */ +#define TCA_SINGLE_EVACT0_bm (1<<1) /* Event Action bit 0 mask. */ +#define TCA_SINGLE_EVACT0_bp 1 /* Event Action bit 0 position. */ +#define TCA_SINGLE_EVACT1_bm (1<<2) /* Event Action bit 1 mask. */ +#define TCA_SINGLE_EVACT1_bp 2 /* Event Action bit 1 position. */ + +/* TCA_SINGLE.INTCTRL bit masks and bit positions */ +#define TCA_SINGLE_OVF_bm 0x01 /* Overflow Interrupt bit mask. */ +#define TCA_SINGLE_OVF_bp 0 /* Overflow Interrupt bit position. */ +#define TCA_SINGLE_CMP0_bm 0x10 /* Compare 0 Interrupt bit mask. */ +#define TCA_SINGLE_CMP0_bp 4 /* Compare 0 Interrupt bit position. */ +#define TCA_SINGLE_CMP1_bm 0x20 /* Compare 1 Interrupt bit mask. */ +#define TCA_SINGLE_CMP1_bp 5 /* Compare 1 Interrupt bit position. */ +#define TCA_SINGLE_CMP2_bm 0x40 /* Compare 2 Interrupt bit mask. */ +#define TCA_SINGLE_CMP2_bp 6 /* Compare 2 Interrupt bit position. */ + +/* TCA_SINGLE.INTFLAGS bit masks and bit positions */ +/* TCA_SINGLE_OVF is already defined. */ +/* TCA_SINGLE_CMP0 is already defined. */ +/* TCA_SINGLE_CMP1 is already defined. */ +/* TCA_SINGLE_CMP2 is already defined. */ + +/* TCA_SINGLE.DBGCTRL bit masks and bit positions */ +#define TCA_SINGLE_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SINGLE_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCA_SPLIT.CTRLA bit masks and bit positions */ +#define TCA_SPLIT_ENABLE_bm 0x01 /* Module Enable bit mask. */ +#define TCA_SPLIT_ENABLE_bp 0 /* Module Enable bit position. */ +#define TCA_SPLIT_CLKSEL_gm 0x0E /* Clock Selection group mask. */ +#define TCA_SPLIT_CLKSEL_gp 1 /* Clock Selection group position. */ +#define TCA_SPLIT_CLKSEL0_bm (1<<1) /* Clock Selection bit 0 mask. */ +#define TCA_SPLIT_CLKSEL0_bp 1 /* Clock Selection bit 0 position. */ +#define TCA_SPLIT_CLKSEL1_bm (1<<2) /* Clock Selection bit 1 mask. */ +#define TCA_SPLIT_CLKSEL1_bp 2 /* Clock Selection bit 1 position. */ +#define TCA_SPLIT_CLKSEL2_bm (1<<3) /* Clock Selection bit 2 mask. */ +#define TCA_SPLIT_CLKSEL2_bp 3 /* Clock Selection bit 2 position. */ + +/* TCA_SPLIT.CTRLB bit masks and bit positions */ +#define TCA_SPLIT_LCMP0EN_bm 0x01 /* Low Compare 0 Enable bit mask. */ +#define TCA_SPLIT_LCMP0EN_bp 0 /* Low Compare 0 Enable bit position. */ +#define TCA_SPLIT_LCMP1EN_bm 0x02 /* Low Compare 1 Enable bit mask. */ +#define TCA_SPLIT_LCMP1EN_bp 1 /* Low Compare 1 Enable bit position. */ +#define TCA_SPLIT_LCMP2EN_bm 0x04 /* Low Compare 2 Enable bit mask. */ +#define TCA_SPLIT_LCMP2EN_bp 2 /* Low Compare 2 Enable bit position. */ +#define TCA_SPLIT_HCMP0EN_bm 0x10 /* High Compare 0 Enable bit mask. */ +#define TCA_SPLIT_HCMP0EN_bp 4 /* High Compare 0 Enable bit position. */ +#define TCA_SPLIT_HCMP1EN_bm 0x20 /* High Compare 1 Enable bit mask. */ +#define TCA_SPLIT_HCMP1EN_bp 5 /* High Compare 1 Enable bit position. */ +#define TCA_SPLIT_HCMP2EN_bm 0x40 /* High Compare 2 Enable bit mask. */ +#define TCA_SPLIT_HCMP2EN_bp 6 /* High Compare 2 Enable bit position. */ + +/* TCA_SPLIT.CTRLC bit masks and bit positions */ +#define TCA_SPLIT_LCMP0OV_bm 0x01 /* Low Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_LCMP0OV_bp 0 /* Low Compare 0 Output Value bit position. */ +#define TCA_SPLIT_LCMP1OV_bm 0x02 /* Low Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_LCMP1OV_bp 1 /* Low Compare 1 Output Value bit position. */ +#define TCA_SPLIT_LCMP2OV_bm 0x04 /* Low Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_LCMP2OV_bp 2 /* Low Compare 2 Output Value bit position. */ +#define TCA_SPLIT_HCMP0OV_bm 0x10 /* High Compare 0 Output Value bit mask. */ +#define TCA_SPLIT_HCMP0OV_bp 4 /* High Compare 0 Output Value bit position. */ +#define TCA_SPLIT_HCMP1OV_bm 0x20 /* High Compare 1 Output Value bit mask. */ +#define TCA_SPLIT_HCMP1OV_bp 5 /* High Compare 1 Output Value bit position. */ +#define TCA_SPLIT_HCMP2OV_bm 0x40 /* High Compare 2 Output Value bit mask. */ +#define TCA_SPLIT_HCMP2OV_bp 6 /* High Compare 2 Output Value bit position. */ + +/* TCA_SPLIT.CTRLD bit masks and bit positions */ +#define TCA_SPLIT_SPLITM_bm 0x01 /* Split Mode Enable bit mask. */ +#define TCA_SPLIT_SPLITM_bp 0 /* Split Mode Enable bit position. */ + +/* TCA_SPLIT.CTRLECLR bit masks and bit positions */ +#define TCA_SPLIT_CMD_gm 0x0C /* Command group mask. */ +#define TCA_SPLIT_CMD_gp 2 /* Command group position. */ +#define TCA_SPLIT_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TCA_SPLIT_CMD0_bp 2 /* Command bit 0 position. */ +#define TCA_SPLIT_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TCA_SPLIT_CMD1_bp 3 /* Command bit 1 position. */ + +/* TCA_SPLIT.CTRLESET bit masks and bit positions */ +/* TCA_SPLIT_CMD is already defined. */ + +/* TCA_SPLIT.INTCTRL bit masks and bit positions */ +#define TCA_SPLIT_LUNF_bm 0x01 /* Low Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_LUNF_bp 0 /* Low Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_HUNF_bm 0x02 /* High Underflow Interrupt Enable bit mask. */ +#define TCA_SPLIT_HUNF_bp 1 /* High Underflow Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP0_bm 0x10 /* Low Compare 0 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP0_bp 4 /* Low Compare 0 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP1_bm 0x20 /* Low Compare 1 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP1_bp 5 /* Low Compare 1 Interrupt Enable bit position. */ +#define TCA_SPLIT_LCMP2_bm 0x40 /* Low Compare 2 Interrupt Enable bit mask. */ +#define TCA_SPLIT_LCMP2_bp 6 /* Low Compare 2 Interrupt Enable bit position. */ + +/* TCA_SPLIT.INTFLAGS bit masks and bit positions */ +/* TCA_SPLIT_LUNF is already defined. */ +/* TCA_SPLIT_HUNF is already defined. */ +/* TCA_SPLIT_LCMP0 is already defined. */ +/* TCA_SPLIT_LCMP1 is already defined. */ +/* TCA_SPLIT_LCMP2 is already defined. */ + +/* TCA_SPLIT.DBGCTRL bit masks and bit positions */ +#define TCA_SPLIT_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCA_SPLIT_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + + + + + + + + +/* TCB - 16-bit Timer Type B */ +/* TCB.CTRLA bit masks and bit positions */ +#define TCB_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCB_ENABLE_bp 0 /* Enable bit position. */ +#define TCB_CLKSEL_gm 0x06 /* Clock Select group mask. */ +#define TCB_CLKSEL_gp 1 /* Clock Select group position. */ +#define TCB_CLKSEL0_bm (1<<1) /* Clock Select bit 0 mask. */ +#define TCB_CLKSEL0_bp 1 /* Clock Select bit 0 position. */ +#define TCB_CLKSEL1_bm (1<<2) /* Clock Select bit 1 mask. */ +#define TCB_CLKSEL1_bp 2 /* Clock Select bit 1 position. */ +#define TCB_SYNCUPD_bm 0x10 /* Synchronize Update bit mask. */ +#define TCB_SYNCUPD_bp 4 /* Synchronize Update bit position. */ +#define TCB_RUNSTDBY_bm 0x40 /* Run Standby bit mask. */ +#define TCB_RUNSTDBY_bp 6 /* Run Standby bit position. */ + +/* TCB.CTRLB bit masks and bit positions */ +#define TCB_CNTMODE_gm 0x07 /* Timer Mode group mask. */ +#define TCB_CNTMODE_gp 0 /* Timer Mode group position. */ +#define TCB_CNTMODE0_bm (1<<0) /* Timer Mode bit 0 mask. */ +#define TCB_CNTMODE0_bp 0 /* Timer Mode bit 0 position. */ +#define TCB_CNTMODE1_bm (1<<1) /* Timer Mode bit 1 mask. */ +#define TCB_CNTMODE1_bp 1 /* Timer Mode bit 1 position. */ +#define TCB_CNTMODE2_bm (1<<2) /* Timer Mode bit 2 mask. */ +#define TCB_CNTMODE2_bp 2 /* Timer Mode bit 2 position. */ +#define TCB_CCMPEN_bm 0x10 /* Pin Output Enable bit mask. */ +#define TCB_CCMPEN_bp 4 /* Pin Output Enable bit position. */ +#define TCB_CCMPINIT_bm 0x20 /* Pin Initial State bit mask. */ +#define TCB_CCMPINIT_bp 5 /* Pin Initial State bit position. */ +#define TCB_ASYNC_bm 0x40 /* Asynchronous Enable bit mask. */ +#define TCB_ASYNC_bp 6 /* Asynchronous Enable bit position. */ + +/* TCB.EVCTRL bit masks and bit positions */ +#define TCB_CAPTEI_bm 0x01 /* Event Input Enable bit mask. */ +#define TCB_CAPTEI_bp 0 /* Event Input Enable bit position. */ +#define TCB_EDGE_bm 0x10 /* Event Edge bit mask. */ +#define TCB_EDGE_bp 4 /* Event Edge bit position. */ +#define TCB_FILTER_bm 0x40 /* Input Capture Noise Cancellation Filter bit mask. */ +#define TCB_FILTER_bp 6 /* Input Capture Noise Cancellation Filter bit position. */ + +/* TCB.INTCTRL bit masks and bit positions */ +#define TCB_CAPT_bm 0x01 /* Capture or Timeout bit mask. */ +#define TCB_CAPT_bp 0 /* Capture or Timeout bit position. */ + +/* TCB.INTFLAGS bit masks and bit positions */ +/* TCB_CAPT is already defined. */ + +/* TCB.STATUS bit masks and bit positions */ +#define TCB_RUN_bm 0x01 /* Run bit mask. */ +#define TCB_RUN_bp 0 /* Run bit position. */ + +/* TCB.DBGCTRL bit masks and bit positions */ +#define TCB_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TCB_DBGRUN_bp 0 /* Debug Run bit position. */ + + + + +/* TCD - Timer Counter D */ +/* TCD.CTRLA bit masks and bit positions */ +#define TCD_ENABLE_bm 0x01 /* Enable bit mask. */ +#define TCD_ENABLE_bp 0 /* Enable bit position. */ +#define TCD_SYNCPRES_gm 0x06 /* Syncronization prescaler group mask. */ +#define TCD_SYNCPRES_gp 1 /* Syncronization prescaler group position. */ +#define TCD_SYNCPRES0_bm (1<<1) /* Syncronization prescaler bit 0 mask. */ +#define TCD_SYNCPRES0_bp 1 /* Syncronization prescaler bit 0 position. */ +#define TCD_SYNCPRES1_bm (1<<2) /* Syncronization prescaler bit 1 mask. */ +#define TCD_SYNCPRES1_bp 2 /* Syncronization prescaler bit 1 position. */ +#define TCD_CNTPRES_gm 0x18 /* counter prescaler group mask. */ +#define TCD_CNTPRES_gp 3 /* counter prescaler group position. */ +#define TCD_CNTPRES0_bm (1<<3) /* counter prescaler bit 0 mask. */ +#define TCD_CNTPRES0_bp 3 /* counter prescaler bit 0 position. */ +#define TCD_CNTPRES1_bm (1<<4) /* counter prescaler bit 1 mask. */ +#define TCD_CNTPRES1_bp 4 /* counter prescaler bit 1 position. */ +#define TCD_CLKSEL_gm 0x60 /* clock select group mask. */ +#define TCD_CLKSEL_gp 5 /* clock select group position. */ +#define TCD_CLKSEL0_bm (1<<5) /* clock select bit 0 mask. */ +#define TCD_CLKSEL0_bp 5 /* clock select bit 0 position. */ +#define TCD_CLKSEL1_bm (1<<6) /* clock select bit 1 mask. */ +#define TCD_CLKSEL1_bp 6 /* clock select bit 1 position. */ + +/* TCD.CTRLB bit masks and bit positions */ +#define TCD_WGMODE_gm 0x03 /* Waveform generation mode group mask. */ +#define TCD_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TCD_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TCD_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TCD_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TCD_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ + +/* TCD.CTRLC bit masks and bit positions */ +#define TCD_CMPOVR_bm 0x01 /* Compare output value override bit mask. */ +#define TCD_CMPOVR_bp 0 /* Compare output value override bit position. */ +#define TCD_AUPDATE_bm 0x02 /* Auto update bit mask. */ +#define TCD_AUPDATE_bp 1 /* Auto update bit position. */ +#define TCD_FIFTY_bm 0x08 /* Fifty percent waveform bit mask. */ +#define TCD_FIFTY_bp 3 /* Fifty percent waveform bit position. */ +#define TCD_CMPCSEL_bm 0x40 /* Compare C output select bit mask. */ +#define TCD_CMPCSEL_bp 6 /* Compare C output select bit position. */ +#define TCD_CMPDSEL_bm 0x80 /* Compare D output select bit mask. */ +#define TCD_CMPDSEL_bp 7 /* Compare D output select bit position. */ + +/* TCD.CTRLD bit masks and bit positions */ +#define TCD_CMPAVAL_gm 0x0F /* Compare A value group mask. */ +#define TCD_CMPAVAL_gp 0 /* Compare A value group position. */ +#define TCD_CMPAVAL0_bm (1<<0) /* Compare A value bit 0 mask. */ +#define TCD_CMPAVAL0_bp 0 /* Compare A value bit 0 position. */ +#define TCD_CMPAVAL1_bm (1<<1) /* Compare A value bit 1 mask. */ +#define TCD_CMPAVAL1_bp 1 /* Compare A value bit 1 position. */ +#define TCD_CMPAVAL2_bm (1<<2) /* Compare A value bit 2 mask. */ +#define TCD_CMPAVAL2_bp 2 /* Compare A value bit 2 position. */ +#define TCD_CMPAVAL3_bm (1<<3) /* Compare A value bit 3 mask. */ +#define TCD_CMPAVAL3_bp 3 /* Compare A value bit 3 position. */ +#define TCD_CMPBVAL_gm 0xF0 /* Compare B value group mask. */ +#define TCD_CMPBVAL_gp 4 /* Compare B value group position. */ +#define TCD_CMPBVAL0_bm (1<<4) /* Compare B value bit 0 mask. */ +#define TCD_CMPBVAL0_bp 4 /* Compare B value bit 0 position. */ +#define TCD_CMPBVAL1_bm (1<<5) /* Compare B value bit 1 mask. */ +#define TCD_CMPBVAL1_bp 5 /* Compare B value bit 1 position. */ +#define TCD_CMPBVAL2_bm (1<<6) /* Compare B value bit 2 mask. */ +#define TCD_CMPBVAL2_bp 6 /* Compare B value bit 2 position. */ +#define TCD_CMPBVAL3_bm (1<<7) /* Compare B value bit 3 mask. */ +#define TCD_CMPBVAL3_bp 7 /* Compare B value bit 3 position. */ + +/* TCD.CTRLE bit masks and bit positions */ +#define TCD_SYNCEOC_bm 0x01 /* synchronize end of cycle strobe bit mask. */ +#define TCD_SYNCEOC_bp 0 /* synchronize end of cycle strobe bit position. */ +#define TCD_SYNC_bm 0x02 /* synchronize strobe bit mask. */ +#define TCD_SYNC_bp 1 /* synchronize strobe bit position. */ +#define TCD_RESTART_bm 0x04 /* Restart strobe bit mask. */ +#define TCD_RESTART_bp 2 /* Restart strobe bit position. */ +#define TCD_SCAPTUREA_bm 0x08 /* Software Capture A Strobe bit mask. */ +#define TCD_SCAPTUREA_bp 3 /* Software Capture A Strobe bit position. */ +#define TCD_SCAPTUREB_bm 0x10 /* Software Capture B Strobe bit mask. */ +#define TCD_SCAPTUREB_bp 4 /* Software Capture B Strobe bit position. */ +#define TCD_DISEOC_bm 0x80 /* Disable at end of cycle bit mask. */ +#define TCD_DISEOC_bp 7 /* Disable at end of cycle bit position. */ + +/* TCD.EVCTRLA bit masks and bit positions */ +#define TCD_TRIGEI_bm 0x01 /* Trigger event enable bit mask. */ +#define TCD_TRIGEI_bp 0 /* Trigger event enable bit position. */ +#define TCD_ACTION_bm 0x04 /* event action bit mask. */ +#define TCD_ACTION_bp 2 /* event action bit position. */ +#define TCD_EDGE_bm 0x10 /* edge select bit mask. */ +#define TCD_EDGE_bp 4 /* edge select bit position. */ +#define TCD_CFG_gm 0xC0 /* event config group mask. */ +#define TCD_CFG_gp 6 /* event config group position. */ +#define TCD_CFG0_bm (1<<6) /* event config bit 0 mask. */ +#define TCD_CFG0_bp 6 /* event config bit 0 position. */ +#define TCD_CFG1_bm (1<<7) /* event config bit 1 mask. */ +#define TCD_CFG1_bp 7 /* event config bit 1 position. */ + +/* TCD.EVCTRLB bit masks and bit positions */ +/* TCD_TRIGEI is already defined. */ +/* TCD_ACTION is already defined. */ +/* TCD_EDGE is already defined. */ +/* TCD_CFG is already defined. */ + +/* TCD.INTCTRL bit masks and bit positions */ +#define TCD_OVF_bm 0x01 /* Overflow interrupt enable bit mask. */ +#define TCD_OVF_bp 0 /* Overflow interrupt enable bit position. */ +#define TCD_TRIGA_bm 0x04 /* Trigger A interrupt enable bit mask. */ +#define TCD_TRIGA_bp 2 /* Trigger A interrupt enable bit position. */ +#define TCD_TRIGB_bm 0x08 /* Trigger B interrupt enable bit mask. */ +#define TCD_TRIGB_bp 3 /* Trigger B interrupt enable bit position. */ + +/* TCD.INTFLAGS bit masks and bit positions */ +/* TCD_OVF is already defined. */ +/* TCD_TRIGA is already defined. */ +/* TCD_TRIGB is already defined. */ + +/* TCD.STATUS bit masks and bit positions */ +#define TCD_ENRDY_bm 0x01 /* Enable ready bit mask. */ +#define TCD_ENRDY_bp 0 /* Enable ready bit position. */ +#define TCD_CMDRDY_bm 0x02 /* Command ready bit mask. */ +#define TCD_CMDRDY_bp 1 /* Command ready bit position. */ +#define TCD_PWMACTA_bm 0x40 /* PWM activity on A bit mask. */ +#define TCD_PWMACTA_bp 6 /* PWM activity on A bit position. */ +#define TCD_PWMACTB_bm 0x80 /* PWM activity on B bit mask. */ +#define TCD_PWMACTB_bp 7 /* PWM activity on B bit position. */ + +/* TCD.INPUTCTRLA bit masks and bit positions */ +#define TCD_INPUTMODE_gm 0x0F /* Input mode group mask. */ +#define TCD_INPUTMODE_gp 0 /* Input mode group position. */ +#define TCD_INPUTMODE0_bm (1<<0) /* Input mode bit 0 mask. */ +#define TCD_INPUTMODE0_bp 0 /* Input mode bit 0 position. */ +#define TCD_INPUTMODE1_bm (1<<1) /* Input mode bit 1 mask. */ +#define TCD_INPUTMODE1_bp 1 /* Input mode bit 1 position. */ +#define TCD_INPUTMODE2_bm (1<<2) /* Input mode bit 2 mask. */ +#define TCD_INPUTMODE2_bp 2 /* Input mode bit 2 position. */ +#define TCD_INPUTMODE3_bm (1<<3) /* Input mode bit 3 mask. */ +#define TCD_INPUTMODE3_bp 3 /* Input mode bit 3 position. */ + +/* TCD.INPUTCTRLB bit masks and bit positions */ +/* TCD_INPUTMODE is already defined. */ + +/* TCD.FAULTCTRL bit masks and bit positions */ +#define TCD_CMPA_bm 0x01 /* Compare A value bit mask. */ +#define TCD_CMPA_bp 0 /* Compare A value bit position. */ +#define TCD_CMPB_bm 0x02 /* Compare B value bit mask. */ +#define TCD_CMPB_bp 1 /* Compare B value bit position. */ +#define TCD_CMPC_bm 0x04 /* Compare C value bit mask. */ +#define TCD_CMPC_bp 2 /* Compare C value bit position. */ +#define TCD_CMPD_bm 0x08 /* Compare D vaule bit mask. */ +#define TCD_CMPD_bp 3 /* Compare D vaule bit position. */ +#define TCD_CMPAEN_bm 0x10 /* Compare A enable bit mask. */ +#define TCD_CMPAEN_bp 4 /* Compare A enable bit position. */ +#define TCD_CMPBEN_bm 0x20 /* Compare B enable bit mask. */ +#define TCD_CMPBEN_bp 5 /* Compare B enable bit position. */ +#define TCD_CMPCEN_bm 0x40 /* Compare C enable bit mask. */ +#define TCD_CMPCEN_bp 6 /* Compare C enable bit position. */ +#define TCD_CMPDEN_bm 0x80 /* Compare D enable bit mask. */ +#define TCD_CMPDEN_bp 7 /* Compare D enable bit position. */ + +/* TCD.DLYCTRL bit masks and bit positions */ +#define TCD_DLYSEL_gm 0x03 /* Delay select group mask. */ +#define TCD_DLYSEL_gp 0 /* Delay select group position. */ +#define TCD_DLYSEL0_bm (1<<0) /* Delay select bit 0 mask. */ +#define TCD_DLYSEL0_bp 0 /* Delay select bit 0 position. */ +#define TCD_DLYSEL1_bm (1<<1) /* Delay select bit 1 mask. */ +#define TCD_DLYSEL1_bp 1 /* Delay select bit 1 position. */ +#define TCD_DLYTRIG_gm 0x0C /* Delay trigger group mask. */ +#define TCD_DLYTRIG_gp 2 /* Delay trigger group position. */ +#define TCD_DLYTRIG0_bm (1<<2) /* Delay trigger bit 0 mask. */ +#define TCD_DLYTRIG0_bp 2 /* Delay trigger bit 0 position. */ +#define TCD_DLYTRIG1_bm (1<<3) /* Delay trigger bit 1 mask. */ +#define TCD_DLYTRIG1_bp 3 /* Delay trigger bit 1 position. */ +#define TCD_DLYPRESC_gm 0x30 /* Delay prescaler group mask. */ +#define TCD_DLYPRESC_gp 4 /* Delay prescaler group position. */ +#define TCD_DLYPRESC0_bm (1<<4) /* Delay prescaler bit 0 mask. */ +#define TCD_DLYPRESC0_bp 4 /* Delay prescaler bit 0 position. */ +#define TCD_DLYPRESC1_bm (1<<5) /* Delay prescaler bit 1 mask. */ +#define TCD_DLYPRESC1_bp 5 /* Delay prescaler bit 1 position. */ + +/* TCD.DLYVAL bit masks and bit positions */ +#define TCD_DLYVAL_gm 0xFF /* Delay value group mask. */ +#define TCD_DLYVAL_gp 0 /* Delay value group position. */ +#define TCD_DLYVAL0_bm (1<<0) /* Delay value bit 0 mask. */ +#define TCD_DLYVAL0_bp 0 /* Delay value bit 0 position. */ +#define TCD_DLYVAL1_bm (1<<1) /* Delay value bit 1 mask. */ +#define TCD_DLYVAL1_bp 1 /* Delay value bit 1 position. */ +#define TCD_DLYVAL2_bm (1<<2) /* Delay value bit 2 mask. */ +#define TCD_DLYVAL2_bp 2 /* Delay value bit 2 position. */ +#define TCD_DLYVAL3_bm (1<<3) /* Delay value bit 3 mask. */ +#define TCD_DLYVAL3_bp 3 /* Delay value bit 3 position. */ +#define TCD_DLYVAL4_bm (1<<4) /* Delay value bit 4 mask. */ +#define TCD_DLYVAL4_bp 4 /* Delay value bit 4 position. */ +#define TCD_DLYVAL5_bm (1<<5) /* Delay value bit 5 mask. */ +#define TCD_DLYVAL5_bp 5 /* Delay value bit 5 position. */ +#define TCD_DLYVAL6_bm (1<<6) /* Delay value bit 6 mask. */ +#define TCD_DLYVAL6_bp 6 /* Delay value bit 6 position. */ +#define TCD_DLYVAL7_bm (1<<7) /* Delay value bit 7 mask. */ +#define TCD_DLYVAL7_bp 7 /* Delay value bit 7 position. */ + +/* TCD.DITCTRL bit masks and bit positions */ +#define TCD_DITHERSEL_gm 0x03 /* dither select group mask. */ +#define TCD_DITHERSEL_gp 0 /* dither select group position. */ +#define TCD_DITHERSEL0_bm (1<<0) /* dither select bit 0 mask. */ +#define TCD_DITHERSEL0_bp 0 /* dither select bit 0 position. */ +#define TCD_DITHERSEL1_bm (1<<1) /* dither select bit 1 mask. */ +#define TCD_DITHERSEL1_bp 1 /* dither select bit 1 position. */ + +/* TCD.DITVAL bit masks and bit positions */ +#define TCD_DITHER_gm 0x0F /* Dither value group mask. */ +#define TCD_DITHER_gp 0 /* Dither value group position. */ +#define TCD_DITHER0_bm (1<<0) /* Dither value bit 0 mask. */ +#define TCD_DITHER0_bp 0 /* Dither value bit 0 position. */ +#define TCD_DITHER1_bm (1<<1) /* Dither value bit 1 mask. */ +#define TCD_DITHER1_bp 1 /* Dither value bit 1 position. */ +#define TCD_DITHER2_bm (1<<2) /* Dither value bit 2 mask. */ +#define TCD_DITHER2_bp 2 /* Dither value bit 2 position. */ +#define TCD_DITHER3_bm (1<<3) /* Dither value bit 3 mask. */ +#define TCD_DITHER3_bp 3 /* Dither value bit 3 position. */ + +/* TCD.DBGCTRL bit masks and bit positions */ +#define TCD_DBGRUN_bm 0x01 /* Debug run bit mask. */ +#define TCD_DBGRUN_bp 0 /* Debug run bit position. */ +#define TCD_FAULTDET_bm 0x04 /* Fault detection bit mask. */ +#define TCD_FAULTDET_bp 2 /* Fault detection bit position. */ + + + + + + + +/* TWI - Two-Wire Interface */ +/* TWI.CTRLA bit masks and bit positions */ +#define TWI_FMPEN_bm 0x02 /* FM Plus Enable bit mask. */ +#define TWI_FMPEN_bp 1 /* FM Plus Enable bit position. */ +#define TWI_SDAHOLD_gm 0x0C /* SDA Hold Time group mask. */ +#define TWI_SDAHOLD_gp 2 /* SDA Hold Time group position. */ +#define TWI_SDAHOLD0_bm (1<<2) /* SDA Hold Time bit 0 mask. */ +#define TWI_SDAHOLD0_bp 2 /* SDA Hold Time bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<3) /* SDA Hold Time bit 1 mask. */ +#define TWI_SDAHOLD1_bp 3 /* SDA Hold Time bit 1 position. */ +#define TWI_SDASETUP_bm 0x10 /* SDA Setup Time bit mask. */ +#define TWI_SDASETUP_bp 4 /* SDA Setup Time bit position. */ + +/* TWI.DBGCTRL bit masks and bit positions */ +#define TWI_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define TWI_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* TWI.MCTRLA bit masks and bit positions */ +#define TWI_ENABLE_bm 0x01 /* Enable TWI Master bit mask. */ +#define TWI_ENABLE_bp 0 /* Enable TWI Master bit position. */ +#define TWI_SMEN_bm 0x02 /* Smart Mode Enable bit mask. */ +#define TWI_SMEN_bp 1 /* Smart Mode Enable bit position. */ +#define TWI_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +#define TWI_QCEN_bm 0x10 /* Quick Command Enable bit mask. */ +#define TWI_QCEN_bp 4 /* Quick Command Enable bit position. */ +#define TWI_WIEN_bm 0x40 /* Write Interrupt Enable bit mask. */ +#define TWI_WIEN_bp 6 /* Write Interrupt Enable bit position. */ +#define TWI_RIEN_bm 0x80 /* Read Interrupt Enable bit mask. */ +#define TWI_RIEN_bp 7 /* Read Interrupt Enable bit position. */ + +/* TWI.MCTRLB bit masks and bit positions */ +#define TWI_MCMD_gm 0x03 /* Command group mask. */ +#define TWI_MCMD_gp 0 /* Command group position. */ +#define TWI_MCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MCMD1_bp 1 /* Command bit 1 position. */ +#define TWI_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_ACKACT_bp 2 /* Acknowledge Action bit position. */ +#define TWI_FLUSH_bm 0x08 /* Flush bit mask. */ +#define TWI_FLUSH_bp 3 /* Flush bit position. */ + +/* TWI.MSTATUS bit masks and bit positions */ +#define TWI_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +#define TWI_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_BUSERR_bp 2 /* Bus Error bit position. */ +#define TWI_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +#define TWI_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_RXACK_bp 4 /* Received Acknowledge bit position. */ +#define TWI_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_CLKHOLD_bp 5 /* Clock Hold bit position. */ +#define TWI_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_WIF_bp 6 /* Write Interrupt Flag bit position. */ +#define TWI_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_RIF_bp 7 /* Read Interrupt Flag bit position. */ + + + + +/* TWI.SCTRLA bit masks and bit positions */ +/* TWI_ENABLE is already defined. */ +/* TWI_SMEN is already defined. */ +#define TWI_PMEN_bm 0x04 /* Promiscuous Mode Enable bit mask. */ +#define TWI_PMEN_bp 2 /* Promiscuous Mode Enable bit position. */ +#define TWI_PIEN_bm 0x20 /* Stop Interrupt Enable bit mask. */ +#define TWI_PIEN_bp 5 /* Stop Interrupt Enable bit position. */ +#define TWI_APIEN_bm 0x40 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_APIEN_bp 6 /* Address/Stop Interrupt Enable bit position. */ +#define TWI_DIEN_bm 0x80 /* Data Interrupt Enable bit mask. */ +#define TWI_DIEN_bp 7 /* Data Interrupt Enable bit position. */ + +/* TWI.SCTRLB bit masks and bit positions */ +#define TWI_SCMD_gm 0x03 /* Command group mask. */ +#define TWI_SCMD_gp 0 /* Command group position. */ +#define TWI_SCMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SCMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SCMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SCMD1_bp 1 /* Command bit 1 position. */ +/* TWI_ACKACT is already defined. */ + +/* TWI.SSTATUS bit masks and bit positions */ +#define TWI_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_AP_bp 0 /* Slave Address or Stop bit position. */ +#define TWI_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_DIR_bp 1 /* Read/Write Direction bit position. */ +/* TWI_BUSERR is already defined. */ +#define TWI_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_COLL_bp 3 /* Collision bit position. */ +/* TWI_RXACK is already defined. */ +/* TWI_CLKHOLD is already defined. */ +#define TWI_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +#define TWI_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_DIF_bp 7 /* Data Interrupt Flag bit position. */ + + + +/* TWI.SADDRMASK bit masks and bit positions */ +#define TWI_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_ADDREN_bp 0 /* Address Enable bit position. */ +#define TWI_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +/* USART - Universal Synchronous and Asynchronous Receiver and Transmitter */ +/* USART.RXDATAL bit masks and bit positions */ +#define USART_DATA_gm 0xFF /* RX Data group mask. */ +#define USART_DATA_gp 0 /* RX Data group position. */ +#define USART_DATA0_bm (1<<0) /* RX Data bit 0 mask. */ +#define USART_DATA0_bp 0 /* RX Data bit 0 position. */ +#define USART_DATA1_bm (1<<1) /* RX Data bit 1 mask. */ +#define USART_DATA1_bp 1 /* RX Data bit 1 position. */ +#define USART_DATA2_bm (1<<2) /* RX Data bit 2 mask. */ +#define USART_DATA2_bp 2 /* RX Data bit 2 position. */ +#define USART_DATA3_bm (1<<3) /* RX Data bit 3 mask. */ +#define USART_DATA3_bp 3 /* RX Data bit 3 position. */ +#define USART_DATA4_bm (1<<4) /* RX Data bit 4 mask. */ +#define USART_DATA4_bp 4 /* RX Data bit 4 position. */ +#define USART_DATA5_bm (1<<5) /* RX Data bit 5 mask. */ +#define USART_DATA5_bp 5 /* RX Data bit 5 position. */ +#define USART_DATA6_bm (1<<6) /* RX Data bit 6 mask. */ +#define USART_DATA6_bp 6 /* RX Data bit 6 position. */ +#define USART_DATA7_bm (1<<7) /* RX Data bit 7 mask. */ +#define USART_DATA7_bp 7 /* RX Data bit 7 position. */ + +/* USART.RXDATAH bit masks and bit positions */ +#define USART_DATA8_bm 0x01 /* Receiver Data Register bit mask. */ +#define USART_DATA8_bp 0 /* Receiver Data Register bit position. */ +#define USART_PERR_bm 0x02 /* Parity Error bit mask. */ +#define USART_PERR_bp 1 /* Parity Error bit position. */ +#define USART_FERR_bm 0x04 /* Frame Error bit mask. */ +#define USART_FERR_bp 2 /* Frame Error bit position. */ +#define USART_BUFOVF_bm 0x40 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 6 /* Buffer Overflow bit position. */ +#define USART_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Complete Interrupt Flag bit position. */ + +/* USART.TXDATAL bit masks and bit positions */ +/* USART_DATA is already defined. */ + +/* USART.TXDATAH bit masks and bit positions */ +/* USART_DATA8 is already defined. */ + +/* USART.STATUS bit masks and bit positions */ +#define USART_WFB_bm 0x01 /* Wait For Break bit mask. */ +#define USART_WFB_bp 0 /* Wait For Break bit position. */ +#define USART_BDF_bm 0x02 /* Break Detected Flag bit mask. */ +#define USART_BDF_bp 1 /* Break Detected Flag bit position. */ +#define USART_ISFIF_bm 0x08 /* Inconsistent Sync Field Interrupt Flag bit mask. */ +#define USART_ISFIF_bp 3 /* Inconsistent Sync Field Interrupt Flag bit position. */ +#define USART_RXSIF_bm 0x10 /* Receive Start Interrupt bit mask. */ +#define USART_RXSIF_bp 4 /* Receive Start Interrupt bit position. */ +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +/* USART_RXCIF is already defined. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RS485_gm 0x03 /* RS485 Mode internal transmitter group mask. */ +#define USART_RS485_gp 0 /* RS485 Mode internal transmitter group position. */ +#define USART_RS4850_bm (1<<0) /* RS485 Mode internal transmitter bit 0 mask. */ +#define USART_RS4850_bp 0 /* RS485 Mode internal transmitter bit 0 position. */ +#define USART_RS4851_bm (1<<1) /* RS485 Mode internal transmitter bit 1 mask. */ +#define USART_RS4851_bp 1 /* RS485 Mode internal transmitter bit 1 position. */ +#define USART_ABEIE_bm 0x04 /* Auto-baud Error Interrupt Enable bit mask. */ +#define USART_ABEIE_bp 2 /* Auto-baud Error Interrupt Enable bit position. */ +#define USART_LBME_bm 0x08 /* Loop-back Mode Enable bit mask. */ +#define USART_LBME_bp 3 /* Loop-back Mode Enable bit position. */ +#define USART_RXSIE_bm 0x10 /* Receiver Start Frame Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 4 /* Receiver Start Frame Interrupt Enable bit position. */ +#define USART_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable bit mask. */ +#define USART_DREIE_bp 5 /* Data Register Empty Interrupt Enable bit position. */ +#define USART_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable bit mask. */ +#define USART_TXCIE_bp 6 /* Transmit Complete Interrupt Enable bit position. */ +#define USART_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable bit mask. */ +#define USART_RXCIE_bp 7 /* Receive Complete Interrupt Enable bit position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_MPCM_bm 0x01 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 0 /* Multi-processor Communication Mode bit position. */ +#define USART_RXMODE_gm 0x06 /* Receiver Mode group mask. */ +#define USART_RXMODE_gp 1 /* Receiver Mode group position. */ +#define USART_RXMODE0_bm (1<<1) /* Receiver Mode bit 0 mask. */ +#define USART_RXMODE0_bp 1 /* Receiver Mode bit 0 position. */ +#define USART_RXMODE1_bm (1<<2) /* Receiver Mode bit 1 mask. */ +#define USART_RXMODE1_bp 2 /* Receiver Mode bit 1 position. */ +#define USART_ODME_bm 0x08 /* Open Drain Mode Enable bit mask. */ +#define USART_ODME_bp 3 /* Open Drain Mode Enable bit position. */ +#define USART_SFDEN_bm 0x10 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 4 /* Start Frame Detection Enable bit position. */ +#define USART_TXEN_bm 0x40 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 6 /* Transmitter Enable bit position. */ +#define USART_RXEN_bm 0x80 /* Reciever enable bit mask. */ +#define USART_RXEN_bp 7 /* Reciever enable bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + + +/* USART.DBGCTRL bit masks and bit positions */ +#define USART_DBGRUN_bm 0x01 /* Debug Run bit mask. */ +#define USART_DBGRUN_bp 0 /* Debug Run bit position. */ + +/* USART.EVCTRL bit masks and bit positions */ +#define USART_IREI_bm 0x01 /* IrDA Event Input Enable bit mask. */ +#define USART_IREI_bp 0 /* IrDA Event Input Enable bit position. */ + +/* USART.TXPLCTRL bit masks and bit positions */ +#define USART_TXPL_gm 0xFF /* Transmit pulse length group mask. */ +#define USART_TXPL_gp 0 /* Transmit pulse length group position. */ +#define USART_TXPL0_bm (1<<0) /* Transmit pulse length bit 0 mask. */ +#define USART_TXPL0_bp 0 /* Transmit pulse length bit 0 position. */ +#define USART_TXPL1_bm (1<<1) /* Transmit pulse length bit 1 mask. */ +#define USART_TXPL1_bp 1 /* Transmit pulse length bit 1 position. */ +#define USART_TXPL2_bm (1<<2) /* Transmit pulse length bit 2 mask. */ +#define USART_TXPL2_bp 2 /* Transmit pulse length bit 2 position. */ +#define USART_TXPL3_bm (1<<3) /* Transmit pulse length bit 3 mask. */ +#define USART_TXPL3_bp 3 /* Transmit pulse length bit 3 position. */ +#define USART_TXPL4_bm (1<<4) /* Transmit pulse length bit 4 mask. */ +#define USART_TXPL4_bp 4 /* Transmit pulse length bit 4 position. */ +#define USART_TXPL5_bm (1<<5) /* Transmit pulse length bit 5 mask. */ +#define USART_TXPL5_bp 5 /* Transmit pulse length bit 5 position. */ +#define USART_TXPL6_bm (1<<6) /* Transmit pulse length bit 6 mask. */ +#define USART_TXPL6_bp 6 /* Transmit pulse length bit 6 position. */ +#define USART_TXPL7_bm (1<<7) /* Transmit pulse length bit 7 mask. */ +#define USART_TXPL7_bp 7 /* Transmit pulse length bit 7 position. */ + +/* USART.RXPLCTRL bit masks and bit positions */ +#define USART_RXPL_gm 0x7F /* Receiver Pulse Lenght group mask. */ +#define USART_RXPL_gp 0 /* Receiver Pulse Lenght group position. */ +#define USART_RXPL0_bm (1<<0) /* Receiver Pulse Lenght bit 0 mask. */ +#define USART_RXPL0_bp 0 /* Receiver Pulse Lenght bit 0 position. */ +#define USART_RXPL1_bm (1<<1) /* Receiver Pulse Lenght bit 1 mask. */ +#define USART_RXPL1_bp 1 /* Receiver Pulse Lenght bit 1 position. */ +#define USART_RXPL2_bm (1<<2) /* Receiver Pulse Lenght bit 2 mask. */ +#define USART_RXPL2_bp 2 /* Receiver Pulse Lenght bit 2 position. */ +#define USART_RXPL3_bm (1<<3) /* Receiver Pulse Lenght bit 3 mask. */ +#define USART_RXPL3_bp 3 /* Receiver Pulse Lenght bit 3 position. */ +#define USART_RXPL4_bm (1<<4) /* Receiver Pulse Lenght bit 4 mask. */ +#define USART_RXPL4_bp 4 /* Receiver Pulse Lenght bit 4 position. */ +#define USART_RXPL5_bm (1<<5) /* Receiver Pulse Lenght bit 5 mask. */ +#define USART_RXPL5_bp 5 /* Receiver Pulse Lenght bit 5 position. */ +#define USART_RXPL6_bm (1<<6) /* Receiver Pulse Lenght bit 6 mask. */ +#define USART_RXPL6_bp 6 /* Receiver Pulse Lenght bit 6 position. */ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT_gm 0xFF /* Pin Interrupt group mask. */ +#define VPORT_INT_gp 0 /* Pin Interrupt group position. */ +#define VPORT_INT0_bm (1<<0) /* Pin Interrupt bit 0 mask. */ +#define VPORT_INT0_bp 0 /* Pin Interrupt bit 0 position. */ +#define VPORT_INT1_bm (1<<1) /* Pin Interrupt bit 1 mask. */ +#define VPORT_INT1_bp 1 /* Pin Interrupt bit 1 position. */ +#define VPORT_INT2_bm (1<<2) /* Pin Interrupt bit 2 mask. */ +#define VPORT_INT2_bp 2 /* Pin Interrupt bit 2 position. */ +#define VPORT_INT3_bm (1<<3) /* Pin Interrupt bit 3 mask. */ +#define VPORT_INT3_bp 3 /* Pin Interrupt bit 3 position. */ +#define VPORT_INT4_bm (1<<4) /* Pin Interrupt bit 4 mask. */ +#define VPORT_INT4_bp 4 /* Pin Interrupt bit 4 position. */ +#define VPORT_INT5_bm (1<<5) /* Pin Interrupt bit 5 mask. */ +#define VPORT_INT5_bp 5 /* Pin Interrupt bit 5 position. */ +#define VPORT_INT6_bm (1<<6) /* Pin Interrupt bit 6 mask. */ +#define VPORT_INT6_bp 6 /* Pin Interrupt bit 6 position. */ +#define VPORT_INT7_bm (1<<7) /* Pin Interrupt bit 7 mask. */ +#define VPORT_INT7_bp 7 /* Pin Interrupt bit 7 position. */ + +/* VREF - Voltage reference */ +/* VREF.CTRLA bit masks and bit positions */ +#define VREF_DAC0REFSEL_gm 0x07 /* DAC0/AC0 reference select group mask. */ +#define VREF_DAC0REFSEL_gp 0 /* DAC0/AC0 reference select group position. */ +#define VREF_DAC0REFSEL0_bm (1<<0) /* DAC0/AC0 reference select bit 0 mask. */ +#define VREF_DAC0REFSEL0_bp 0 /* DAC0/AC0 reference select bit 0 position. */ +#define VREF_DAC0REFSEL1_bm (1<<1) /* DAC0/AC0 reference select bit 1 mask. */ +#define VREF_DAC0REFSEL1_bp 1 /* DAC0/AC0 reference select bit 1 position. */ +#define VREF_DAC0REFSEL2_bm (1<<2) /* DAC0/AC0 reference select bit 2 mask. */ +#define VREF_DAC0REFSEL2_bp 2 /* DAC0/AC0 reference select bit 2 position. */ +#define VREF_ADC0REFSEL_gm 0x70 /* ADC0 reference select group mask. */ +#define VREF_ADC0REFSEL_gp 4 /* ADC0 reference select group position. */ +#define VREF_ADC0REFSEL0_bm (1<<4) /* ADC0 reference select bit 0 mask. */ +#define VREF_ADC0REFSEL0_bp 4 /* ADC0 reference select bit 0 position. */ +#define VREF_ADC0REFSEL1_bm (1<<5) /* ADC0 reference select bit 1 mask. */ +#define VREF_ADC0REFSEL1_bp 5 /* ADC0 reference select bit 1 position. */ +#define VREF_ADC0REFSEL2_bm (1<<6) /* ADC0 reference select bit 2 mask. */ +#define VREF_ADC0REFSEL2_bp 6 /* ADC0 reference select bit 2 position. */ + +/* VREF.CTRLB bit masks and bit positions */ +#define VREF_DAC0REFEN_bm 0x01 /* DAC0/AC0 reference enable bit mask. */ +#define VREF_DAC0REFEN_bp 0 /* DAC0/AC0 reference enable bit position. */ +#define VREF_ADC0REFEN_bm 0x02 /* ADC0 reference enable bit mask. */ +#define VREF_ADC0REFEN_bp 1 /* ADC0 reference enable bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRLA bit masks and bit positions */ +#define WDT_PERIOD_gm 0x0F /* Period group mask. */ +#define WDT_PERIOD_gp 0 /* Period group position. */ +#define WDT_PERIOD0_bm (1<<0) /* Period bit 0 mask. */ +#define WDT_PERIOD0_bp 0 /* Period bit 0 position. */ +#define WDT_PERIOD1_bm (1<<1) /* Period bit 1 mask. */ +#define WDT_PERIOD1_bp 1 /* Period bit 1 position. */ +#define WDT_PERIOD2_bm (1<<2) /* Period bit 2 mask. */ +#define WDT_PERIOD2_bp 2 /* Period bit 2 position. */ +#define WDT_PERIOD3_bm (1<<3) /* Period bit 3 mask. */ +#define WDT_PERIOD3_bp 3 /* Period bit 3 position. */ +#define WDT_WINDOW_gm 0xF0 /* Window group mask. */ +#define WDT_WINDOW_gp 4 /* Window group position. */ +#define WDT_WINDOW0_bm (1<<4) /* Window bit 0 mask. */ +#define WDT_WINDOW0_bp 4 /* Window bit 0 position. */ +#define WDT_WINDOW1_bm (1<<5) /* Window bit 1 mask. */ +#define WDT_WINDOW1_bp 5 /* Window bit 1 position. */ +#define WDT_WINDOW2_bm (1<<6) /* Window bit 2 mask. */ +#define WDT_WINDOW2_bp 6 /* Window bit 2 position. */ +#define WDT_WINDOW3_bm (1<<7) /* Window bit 3 mask. */ +#define WDT_WINDOW3_bp 7 /* Window bit 3 position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +#define WDT_LOCK_bm 0x80 /* Lock enable bit mask. */ +#define WDT_LOCK_bp 7 /* Lock enable bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* CRCSCAN interrupt vectors */ +#define CRCSCAN_NMI_vect_num 1 +#define CRCSCAN_NMI_vect _VECTOR(1) /* */ + +/* BOD interrupt vectors */ +#define BOD_VLM_vect_num 2 +#define BOD_VLM_vect _VECTOR(2) /* */ + +/* PORTA interrupt vectors */ +#define PORTA_PORT_vect_num 3 +#define PORTA_PORT_vect _VECTOR(3) /* */ + +/* PORTB interrupt vectors */ +#define PORTB_PORT_vect_num 4 +#define PORTB_PORT_vect _VECTOR(4) /* */ + +/* PORTC interrupt vectors */ +#define PORTC_PORT_vect_num 5 +#define PORTC_PORT_vect _VECTOR(5) /* */ + +/* RTC interrupt vectors */ +#define RTC_CNT_vect_num 6 +#define RTC_CNT_vect _VECTOR(6) /* */ +#define RTC_PIT_vect_num 7 +#define RTC_PIT_vect _VECTOR(7) /* */ + +/* TCA0 interrupt vectors */ +#define TCA0_LUNF_vect_num 8 +#define TCA0_LUNF_vect _VECTOR(8) /* */ +#define TCA0_OVF_vect_num 8 +#define TCA0_OVF_vect _VECTOR(8) /* */ +#define TCA0_HUNF_vect_num 9 +#define TCA0_HUNF_vect _VECTOR(9) /* */ +#define TCA0_CMP0_vect_num 10 +#define TCA0_CMP0_vect _VECTOR(10) /* */ +#define TCA0_LCMP0_vect_num 10 +#define TCA0_LCMP0_vect _VECTOR(10) /* */ +#define TCA0_CMP1_vect_num 11 +#define TCA0_CMP1_vect _VECTOR(11) /* */ +#define TCA0_LCMP1_vect_num 11 +#define TCA0_LCMP1_vect _VECTOR(11) /* */ +#define TCA0_CMP2_vect_num 12 +#define TCA0_CMP2_vect _VECTOR(12) /* */ +#define TCA0_LCMP2_vect_num 12 +#define TCA0_LCMP2_vect _VECTOR(12) /* */ + +/* TCB0 interrupt vectors */ +#define TCB0_INT_vect_num 13 +#define TCB0_INT_vect _VECTOR(13) /* */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 14 +#define TCD0_OVF_vect _VECTOR(14) /* */ +#define TCD0_TRIG_vect_num 15 +#define TCD0_TRIG_vect _VECTOR(15) /* */ + +/* AC0 interrupt vectors */ +#define AC0_AC_vect_num 16 +#define AC0_AC_vect _VECTOR(16) /* */ + +/* ADC0 interrupt vectors */ +#define ADC0_RESRDY_vect_num 17 +#define ADC0_RESRDY_vect _VECTOR(17) /* */ +#define ADC0_WCOMP_vect_num 18 +#define ADC0_WCOMP_vect _VECTOR(18) /* */ + +/* TWI0 interrupt vectors */ +#define TWI0_TWIS_vect_num 19 +#define TWI0_TWIS_vect _VECTOR(19) /* */ +#define TWI0_TWIM_vect_num 20 +#define TWI0_TWIM_vect _VECTOR(20) /* */ + +/* SPI0 interrupt vectors */ +#define SPI0_INT_vect_num 21 +#define SPI0_INT_vect _VECTOR(21) /* */ + +/* USART0 interrupt vectors */ +#define USART0_RXC_vect_num 22 +#define USART0_RXC_vect _VECTOR(22) /* */ +#define USART0_DRE_vect_num 23 +#define USART0_DRE_vect _VECTOR(23) /* */ +#define USART0_TXC_vect_num 24 +#define USART0_TXC_vect _VECTOR(24) /* */ + +/* NVMCTRL interrupt vectors */ +#define NVMCTRL_EE_vect_num 25 +#define NVMCTRL_EE_vect _VECTOR(25) /* */ + +#define _VECTOR_SIZE 2 /* Size of individual vector. */ +#define _VECTORS_SIZE (26 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define DATAMEM_START (0x0000) +# define DATAMEM_SIZE (40960) +#else +# define DATAMEM_START (0x0000U) +# define DATAMEM_SIZE (40960U) +#endif +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define EEPROM_START (0x1400) +# define EEPROM_SIZE (128) +# define EEPROM_PAGE_SIZE (32) +#else +# define EEPROM_START (0x1400U) +# define EEPROM_SIZE (128U) +# define EEPROM_PAGE_SIZE (32U) +#endif +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +/* Added MAPPED_EEPROM segment names for avr-libc */ +#define MAPPED_EEPROM_START (EEPROM_START) +#define MAPPED_EEPROM_SIZE (EEPROM_SIZE) +#define MAPPED_EEPROM_PAGE_SIZE (EEPROM_PAGE_SIZE) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define FUSES_START (0x1280) +# define FUSES_SIZE (10) +# define FUSES_PAGE_SIZE (32) +#else +# define FUSES_START (0x1280U) +# define FUSES_SIZE (10U) +# define FUSES_PAGE_SIZE (32U) +#endif +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define INTERNAL_SRAM_START (0x3E00) +# define INTERNAL_SRAM_SIZE (512) +# define INTERNAL_SRAM_PAGE_SIZE (0) +#else +# define INTERNAL_SRAM_START (0x3E00U) +# define INTERNAL_SRAM_SIZE (512U) +# define INTERNAL_SRAM_PAGE_SIZE (0U) +#endif +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define IO_START (0x0000) +# define IO_SIZE (4352) +# define IO_PAGE_SIZE (0) +#else +# define IO_START (0x0000U) +# define IO_SIZE (4352U) +# define IO_PAGE_SIZE (0U) +#endif +#define IO_END (IO_START + IO_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define LOCKBITS_START (0x128A) +# define LOCKBITS_SIZE (1) +# define LOCKBITS_PAGE_SIZE (32) +#else +# define LOCKBITS_START (0x128AU) +# define LOCKBITS_SIZE (1U) +# define LOCKBITS_PAGE_SIZE (32U) +#endif +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define MAPPED_PROGMEM_START (0x8000) +# define MAPPED_PROGMEM_SIZE (8192) +# define MAPPED_PROGMEM_PAGE_SIZE (64) +#else +# define MAPPED_PROGMEM_START (0x8000U) +# define MAPPED_PROGMEM_SIZE (8192U) +# define MAPPED_PROGMEM_PAGE_SIZE (64U) +#endif +#define MAPPED_PROGMEM_END (MAPPED_PROGMEM_START + MAPPED_PROGMEM_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROD_SIGNATURES_START (0x1103) +# define PROD_SIGNATURES_SIZE (61) +# define PROD_SIGNATURES_PAGE_SIZE (64) +#else +# define PROD_SIGNATURES_START (0x1103U) +# define PROD_SIGNATURES_SIZE (61U) +# define PROD_SIGNATURES_PAGE_SIZE (64U) +#endif +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define SIGNATURES_START (0x1100) +# define SIGNATURES_SIZE (3) +# define SIGNATURES_PAGE_SIZE (64) +#else +# define SIGNATURES_START (0x1100U) +# define SIGNATURES_SIZE (3U) +# define SIGNATURES_PAGE_SIZE (64U) +#endif +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define USER_SIGNATURES_START (0x1300) +# define USER_SIGNATURES_SIZE (32) +# define USER_SIGNATURES_PAGE_SIZE (32) +#else +# define USER_SIGNATURES_START (0x1300U) +# define USER_SIGNATURES_SIZE (32U) +# define USER_SIGNATURES_PAGE_SIZE (32U) +#endif +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) +# define PROGMEM_START (0x0000) +# define PROGMEM_SIZE (8192) +# define PROGMEM_PAGE_SIZE (64) +#else +# define PROGMEM_START (0x0000U) +# define PROGMEM_SIZE (8192U) +# define PROGMEM_PAGE_SIZE (64U) +#endif +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 10 + +/* Fuse Byte 0 (WDTCFG) */ +#define FUSE_PERIOD0 (unsigned char)_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_PERIOD1 (unsigned char)_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_PERIOD2 (unsigned char)_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_PERIOD3 (unsigned char)_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WINDOW0 (unsigned char)_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WINDOW1 (unsigned char)_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WINDOW2 (unsigned char)_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WINDOW3 (unsigned char)_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE0_DEFAULT (0x0) +#define FUSE_WDTCFG_DEFAULT (0x0) + +/* Fuse Byte 1 (BODCFG) */ +#define FUSE_SLEEP0 (unsigned char)_BV(0) /* BOD Operation in Sleep Mode Bit 0 */ +#define FUSE_SLEEP1 (unsigned char)_BV(1) /* BOD Operation in Sleep Mode Bit 1 */ +#define FUSE_ACTIVE0 (unsigned char)_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_ACTIVE1 (unsigned char)_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_SAMPFREQ (unsigned char)_BV(4) /* BOD Sample Frequency */ +#define FUSE_LVL0 (unsigned char)_BV(5) /* BOD Level Bit 0 */ +#define FUSE_LVL1 (unsigned char)_BV(6) /* BOD Level Bit 1 */ +#define FUSE_LVL2 (unsigned char)_BV(7) /* BOD Level Bit 2 */ +#define FUSE1_DEFAULT (0x0) +#define FUSE_BODCFG_DEFAULT (0x0) + +/* Fuse Byte 2 (OSCCFG) */ +#define FUSE_FREQSEL0 (unsigned char)_BV(0) /* Frequency Select Bit 0 */ +#define FUSE_FREQSEL1 (unsigned char)_BV(1) /* Frequency Select Bit 1 */ +#define FUSE_OSCLOCK (unsigned char)_BV(7) /* Oscillator Lock */ +#define FUSE2_DEFAULT (0x2) +#define FUSE_OSCCFG_DEFAULT (0x2) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 (TCD0CFG) */ +#define FUSE_CMPA (unsigned char)_BV(0) /* Compare A Default Output Value */ +#define FUSE_CMPB (unsigned char)_BV(1) /* Compare B Default Output Value */ +#define FUSE_CMPC (unsigned char)_BV(2) /* Compare C Default Output Value */ +#define FUSE_CMPD (unsigned char)_BV(3) /* Compare D Default Output Value */ +#define FUSE_CMPAEN (unsigned char)_BV(4) /* Compare A Output Enable */ +#define FUSE_CMPBEN (unsigned char)_BV(5) /* Compare B Output Enable */ +#define FUSE_CMPCEN (unsigned char)_BV(6) /* Compare C Output Enable */ +#define FUSE_CMPDEN (unsigned char)_BV(7) /* Compare D Output Enable */ +#define FUSE4_DEFAULT (0x0) +#define FUSE_TCD0CFG_DEFAULT (0x0) + +/* Fuse Byte 5 (SYSCFG0) */ +#define FUSE_EESAVE (unsigned char)_BV(0) /* EEPROM Save */ +#define FUSE_RSTPINCFG0 (unsigned char)_BV(2) /* Reset Pin Configuration Bit 0 */ +#define FUSE_RSTPINCFG1 (unsigned char)_BV(3) /* Reset Pin Configuration Bit 1 */ +#define FUSE_CRCSRC0 (unsigned char)_BV(6) /* CRC Source Bit 0 */ +#define FUSE_CRCSRC1 (unsigned char)_BV(7) /* CRC Source Bit 1 */ +#define FUSE5_DEFAULT (0xc4) +#define FUSE_SYSCFG0_DEFAULT (0xc4) + +/* Fuse Byte 6 (SYSCFG1) */ +#define FUSE_SUT0 (unsigned char)_BV(0) /* Startup Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)_BV(1) /* Startup Time Bit 1 */ +#define FUSE_SUT2 (unsigned char)_BV(2) /* Startup Time Bit 2 */ +#define FUSE6_DEFAULT (0x7) +#define FUSE_SYSCFG1_DEFAULT (0x7) + +/* Fuse Byte 7 (APPEND) */ +#define FUSE7_DEFAULT (0x0) +#define FUSE_APPEND_DEFAULT (0x0) + +/* Fuse Byte 8 (BOOTEND) */ +#define FUSE8_DEFAULT (0x0) +#define FUSE_BOOTEND_DEFAULT (0x0) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#ifdef LOCKBITS_DEFAULT +#undef LOCKBITS_DEFAULT +#endif //LOCKBITS_DEFAULT +#define LOCKBITS_DEFAULT (0xc5) + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x20 + + +#endif /* #ifdef _AVR_ATTINY817_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iotn828.h b/hardware/tools/avr/avr/include/avr/iotn828.h new file mode 100644 index 0000000000000000000000000000000000000000..c31094e748fd1facc135025fcea342781ca56145 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn828.h @@ -0,0 +1,911 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATTINY828_H_INCLUDED +#define _AVR_ATTINY828_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn828.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0x00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x01) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x02) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define PUEA _SFR_IO8(0x03) + +#define PINB _SFR_IO8(0x04) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x05) +#define DDRB7 7 +// Inserted "DDB7" from "DDRB7" due to compatibility +#define DDB7 7 +#define DDRB6 6 +// Inserted "DDB6" from "DDRB6" due to compatibility +#define DDB6 6 +#define DDRB5 5 +// Inserted "DDB5" from "DDRB5" due to compatibility +#define DDB5 5 +#define DDRB4 4 +// Inserted "DDB4" from "DDRB4" due to compatibility +#define DDB4 4 +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x06) +#define PORTB7 7 +#define PORTB6 6 +#define PORTB5 5 +#define PORTB4 4 +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PUEB _SFR_IO8(0x07) + +#define PINC _SFR_IO8(0x08) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x09) +#define DDRC7 7 +// Inserted "DDC7" from "DDRC7" due to compatibility +#define DDC7 7 +#define DDRC6 6 +// Inserted "DDC6" from "DDRC6" due to compatibility +#define DDC6 6 +#define DDRC5 5 +// Inserted "DDC5" from "DDRC5" due to compatibility +#define DDC5 5 +#define DDRC4 4 +// Inserted "DDC4" from "DDRC4" due to compatibility +#define DDC4 4 +#define DDRC3 3 +// Inserted "DDC3" from "DDRC3" due to compatibility +#define DDC3 3 +#define DDRC2 2 +// Inserted "DDC2" from "DDRC2" due to compatibility +#define DDC2 2 +#define DDRC1 1 +// Inserted "DDC1" from "DDRC1" due to compatibility +#define DDC1 1 +#define DDRC0 0 +// Inserted "DDC0" from "DDRC0" due to compatibility +#define DDC0 0 + +#define PORTC _SFR_IO8(0x0A) +#define PORTC7 7 +#define PORTC6 6 +#define PORTC5 5 +#define PORTC4 4 +#define PORTC3 3 +#define PORTC2 2 +#define PORTC1 1 +#define PORTC0 0 + +#define PUEC _SFR_IO8(0x0B) + +#define PIND _SFR_IO8(0x0C) +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0D) +#define DDRD3 3 +// Inserted "DDD3" from "DDRD3" due to compatibility +#define DDD3 3 +#define DDRD2 2 +// Inserted "DDD2" from "DDRD2" due to compatibility +#define DDD2 2 +#define DDRD1 1 +// Inserted "DDD1" from "DDRD1" due to compatibility +#define DDD1 1 +#define DDRD0 0 +// Inserted "DDD0" from "DDRD0" due to compatibility +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0E) +#define PORTD3 3 +#define PORTD2 2 +#define PORTD1 1 +#define PORTD0 0 + +#define PUED _SFR_IO8(0x0F) + +/* Reserved [0x10..0x13] */ + +#define PHDE _SFR_IO8(0x14) +#define PHDEC 2 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) + +#define EEAR _SFR_IO8(0x21) + +/* Reserved [0x22] */ + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x24) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0x28) + +/* Reserved [0x29] */ + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) + +#define ACSRB _SFR_IO8(0x2F) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define HLEV 6 +#define HSEL 7 + +#define ACSRA _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACPMUX2 6 +#define ACD 7 + +/* Reserved [0x31..0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define IVSEL 1 + +#define CCP _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RWFLB 3 +#define RWWSRE 4 +#define RSIG 5 +#define RWWSB 6 +#define SPMIE 7 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 + +/* Reserved [0x62..0x63] */ + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSART0 1 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1< + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x25F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x0C + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN84_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn841.h b/hardware/tools/avr/avr/include/avr/iotn841.h new file mode 100644 index 0000000000000000000000000000000000000000..f8d9823a8ec0fc914edf005a6906fde90dca0a68 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn841.h @@ -0,0 +1,903 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_ATTINY841_H_INCLUDED +#define _AVR_ATTINY841_H_INCLUDED + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn841.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +#define ADCSRB _SFR_IO8(0x04) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define ADLAR 3 + +#define ADCSRA _SFR_IO8(0x05) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +/* Combine ADCL and ADCH */ +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x06) +#endif +#define ADCW _SFR_IO16(0x06) + +#define ADCL _SFR_IO8(0x06) +#define ADCH _SFR_IO8(0x07) + +#define ADMUXB _SFR_IO8(0x08) +#define GSEL0 0 +#define GSEL1 1 +#define REFS0 5 +#define REFS1 6 +#define REFS2 7 + +#define ADMUXA _SFR_IO8(0x09) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define MUX5 5 + +#define ACSR0A _SFR_IO8(0x0A) +#define ACIS00 0 +#define ACIS01 1 +#define ACIC0 2 +#define ACIE0 3 +#define ACI0 4 +#define ACO0 5 +#define ACPMUX2 6 +#define ACD0 7 + +#define ACSR0B _SFR_IO8(0x0B) +#define ACPMUX0 0 +#define ACPMUX1 1 +#define ACNMUX0 2 +#define ACNMUX1 3 +#define ACOE0 4 +#define HLEV0 6 +#define HSEL0 7 + +#define ACSR1A _SFR_IO8(0x0C) +#define ACIS10 0 +#define ACIS11 1 +#define ACIC1 2 +#define ACIE1 3 +#define ACI1 4 +#define ACO1 5 +#define ACBG1 6 +#define ACD1 7 + +#define ACSR1B _SFR_IO8(0x0D) +#define ACME1 2 +#define ACOE1 4 +#define HLEV1 6 +#define HSEL1 7 + +#define TIFR1 _SFR_IO8(0x0E) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define TIMSK1 _SFR_IO8(0x0F) +#define TOIE1 0 +#define OCIE1A 1 +#define OCIE1B 2 +#define ICIE1 5 + +#define TIFR2 _SFR_IO8(0x10) +#define TOV2 0 +#define OCF2A 1 +#define OCF2B 2 +#define ICF2 5 + +#define TIMSK2 _SFR_IO8(0x11) +#define TOIE2 0 +#define OCIE2A 1 +#define OCIE2B 2 +#define ICIE2 5 + +#define PCMSK0 _SFR_IO8(0x12) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define GPIOR0 _SFR_IO8(0x13) + +#define GPIOR1 _SFR_IO8(0x14) + +#define GPIOR2 _SFR_IO8(0x15) + +#define PINB _SFR_IO8(0x16) +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDRB3 3 +// Inserted "DDB3" from "DDRB3" due to compatibility +#define DDB3 3 +#define DDRB2 2 +// Inserted "DDB2" from "DDRB2" due to compatibility +#define DDB2 2 +#define DDRB1 1 +// Inserted "DDB1" from "DDRB1" due to compatibility +#define DDB1 1 +#define DDRB0 0 +// Inserted "DDB0" from "DDRB0" due to compatibility +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PORTB3 3 +#define PORTB2 2 +#define PORTB1 1 +#define PORTB0 0 + +#define PINA _SFR_IO8(0x19) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0x1A) +#define DDRA7 7 +// Inserted "DDA7" from "DDRA7" due to compatibility +#define DDA7 7 +#define DDRA6 6 +// Inserted "DDA6" from "DDRA6" due to compatibility +#define DDA6 6 +#define DDRA5 5 +// Inserted "DDA5" from "DDRA5" due to compatibility +#define DDA5 5 +#define DDRA4 4 +// Inserted "DDA4" from "DDRA4" due to compatibility +#define DDA4 4 +#define DDRA3 3 +// Inserted "DDA3" from "DDRA3" due to compatibility +#define DDA3 3 +#define DDRA2 2 +// Inserted "DDA2" from "DDRA2" due to compatibility +#define DDA2 2 +#define DDRA1 1 +// Inserted "DDA1" from "DDRA1" due to compatibility +#define DDA1 1 +#define DDRA0 0 +// Inserted "DDA0" from "DDRA0" due to compatibility +#define DDA0 0 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA7 7 +#define PORTA6 6 +#define PORTA5 5 +#define PORTA4 4 +#define PORTA3 3 +#define PORTA2 2 +#define PORTA1 1 +#define PORTA0 0 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) + +/* Combine EEARL and EEARH */ +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PCMSK1 _SFR_IO8(0x20) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 + +#define WDTCSR _SFR_IO8(0x21) +#define WDE 3 +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define TCCR1C _SFR_IO8(0x22) +#define FOC1B 6 +#define FOC1A 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSR 0 +#define TSM 7 + +/* Combine ICR1L and ICR1H */ +#define ICR1 _SFR_IO16(0x24) + +#define ICR1L _SFR_IO8(0x24) +#define ICR1H _SFR_IO8(0x25) + +/* Reserved [0x26..0x27] */ + +/* Combine OCR1BL and OCR1BH */ +#define OCR1B _SFR_IO16(0x28) + +#define OCR1BL _SFR_IO8(0x28) +#define OCR1BH _SFR_IO8(0x29) + +/* Combine OCR1AL and OCR1AH */ +#define OCR1A _SFR_IO16(0x2A) + +#define OCR1AL _SFR_IO8(0x2A) +#define OCR1AH _SFR_IO8(0x2B) + +/* Combine TCNT1L and TCNT1H */ +#define TCNT1 _SFR_IO16(0x2C) + +#define TCNT1L _SFR_IO8(0x2C) +#define TCNT1H _SFR_IO8(0x2D) + +#define TCCR1B _SFR_IO8(0x2E) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define WGM12 3 +#define WGM13 4 +#define ICES1 6 +#define ICNC1 7 + +#define TCCR1A _SFR_IO8(0x2F) +#define WGM10 0 +#define WGM11 1 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define TCCR0A _SFR_IO8(0x30) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +/* Reserved [0x31] */ + +#define TCNT0 _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define FOC0B 6 +#define FOC0A 7 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 + +#define OCR0A _SFR_IO8(0x36) + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RSIG 5 + +#define TIFR0 _SFR_IO8(0x38) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIMSK0 _SFR_IO8(0x39) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 + +#define GIFR _SFR_IO8(0x3A) +#define PCIF0 4 +#define PCIF1 5 +#define INTF0 6 + +#define GIMSK _SFR_IO8(0x3B) +#define PCIE0 4 +#define PCIE1 5 +#define INT0 6 + +#define OCR0B _SFR_IO8(0x3C) + +/* SP [0x3D..0x3E] */ + +/* SREG [0x3F] */ + +#define DIDR0 _SFR_MEM8(0x60) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define ADC3D 3 +#define ADC4D 4 +#define ADC5D 5 +#define ADC6D 6 +#define ADC7D 7 + +#define DIDR1 _SFR_MEM8(0x61) +#define ADC11D 0 +#define ADC10D 1 +#define ADC8D 2 +#define ADC9D 3 + +#define PUEB _SFR_MEM8(0x62) + +#define PUEA _SFR_MEM8(0x63) + +#define PORTCR _SFR_MEM8(0x64) +#define BBMB 1 +#define BBMA 0 + +#define REMAP _SFR_MEM8(0x65) +#define U0MAP 0 +#define SPIMAP 1 + +#define TOCPMCOE _SFR_MEM8(0x66) +#define TOCC0OE 0 +#define TOCC1OE 1 +#define TOCC2OE 2 +#define TOCC3OE 3 +#define TOCC4OE 4 +#define TOCC5OE 5 +#define TOCC6OE 6 +#define TOCC7OE 7 + +#define TOCPMSA0 _SFR_MEM8(0x67) +#define TOCC0S0 0 +#define TOCC0S1 1 +#define TOCC1S0 2 +#define TOCC1S1 3 +#define TOCC2S0 4 +#define TOCC2S1 5 +#define TOCC3S0 6 +#define TOCC3S1 7 + +#define TOCPMSA1 _SFR_MEM8(0x68) +#define TOCC4S0 0 +#define TOCC4S1 1 +#define TOCC5S0 2 +#define TOCC5S1 3 +#define TOCC6S0 4 +#define TOCC6S1 5 +#define TOCC7S0 6 +#define TOCC7S1 7 + +/* Reserved [0x69] */ + +#define PHDE _SFR_MEM8(0x6A) +#define PHDEA0 0 +#define PHDEA1 1 + +/* Reserved [0x6B..0x6F] */ + +#define PRR _SFR_MEM8(0x70) +#define PRADC 0 +#define PRTIM0 1 +#define PRTIM1 2 +#define PRTIM2 3 +#define PRSPI 4 +#define PRUSART0 5 +#define PRUSART1 6 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn84a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny84A_H_ +#define _AVR_ATtiny84A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PRR _SFR_IO8(0x00) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1< + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x25F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x0B + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) + +#endif /* _AVR_IOTN85_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn861.h b/hardware/tools/avr/avr/include/avr/iotn861.h new file mode 100644 index 0000000000000000000000000000000000000000..16f1cf0c72338a69ac8fa01c35030c62699506fa --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn861.h @@ -0,0 +1,94 @@ +/* Copyright (c) 2006, Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */ + +/* avr/iotn861.h - definitions for ATtiny861 */ + +#ifndef _AVR_IOTN861_H_ +#define _AVR_IOTN861_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 64 +#define RAMSTART (0x60) +#define RAMEND 0x25F +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_DWEN (unsigned char)~_BV(6) +#define FUSE_RSTDISBL (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +#define EFUSE_DEFAULT (0xFF) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x0D + +#define SLEEP_MODE_IDLE (0x00<<3) +#define SLEEP_MODE_ADC (0x01<<3) +#define SLEEP_MODE_PWR_DOWN (0x02<<3) +#define SLEEP_MODE_STANDBY (0x03<<3) + +#endif /* _AVR_IOTN861_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotn861a.h b/hardware/tools/avr/avr/include/avr/iotn861a.h new file mode 100644 index 0000000000000000000000000000000000000000..efa691e013b87f2e031743dba67242de7f4caf25 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotn861a.h @@ -0,0 +1,988 @@ +/* Copyright (c) 2009 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */ + +/* avr/iotn861a.h - definitions for ATtiny861A */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn861a.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny861A_H_ +#define _AVR_ATtiny861A_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define TCCR1E _SFR_IO8(0x00) +#define OC1OE0 0 +#define OC1OE1 1 +#define OC1OE2 2 +#define OC1OE3 3 +#define OC1OE4 4 +#define OC1OE5 5 + +#define DIDR0 _SFR_IO8(0x01) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define AREFD 3 +#define ADC3D 4 +#define ADC4D 5 +#define ADC5D 6 +#define ADC6D 7 + +#define DIDR1 _SFR_IO8(0x02) +#define ADC7D 4 +#define ADC8D 5 +#define ADC9D 6 +#define ADC10D 7 + +#define ADCSRB _SFR_IO8(0x03) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define MUX5 3 +#define REFS2 4 +#define IPR 5 +#define GSEL 6 +#define BIN 7 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) + +#define ADCL _SFR_IO8(0x04) +#define ADCL0 0 +#define ADCL1 1 +#define ADCL2 2 +#define ADCL3 3 +#define ADCL4 4 +#define ADCL5 5 +#define ADCL6 6 +#define ADCL7 7 + +#define ADCH _SFR_IO8(0x05) +#define ADCH0 0 +#define ADCH1 1 +#define ADCH2 2 +#define ADCH3 3 +#define ADCH4 4 +#define ADCH5 5 +#define ADCH6 6 +#define ADCH7 7 + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSRA _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACME 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define ACSRB _SFR_IO8(0x09) +#define ACM0 0 +#define ACM1 1 +#define ACM2 2 +#define HLEV 6 +#define HSEL 7 + +#define GPIOR0 _SFR_IO8(0x0A) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define GPIOR1 _SFR_IO8(0x0B) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x0C) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define USICR _SFR_IO8(0x0D) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x0E) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x0F) +#define USIDR0 0 +#define USIDR1 1 +#define USIDR2 2 +#define USIDR3 3 +#define USIDR4 4 +#define USIDR5 5 +#define USIDR6 6 +#define USIDR7 7 + +#define USIBR _SFR_IO8(0x10) +#define USIBR0 0 +#define USIBR1 1 +#define USIBR2 2 +#define USIBR3 3 +#define USIBR4 4 +#define USIBR5 5 +#define USIBR6 6 +#define USIBR7 7 + +#define USIPP _SFR_IO8(0x11) +#define USIPOS 0 + +#define OCR0B _SFR_IO8(0x12) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define OCR0A _SFR_IO8(0x13) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define TCNT0H _SFR_IO8(0x14) +#define TCNT0H_0 0 +#define TCNT0H_1 1 +#define TCNT0H_2 2 +#define TCNT0H_3 3 +#define TCNT0H_4 4 +#define TCNT0H_5 5 +#define TCNT0H_6 6 +#define TCNT0H_7 7 + +#define TCCR0A _SFR_IO8(0x15) +#define WGM00 0 +#define ACIC0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x1D) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x1E) + +#define EEARL _SFR_IO8(0x1E) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x1F) +#define EEAR8 0 + +#define DWDR _SFR_IO8(0x20) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define PCMSK1 _SFR_IO8(0x22) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 +#define PCINT12 4 +#define PCINT13 5 +#define PCINT14 6 +#define PCINT15 7 + +#define PCMSK0 _SFR_IO8(0x23) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define DT1 _SFR_IO8(0x24) +#define DT1L0 0 +#define DT1L1 1 +#define DT1L2 2 +#define DT1L3 3 +#define DT1H0 4 +#define DT1H1 5 +#define DT1H2 6 +#define DT1H3 7 + +#define TC1H _SFR_IO8(0x25) +#define TC18 0 +#define TC19 1 + +#define TCCR1D _SFR_IO8(0x26) +#define WGM10 0 +#define WGM11 1 +#define FPF1 2 +#define FPAC1 3 +#define FPES1 4 +#define FPNC1 5 +#define FPEN1 6 +#define FPIE1 7 + +#define TCCR1C _SFR_IO8(0x27) +#define PWM1D 0 +#define FOC1D 1 +#define COM1D0 2 +#define COM1D1 3 +#define COM1B0S 4 +#define COM1B1S 5 +#define COM1A0S 6 +#define COM1A1S 7 + +#define CLKPR _SFR_IO8(0x28) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PCKE 2 +#define LSM 7 + +#define OCR1D _SFR_IO8(0x2A) +#define OCR1D0 0 +#define OCR1D1 1 +#define OCR1D2 2 +#define OCR1D3 3 +#define OCR1D4 4 +#define OCR1D5 5 +#define OCR1D6 6 +#define OCR1D7 7 + +#define OCR1C _SFR_IO8(0x2B) +#define OCR1C0 0 +#define OCR1C1 1 +#define OCR1C2 2 +#define OCR1C3 3 +#define OCR1C4 4 +#define OCR1C5 5 +#define OCR1C6 6 +#define OCR1C7 7 + +#define OCR1B _SFR_IO8(0x2C) +#define OCR1B0 0 +#define OCR1B1 1 +#define OCR1B2 2 +#define OCR1B3 3 +#define OCR1B4 4 +#define OCR1B5 5 +#define OCR1B6 6 +#define OCR1B7 7 + +#define OCR1A _SFR_IO8(0x2D) +#define OCR1A0 0 +#define OCR1A1 1 +#define OCR1A2 2 +#define OCR1A3 3 +#define OCR1A4 4 +#define OCR1A5 5 +#define OCR1A6 6 +#define OCR1A7 7 + +#define TCNT1 _SFR_IO8(0x2E) +#define TC1H_0 0 +#define TC1H_1 1 +#define TC1H_2 2 +#define TC1H_3 3 +#define TC1H_4 4 +#define TC1H_5 5 +#define TC1H_6 6 +#define TC1H_7 7 + +#define TCCR1B _SFR_IO8(0x2F) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CS13 3 +#define DTPS10 4 +#define DTPS11 5 +#define PSR1 6 +#define PWM1X 7 + +#define TCCR1A _SFR_IO8(0x30) +#define PWM1B 0 +#define PWM1A 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define OSCCAL _SFR_IO8(0x31) +#define CAL0 0 +#define CAL1 1 +#define CAL2 2 +#define CAL3 3 +#define CAL4 4 +#define CAL5 5 +#define CAL6 6 +#define CAL7 7 + +#define TCNT0L _SFR_IO8(0x32) +#define TCNT0L_0 0 +#define TCNT0L_1 1 +#define TCNT0L_2 2 +#define TCNT0L_3 3 +#define TCNT0L_4 4 +#define TCNT0L_5 5 +#define TCNT0L_6 6 +#define TCNT0L_7 7 + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define PSR0 3 +#define TSM 4 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define BODSE 2 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define PUD 6 +#define BODS 7 + +#define PRR _SFR_IO8(0x36) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn87.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny87_H_ +#define _AVR_ATtiny87_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINA _SFR_IO8(0x00) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x01) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x02) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 +#define PORTA4 4 +#define PORTA5 5 +#define PORTA6 6 +#define PORTA7 7 + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 2 +#define BBMA 4 +#define BBMB 5 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEAR _SFR_IO16(0x21) + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define EEARH _SFR_IO8(0x22) +#define EEAR8 0 + +#define GTCCR _SFR_IO8(0x23) +#define PSR1 0 +#define PSR0 1 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x25) +#define WGM00 0 +#define WGM01 1 +#define COM0A0 6 +#define COM0A1 7 + +#define TCCR0B _SFR_IO8(0x26) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define FOC0A 7 + +#define TCNT0 _SFR_IO8(0x27) +#define TCNT00 0 +#define TCNT01 1 +#define TCNT02 2 +#define TCNT03 3 +#define TCNT04 4 +#define TCNT05 5 +#define TCNT06 6 +#define TCNT07 7 + +#define OCR0A _SFR_IO8(0x28) +#define OCR00 0 +#define OCR01 1 +#define OCR02 2 +#define OCR03 3 +#define OCR04 4 +#define OCR05 5 +#define OCR06 6 +#define OCR07 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACIRS 6 +#define ACD 7 + +#define DWDR _SFR_IO8(0x31) +#define DWDR0 0 +#define DWDR1 1 +#define DWDR2 2 +#define DWDR3 3 +#define DWDR4 4 +#define DWDR5 5 +#define DWDR6 6 +#define DWDR7 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SPMEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define SIGRD 5 +#define RWWSB 6 + +#define WDTCR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define CLKCSR _SFR_MEM8(0x62) +#define CLKC0 0 +#define CLKC1 1 +#define CLKC2 2 +#define CLKC3 3 +#define CLKRDY 4 +#define CLKCCE 7 + +#define CLKSELR _SFR_MEM8(0x63) +#define CSEL0 0 +#define CSEL1 1 +#define CSEL2 2 +#define CSEL3 3 +#define CSUT0 4 +#define CSUT1 5 +#define COUT 6 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 +#define PRSPI 4 +#define PRLIN 5 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn88.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_IOTN88_H_ +#define _AVR_IOTN88_H_ 1 + +/* Registers and associated bit numbers */ + +#define PINB _SFR_IO8(0x03) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x04) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x05) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 +#define PORTB4 4 +#define PORTB5 5 +#define PORTB6 6 +#define PORTB7 7 + +#define PINC _SFR_IO8(0x06) +#define PINC0 0 +#define PINC1 1 +#define PINC2 2 +#define PINC3 3 +#define PINC4 4 +#define PINC5 5 +#define PINC6 6 +#define PINC7 7 + +#define DDRC _SFR_IO8(0x07) +#define DDC0 0 +#define DDC1 1 +#define DDC2 2 +#define DDC3 3 +#define DDC4 4 +#define DDC5 5 +#define DDC6 6 +#define DDC7 7 + +#define PORTC _SFR_IO8(0x08) +#define PORTC0 0 +#define PORTC1 1 +#define PORTC2 2 +#define PORTC3 3 +#define PORTC4 4 +#define PORTC5 5 +#define PORTC6 6 +#define PORTC7 7 + +#define PIND _SFR_IO8(0x09) +#define PIND0 0 +#define PIND1 1 +#define PIND2 2 +#define PIND3 3 +#define PIND4 4 +#define PIND5 5 +#define PIND6 6 +#define PIND7 7 + +#define DDRD _SFR_IO8(0x0A) +#define DDD0 0 +#define DDD1 1 +#define DDD2 2 +#define DDD3 3 +#define DDD4 4 +#define DDD5 5 +#define DDD6 6 +#define DDD7 7 + +#define PORTD _SFR_IO8(0x0B) +#define PORTD0 0 +#define PORTD1 1 +#define PORTD2 2 +#define PORTD3 3 +#define PORTD4 4 +#define PORTD5 5 +#define PORTD6 6 +#define PORTD7 7 + +#define PINA _SFR_IO8(0x0C) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 + +#define DDRA _SFR_IO8(0x0D) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 + +#define PORTA _SFR_IO8(0x0E) +#define PORTA0 0 +#define PORTA1 1 +#define PORTA2 2 +#define PORTA3 3 + +#define PORTCR _SFR_IO8(0x12) +#define PUDA 0 +#define PUDB 1 +#define PUDC 2 +#define PUDD 3 +#define BBMA 4 +#define BBMB 5 +#define BBMC 6 +#define BBMD 7 + +#define TIFR0 _SFR_IO8(0x15) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 + +#define TIFR1 _SFR_IO8(0x16) +#define TOV1 0 +#define OCF1A 1 +#define OCF1B 2 +#define ICF1 5 + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 +#define PCIF1 1 +#define PCIF2 2 +#define PCIF3 3 + +#define EIFR _SFR_IO8(0x1C) +#define INTF0 0 +#define INTF1 1 + +#define EIMSK _SFR_IO8(0x1D) +#define INT0 0 +#define INT1 1 + +#define GPIOR0 _SFR_IO8(0x1E) +#define GPIOR00 0 +#define GPIOR01 1 +#define GPIOR02 2 +#define GPIOR03 3 +#define GPIOR04 4 +#define GPIOR05 5 +#define GPIOR06 6 +#define GPIOR07 7 + +#define EECR _SFR_IO8(0x1F) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +#define EEDR _SFR_IO8(0x20) +#define EEDR0 0 +#define EEDR1 1 +#define EEDR2 2 +#define EEDR3 3 +#define EEDR4 4 +#define EEDR5 5 +#define EEDR6 6 +#define EEDR7 7 + +#define EEARL _SFR_IO8(0x21) +#define EEAR0 0 +#define EEAR1 1 +#define EEAR2 2 +#define EEAR3 3 +#define EEAR4 4 +#define EEAR5 5 +#define EEAR6 6 +#define EEAR7 7 + +#define GTCCR _SFR_IO8(0x23) +#define PSRSYNC 0 +#define TSM 7 + +#define TCCR0A _SFR_IO8(0x25) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define CTC0 3 + +#define TCNT0 _SFR_IO8(0x26) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define OCR0A _SFR_IO8(0x27) +#define OCR0A_0 0 +#define OCR0A_1 1 +#define OCR0A_2 2 +#define OCR0A_3 3 +#define OCR0A_4 4 +#define OCR0A_5 5 +#define OCR0A_6 6 +#define OCR0A_7 7 + +#define OCR0B _SFR_IO8(0x28) +#define OCR0B_0 0 +#define OCR0B_1 1 +#define OCR0B_2 2 +#define OCR0B_3 3 +#define OCR0B_4 4 +#define OCR0B_5 5 +#define OCR0B_6 6 +#define OCR0B_7 7 + +#define GPIOR1 _SFR_IO8(0x2A) +#define GPIOR10 0 +#define GPIOR11 1 +#define GPIOR12 2 +#define GPIOR13 3 +#define GPIOR14 4 +#define GPIOR15 5 +#define GPIOR16 6 +#define GPIOR17 7 + +#define GPIOR2 _SFR_IO8(0x2B) +#define GPIOR20 0 +#define GPIOR21 1 +#define GPIOR22 2 +#define GPIOR23 3 +#define GPIOR24 4 +#define GPIOR25 5 +#define GPIOR26 6 +#define GPIOR27 7 + +#define SPCR _SFR_IO8(0x2C) +#define SPR0 0 +#define SPR1 1 +#define CPHA 2 +#define CPOL 3 +#define MSTR 4 +#define DORD 5 +#define SPE 6 +#define SPIE 7 + +#define SPSR _SFR_IO8(0x2D) +#define SPI2X 0 +#define WCOL 6 +#define SPIF 7 + +#define SPDR _SFR_IO8(0x2E) +#define SPDR0 0 +#define SPDR1 1 +#define SPDR2 2 +#define SPDR3 3 +#define SPDR4 4 +#define SPDR5 5 +#define SPDR6 6 +#define SPDR7 7 + +#define ACSR _SFR_IO8(0x30) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define SMCR _SFR_IO8(0x33) +#define SE 0 +#define SM0 1 +#define SM1 2 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define BODSE 5 +#define BODS 6 + +#define SPMCSR _SFR_IO8(0x37) +#define SELFPRGEN 0 +#define PGERS 1 +#define PGWRT 2 +#define RFLB 3 +#define CTPB 4 +#define RWWSB 6 + +#define WDTCSR _SFR_MEM8(0x60) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PRR _SFR_MEM8(0x64) +#define PRADC 0 +#define PRSPI 2 +#define PRTIM1 3 +#define PRTIM0 5 +#define PRTWI 7 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotn9.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATtiny9_H_ +#define _AVR_ATtiny9_H_ 1 + + +/* Registers and associated bit numbers. */ + +#define PINB _SFR_IO8(0x00) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 + +#define DDRB _SFR_IO8(0x01) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 + +#define PORTB _SFR_IO8(0x02) +#define PORTB0 0 +#define PORTB1 1 +#define PORTB2 2 +#define PORTB3 3 + +#define PUEB _SFR_IO8(0x03) +#define PUEB0 0 +#define PUEB1 1 +#define PUEB2 2 +#define PUEB3 3 + +#define PORTCR _SFR_IO8(0x0C) +#define BBMB 1 + +#define PCMSK _SFR_IO8(0x10) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 + +#define PCIFR _SFR_IO8(0x11) +#define PCIF0 0 + +#define PCICR _SFR_IO8(0x12) +#define PCIE0 0 + +#define EIMSK _SFR_IO8(0x13) +#define INT0 0 + +#define EIFR _SFR_IO8(0x14) +#define INTF0 0 + +#define EICRA _SFR_IO8(0x15) +#define ISC00 0 +#define ISC01 1 + +#define DIDR0 _SFR_IO8(0x17) +#define AIN0D 0 +#define AIN1D 1 + +#define ACSR _SFR_IO8(0x1F) +#define ACIS0 0 +#define ACIS1 1 +#define ACIC 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACD 7 + +#define ICR0 _SFR_IO16(0x22) + +#define ICR0L _SFR_IO8(0x22) +#define ICR0_0 0 +#define ICR0_1 1 +#define ICR0_2 2 +#define ICR0_3 3 +#define ICR0_4 4 +#define ICR0_5 5 +#define ICR0_6 6 +#define ICR0_7 7 + +#define ICR0H _SFR_IO8(0x23) +#define ICR0_8 0 +#define ICR0_9 1 +#define ICR0_10 2 +#define ICR0_11 3 +#define ICR0_12 4 +#define ICR0_13 5 +#define ICR0_14 6 +#define ICR0_15 7 + +#define OCR0B _SFR_IO16(0x24) + +#define OCR0BL _SFR_IO8(0x24) +#define OCR0B0 0 +#define OCR0B1 1 +#define OCR0B2 2 +#define OCR0B3 3 +#define OCR0B4 4 +#define OCR0B5 5 +#define OCR0B6 6 +#define OCR0B7 7 + +#define OCR0BH _SFR_IO8(0x25) +#define OCR0B8 0 +#define OCR0B9 1 +#define OCR0B10 2 +#define OCR0B11 3 +#define OCR0B12 4 +#define OCR0B13 5 +#define OCR0B14 6 +#define OCR0B15 7 + +#define OCR0A _SFR_IO16(0x26) + +#define OCR0AL _SFR_IO8(0x26) +#define OCR0A0 0 +#define OCR0A1 1 +#define OCR0A2 2 +#define OCR0A3 3 +#define OCR0A4 4 +#define OCR0A5 5 +#define OCR0A6 6 +#define OCR0A7 7 + +#define OCR0AH _SFR_IO8(0x27) +#define OCR0A8 0 +#define OCR0A9 1 +#define OCR0A10 2 +#define OCR0A11 3 +#define OCR0A12 4 +#define OCR0A13 5 +#define OCR0A14 6 +#define OCR0A15 7 + +#define TCNT0 _SFR_IO16(0x28) + +#define TCNT0L _SFR_IO8(0x28) +#define TCNT0_0 0 +#define TCNT0_1 1 +#define TCNT0_2 2 +#define TCNT0_3 3 +#define TCNT0_4 4 +#define TCNT0_5 5 +#define TCNT0_6 6 +#define TCNT0_7 7 + +#define TCNT0H _SFR_IO8(0x29) +#define TCNT0_8 0 +#define TCNT0_9 1 +#define TCNT0_10 2 +#define TCNT0_11 3 +#define TCNT0_12 4 +#define TCNT0_13 5 +#define TCNT0_14 6 +#define TCNT0_15 7 + +#define TIFR0 _SFR_IO8(0x2A) +#define TOV0 0 +#define OCF0A 1 +#define OCF0B 2 +#define ICF0 5 + +#define TIMSK0 _SFR_IO8(0x2B) +#define TOIE0 0 +#define OCIE0A 1 +#define OCIE0B 2 +#define ICIE0 5 + +#define TCCR0C _SFR_IO8(0x2C) +#define FOC0B 6 +#define FOC0A 7 + +#define TCCR0B _SFR_IO8(0x2D) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define WGM02 3 +#define WGM03 4 +#define ICES0 6 +#define ICNC0 7 + +#define TCCR0A _SFR_IO8(0x2E) +#define WGM00 0 +#define WGM01 1 +#define COM0B0 4 +#define COM0B1 5 +#define COM0A0 6 +#define COM0A1 7 + +#define GTCCR _SFR_IO8(0x2F) +#define PSR 0 +#define TSM 7 + +#define WDTCSR _SFR_IO8(0x31) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define NVMCSR _SFR_IO8(0x32) +#define NVMBSY 7 + +#define NVMCMD _SFR_IO8(0x33) +#define NVMCMD0 0 +#define NVMCMD1 1 +#define NVMCMD2 2 +#define NVMCMD3 3 +#define NVMCMD4 4 +#define NVMCMD5 5 + +#define VLMCSR _SFR_IO8(0x34) +#define VLM0 0 +#define VLM1 1 +#define VLM2 2 +#define VLMIE 6 +#define VLMF 7 + +#define PRR _SFR_IO8(0x35) +#define PRTIM0 0 +#define PRADC 1 + +#define __AVR_HAVE_PRR ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotnx4.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +#define PRR _SFR_IO8 (0x00) +#define PRTIM1 3 +#define PRTIM0 2 +#define PRUSI 1 +#define PRADC 0 + +#define __AVR_HAVE_PRR ((1<] */ +/* 0x3F SREG [defined in ] */ + +///--- + +/* Interrupt vectors */ +/* Interrupt vector 0 is the reset vector. */ +/* External Interrupt Request 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define EXT_INT0_vect_num 1 +#define EXT_INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Pin Change Interrupt Request 0 */ +#define PCINT0_vect_num 2 +#define PCINT0_vect _VECTOR(2) +#define SIG_PIN_CHANGE0 _VECTOR(2) + +/* Pin Change Interrupt Request 1 */ +#define PCINT1_vect_num 3 +#define PCINT1_vect _VECTOR(3) +#define SIG_PIN_CHANGE1 _VECTOR(3) + +/* Watchdog Time-out */ +#define WDT_vect_num 4 +#define WDT_vect _VECTOR(4) +#define WATCHDOG_vect_num 4 +#define WATCHDOG_vect _VECTOR(4) +#define SIG_WATCHDOG_TIMEOUT _VECTOR(4) + +/* Timer/Counter1 Capture Event */ +#define TIMER1_CAPT_vect_num 5 +#define TIMER1_CAPT_vect _VECTOR(5) +#define TIM1_CAPT_vect_num 5 +#define TIM1_CAPT_vect _VECTOR(5) +#define SIG_INPUT_CAPTURE1 _VECTOR(5) + +/* Timer/Counter1 Compare Match A */ +#define TIM1_COMPA_vect_num 6 +#define TIM1_COMPA_vect _VECTOR(6) +#define SIG_OUTPUT_COMPARE1A _VECTOR(6) + +/* Timer/Counter1 Compare Match B */ +#define TIM1_COMPB_vect_num 7 +#define TIM1_COMPB_vect _VECTOR(7) +#define SIG_OUTPUT_COMPARE1B _VECTOR(7) + +/* Timer/Counter1 Overflow */ +#define TIM1_OVF_vect_num 8 +#define TIM1_OVF_vect _VECTOR(8) +#define SIG_OVERFLOW1 _VECTOR(8) + +/* Timer/Counter0 Compare Match A */ +#define TIM0_COMPA_vect_num 9 +#define TIM0_COMPA_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE0A _VECTOR(9) + +/* Timer/Counter0 Compare Match B */ +#define TIM0_COMPB_vect_num 10 +#define TIM0_COMPB_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE0B _VECTOR(10) + +/* Timer/Counter0 Overflow */ +#define TIM0_OVF_vect_num 11 +#define TIM0_OVF_vect _VECTOR(11) +#define SIG_OVERFLOW0 _VECTOR(11) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 12 +#define ANA_COMP_vect _VECTOR(12) +#define SIG_COMPARATOR _VECTOR(12) + +/* ADC Conversion Complete */ +#define ADC_vect_num 13 +#define ADC_vect _VECTOR(13) +#define SIG_ADC _VECTOR(13) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 14 +#define EE_RDY_vect _VECTOR(14) +#define SIG_EEPROM_READY _VECTOR(14) + +/* USI START */ +#define USI_START_vect_num 15 +#define USI_START_vect _VECTOR(15) +#define USI_STR_vect_num 15 +#define USI_STR_vect _VECTOR(15) +#define SIG_USI_START _VECTOR(15) + +/* USI Overflow */ +#define USI_OVF_vect_num 16 +#define USI_OVF_vect _VECTOR(16) +#define SIG_USI_OVERFLOW _VECTOR(16) + +#define _VECTORS_SIZE 34 + +#endif /* _AVR_IOTNX4_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotnx5.h b/hardware/tools/avr/avr/include/avr/iotnx5.h new file mode 100644 index 0000000000000000000000000000000000000000..4ad9052ab9298224818f72eb1d63fbde1044ae9d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotnx5.h @@ -0,0 +1,442 @@ +/* Copyright (c) 2005,2007 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */ + +/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ + +#ifndef _AVR_IOTNX5_H_ +#define _AVR_IOTNX5_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotnx5.h" +#else +# error "Attempt to include more than one file." +#endif + +/* I/O registers */ + +/* Reserved [0x00..0x02] */ + +#define ADCSRB _SFR_IO8 (0x03) +#define BIN 7 +#define ACME 6 +#define IPR 5 +#define ADTS2 2 +#define ADTS1 1 +#define ADTS0 0 + +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif +#define ADCW _SFR_IO16(0x04) +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8 (0x06) +#define ADEN 7 +#define ADSC 6 +#define ADATE 5 +#define ADIF 4 +#define ADIE 3 +#define ADPS2 2 +#define ADPS1 1 +#define ADPS0 0 + +#define ADMUX _SFR_IO8(0x07) +#define REFS1 7 +#define REFS0 6 +#define ADLAR 5 +#define REFS2 4 +#define MUX3 3 +#define MUX2 2 +#define MUX1 1 +#define MUX0 0 + +#define ACSR _SFR_IO8(0x08) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIS1 1 +#define ACIS0 0 + +/* Reserved [0x09..0x0C] */ + +#define USICR _SFR_IO8(0x0D) +#define USISIE 7 +#define USIOIE 6 +#define USIWM1 5 +#define USIWM0 4 +#define USICS1 3 +#define USICS0 2 +#define USICLK 1 +#define USITC 0 + +#define USISR _SFR_IO8(0x0E) +#define USISIF 7 +#define USIOIF 6 +#define USIPF 5 +#define USIDC 4 +#define USICNT3 3 +#define USICNT2 2 +#define USICNT1 1 +#define USICNT0 0 + +#define USIDR _SFR_IO8(0x0F) +#define USIBR _SFR_IO8(0x10) + +#define GPIOR0 _SFR_IO8(0x11) +#define GPIOR1 _SFR_IO8(0x12) +#define GPIOR2 _SFR_IO8(0x13) + +#define DIDR0 _SFR_IO8(0x14) +#define ADC0D 5 +#define ADC2D 4 +#define ADC3D 3 +#define ADC1D 2 +#define AIN1D 1 +#define AIN0D 0 + +#define PCMSK _SFR_IO8(0x15) +#define PCINT5 5 +#define PCINT4 4 +#define PCINT3 3 +#define PCINT2 2 +#define PCINT1 1 +#define PCINT0 0 + +#define PINB _SFR_IO8(0x16) +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x17) +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x18) +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +/* Reserved [0x19..0x1B] */ + +/* EEPROM Control Register EECR */ +#define EECR _SFR_IO8(0x1C) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define PRR _SFR_IO8(0x20) +#define PRTIM1 3 +#define PRTIM0 2 +#define PRUSI 1 +#define PRADC 0 + +#define __AVR_HAVE_PRR ((1<] */ +/* 0x3F SREG [defined in ] */ + +///--- + +/* Interrupt vectors */ +/* Interrupt vector 0 is the reset vector. */ +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Pin change Interrupt Request 0 */ +#define PCINT0_vect_num 2 +#define PCINT0_vect _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter1 Compare Match 1A */ +#define TIM1_COMPA_vect_num 3 +#define TIM1_COMPA_vect _VECTOR(3) +#define TIMER1_COMPA_vect_num 3 +#define TIMER1_COMPA_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(3) + +/* Timer/Counter1 Overflow */ +#define TIM1_OVF_vect_num 4 +#define TIM1_OVF_vect _VECTOR(4) +#define TIMER1_OVF_vect_num 4 +#define TIMER1_OVF_vect _VECTOR(4) +#define SIG_OVERFLOW1 _VECTOR(4) + +/* Timer/Counter0 Overflow */ +#define TIM0_OVF_vect_num 5 +#define TIM0_OVF_vect _VECTOR(5) +#define TIMER0_OVF_vect_num 5 +#define TIMER0_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW0 _VECTOR(5) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 6 +#define EE_RDY_vect _VECTOR(6) +#define SIG_EEPROM_READY _VECTOR(6) + +/* Analog comparator */ +#define ANA_COMP_vect_num 7 +#define ANA_COMP_vect _VECTOR(7) +#define SIG_COMPARATOR _VECTOR(7) + +/* ADC Conversion ready */ +#define ADC_vect_num 8 +#define ADC_vect _VECTOR(8) +#define SIG_ADC _VECTOR(8) + +/* Timer/Counter1 Compare Match B */ +#define TIM1_COMPB_vect_num 9 +#define TIM1_COMPB_vect _VECTOR(9) +#define TIMER1_COMPB_vect_num 9 +#define TIMER1_COMPB_vect _VECTOR(9) +#define SIG_OUTPUT_COMPARE1B _VECTOR(9) + +/* Timer/Counter0 Compare Match A */ +#define TIM0_COMPA_vect_num 10 +#define TIM0_COMPA_vect _VECTOR(10) +#define TIMER0_COMPA_vect_num 10 +#define TIMER0_COMPA_vect _VECTOR(10) +#define SIG_OUTPUT_COMPARE0A _VECTOR(10) + +/* Timer/Counter0 Compare Match B */ +#define TIM0_COMPB_vect_num 11 +#define TIM0_COMPB_vect _VECTOR(11) +#define TIMER0_COMPB_vect_num 11 +#define TIMER0_COMPB_vect _VECTOR(11) +#define SIG_OUTPUT_COMPARE0B _VECTOR(11) + +/* Watchdog Time-out */ +#define WDT_vect_num 12 +#define WDT_vect _VECTOR(12) +#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) + +/* USI START */ +#define USI_START_vect_num 13 +#define USI_START_vect _VECTOR(13) +#define SIG_USI_START _VECTOR(13) + +/* USI Overflow */ +#define USI_OVF_vect_num 14 +#define USI_OVF_vect _VECTOR(14) +#define SIG_USI_OVERFLOW _VECTOR(14) + +#define _VECTORS_SIZE 30 + +#endif /* _AVR_IOTNX5_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iotnx61.h b/hardware/tools/avr/avr/include/avr/iotnx61.h new file mode 100644 index 0000000000000000000000000000000000000000..3e811c180407aa3ac9995e957fa3e3bdb9ee047a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iotnx61.h @@ -0,0 +1,541 @@ +/* Copyright (c) 2006, 2007 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */ + +/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iotnx61.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_IOTNx61_H_ +#define _AVR_IOTNx61_H_ 1 + +/* Registers and associated bit numbers */ + +#define TCCR1E _SFR_IO8(0x00) +#define OC1OE0 0 +#define OC1OE1 1 +#define OC1OE2 2 +#define OC1OE3 3 +#define OC1OE4 4 +#define OC1OE5 5 + +#define DIDR0 _SFR_IO8(0x01) +#define ADC0D 0 +#define ADC1D 1 +#define ADC2D 2 +#define AREFD 3 +#define ADC3D 4 +#define ADC4D 5 +#define ADC5D 6 +#define ADC6D 7 + +#define DIDR1 _SFR_IO8(0x02) +#define ADC7D 4 +#define ADC8D 5 +#define ADC9D 6 +#define ADC10D 7 + +#define ADCSRB _SFR_IO8(0x03) +#define ADTS0 0 +#define ADTS1 1 +#define ADTS2 2 +#define MUX5 3 +#define REFS2 4 +#define IRP 5 +#define GSEL 6 +#define BIN 7 + +#define ADCW _SFR_IO16(0x04) +#ifndef __ASSEMBLER__ +#define ADC _SFR_IO16(0x04) +#endif + +#define ADCL _SFR_IO8(0x04) +#define ADCH _SFR_IO8(0x05) + +#define ADCSRA _SFR_IO8(0x06) +#define ADPS0 0 +#define ADPS1 1 +#define ADPS2 2 +#define ADIE 3 +#define ADIF 4 +#define ADATE 5 +#define ADSC 6 +#define ADEN 7 + +#define ADMUX _SFR_IO8(0x07) +#define MUX0 0 +#define MUX1 1 +#define MUX2 2 +#define MUX3 3 +#define MUX4 4 +#define ADLAR 5 +#define REFS0 6 +#define REFS1 7 + +#define ACSRA _SFR_IO8(0x08) +#define ACIS0 0 +#define ACIS1 1 +#define ACME 2 +#define ACIE 3 +#define ACI 4 +#define ACO 5 +#define ACBG 6 +#define ACD 7 + +#define ACSRB _SFR_IO8(0x09) +#define ACM0 0 +#define ACM1 1 +#define ACM2 2 +#define HLEV 6 +#define HSEL 7 + +#define GPIOR0 _SFR_IO8(0x0A) + +#define GPIOR1 _SFR_IO8(0x0B) + +#define GPIOR2 _SFR_IO8(0x0C) + +#define USICR _SFR_IO8(0x0D) +#define USITC 0 +#define USICLK 1 +#define USICS0 2 +#define USICS1 3 +#define USIWM0 4 +#define USIWM1 5 +#define USIOIE 6 +#define USISIE 7 + +#define USISR _SFR_IO8(0x0E) +#define USICNT0 0 +#define USICNT1 1 +#define USICNT2 2 +#define USICNT3 3 +#define USIDC 4 +#define USIPF 5 +#define USIOIF 6 +#define USISIF 7 + +#define USIDR _SFR_IO8(0x0F) + +#define USIBR _SFR_IO8(0x10) + +#define USIPP _SFR_IO8(0x11) +#define USIPOS 0 + +#define OCR0B _SFR_IO8(0x12) + +#define OCR0A _SFR_IO8(0x13) + +#define TCNT0H _SFR_IO8(0x14) + +#define TCCR0A _SFR_IO8(0x15) +#define WGM00 0 /* up to at least datasheet rev. B */ +#define CTC0 0 /* newer revisions; change not mentioned + * in revision history */ +#define ACIC0 3 +#define ICES0 4 +#define ICNC0 5 +#define ICEN0 6 +#define TCW0 7 + +#define PINB _SFR_IO8(0x16) +#define PINB0 0 +#define PINB1 1 +#define PINB2 2 +#define PINB3 3 +#define PINB4 4 +#define PINB5 5 +#define PINB6 6 +#define PINB7 7 + +#define DDRB _SFR_IO8(0x17) +#define DDB0 0 +#define DDB1 1 +#define DDB2 2 +#define DDB3 3 +#define DDB4 4 +#define DDB5 5 +#define DDB6 6 +#define DDB7 7 + +#define PORTB _SFR_IO8(0x18) +#define PB0 0 +#define PB1 1 +#define PB2 2 +#define PB3 3 +#define PB4 4 +#define PB5 5 +#define PB6 6 +#define PB7 7 + +#define PINA _SFR_IO8(0x19) +#define PINA0 0 +#define PINA1 1 +#define PINA2 2 +#define PINA3 3 +#define PINA4 4 +#define PINA5 5 +#define PINA6 6 +#define PINA7 7 + +#define DDRA _SFR_IO8(0x1A) +#define DDA0 0 +#define DDA1 1 +#define DDA2 2 +#define DDA3 3 +#define DDA4 4 +#define DDA5 5 +#define DDA6 6 +#define DDA7 7 + +#define PORTA _SFR_IO8(0x1B) +#define PA0 0 +#define PA1 1 +#define PA2 2 +#define PA3 3 +#define PA4 4 +#define PA5 5 +#define PA6 6 +#define PA7 7 + +/* EEPROM Control Register */ +#define EECR _SFR_IO8(0x1C) +#define EERE 0 +#define EEPE 1 +#define EEMPE 2 +#define EERIE 3 +#define EEPM0 4 +#define EEPM1 5 + +/* EEPROM Data Register */ +#define EEDR _SFR_IO8(0x1D) + +/* EEPROM Address Register */ +#define EEAR _SFR_IO16(0x1E) +#define EEARL _SFR_IO8(0x1E) +#define EEARH _SFR_IO8(0x1F) + +#define DWDR _SFR_IO8(0x20) + +#define WDTCR _SFR_IO8(0x21) +#define WDP0 0 +#define WDP1 1 +#define WDP2 2 +#define WDE 3 +#define WDCE 4 +#define WDP3 5 +#define WDIE 6 +#define WDIF 7 + +#define PCMSK1 _SFR_IO8(0x22) +#define PCINT8 0 +#define PCINT9 1 +#define PCINT10 2 +#define PCINT11 3 +#define PCINT12 4 +#define PCINT13 5 +#define PCINT14 6 +#define PCINT15 7 + +#define PCMSK0 _SFR_IO8(0x23) +#define PCINT0 0 +#define PCINT1 1 +#define PCINT2 2 +#define PCINT3 3 +#define PCINT4 4 +#define PCINT5 5 +#define PCINT6 6 +#define PCINT7 7 + +#define DT1 _SFR_IO8(0x24) +#define DT1L0 0 +#define DT1L1 1 +#define DT1L2 2 +#define DT1L3 3 +#define DT1H0 4 +#define DT1H1 5 +#define DT1H2 6 +#define DT1H3 7 + +#define TC1H _SFR_IO8(0x25) +#define TC18 0 +#define TC19 1 + +#define TCCR1D _SFR_IO8(0x26) +#define WGM10 0 +#define WGM11 1 +#define FPF1 2 +#define FPAC1 3 +#define FPES1 4 +#define FPNC1 5 +#define FPEN1 6 +#define FPIE1 7 + +#define TCCR1C _SFR_IO8(0x27) +#define PWM1D 0 +#define FOC1D 1 +#define COM1D0 2 +#define COM1D1 3 +#define COM1B0S 4 +#define COM1B1S 5 +#define COM1A0S 6 +#define COM1A1S 7 + +#define CLKPR _SFR_IO8(0x28) +#define CLKPS0 0 +#define CLKPS1 1 +#define CLKPS2 2 +#define CLKPS3 3 +#define CLKPCE 7 + +#define PLLCSR _SFR_IO8(0x29) +#define PLOCK 0 +#define PLLE 1 +#define PCKE 2 +#define LSM 7 + +#define OCR1D _SFR_IO8(0x2A) + +#define OCR1C _SFR_IO8(0x2B) + +#define OCR1B _SFR_IO8(0x2C) + +#define OCR1A _SFR_IO8(0x2D) + +#define TCNT1 _SFR_IO8(0x2E) + +#define TCCR1B _SFR_IO8(0x2F) +#define CS10 0 +#define CS11 1 +#define CS12 2 +#define CS13 3 +#define DTPS10 4 +#define DTPS11 5 +#define PSR1 6 +#define PWM1X 7 + +#define TCCR1A _SFR_IO8(0x30) +#define PWM1B 0 +#define PWM1A 1 +#define FOC1B 2 +#define FOC1A 3 +#define COM1B0 4 +#define COM1B1 5 +#define COM1A0 6 +#define COM1A1 7 + +#define OSCCAL _SFR_IO8(0x31) + +#define TCNT0L _SFR_IO8(0x32) + +#define TCCR0B _SFR_IO8(0x33) +#define CS00 0 +#define CS01 1 +#define CS02 2 +#define PSR0 3 +#define TSM 4 + +#define MCUSR _SFR_IO8(0x34) +#define PORF 0 +#define EXTRF 1 +#define BORF 2 +#define WDRF 3 + +#define MCUCR _SFR_IO8(0x35) +#define ISC00 0 +#define ISC01 1 +#define SM0 3 +#define SM1 4 +#define SE 5 +#define PUD 6 + +#define PRR _SFR_IO8(0x36) +#define PRADC 0 +#define PRUSI 1 +#define PRTIM0 2 +#define PRTIM1 3 + +#define __AVR_HAVE_PRR ((1<] */ +/* 0x3F SREG [defined in ] */ + + +/* Interrupt vectors */ +/* Interrupt vector 0 is the reset vector. */ +/* External Interrupt 0 */ +#define INT0_vect_num 1 +#define INT0_vect _VECTOR(1) +#define SIG_INTERRUPT0 _VECTOR(1) + +/* Pin Change Interrupt */ +#define PCINT_vect_num 2 +#define PCINT_vect _VECTOR(2) +#define SIG_PIN_CHANGE _VECTOR(2) + +/* Timer/Counter1 Compare Match 1A */ +#define TIMER1_COMPA_vect_num 3 +#define TIMER1_COMPA_vect _VECTOR(3) +#define SIG_OUTPUT_COMPARE1A _VECTOR(3) + +/* Timer/Counter1 Compare Match 1B */ +#define TIMER1_COMPB_vect_num 4 +#define TIMER1_COMPB_vect _VECTOR(4) +#define SIG_OUTPUT_COMPARE1B _VECTOR(4) + +/* Timer/Counter1 Overflow */ +#define TIMER1_OVF_vect_num 5 +#define TIMER1_OVF_vect _VECTOR(5) +#define SIG_OVERFLOW1 _VECTOR(5) + +/* Timer/Counter0 Overflow */ +#define TIMER0_OVF_vect_num 6 +#define TIMER0_OVF_vect _VECTOR(6) +#define SIG_OVERFLOW0 _VECTOR(6) + +/* USI Start */ +#define USI_START_vect_num 7 +#define USI_START_vect _VECTOR(7) +#define SIG_USI_START _VECTOR(7) + +/* USI Overflow */ +#define USI_OVF_vect_num 8 +#define USI_OVF_vect _VECTOR(8) +#define SIG_USI_OVERFLOW _VECTOR(8) + +/* EEPROM Ready */ +#define EE_RDY_vect_num 9 +#define EE_RDY_vect _VECTOR(9) +#define SIG_EEPROM_READY _VECTOR(9) + +/* Analog Comparator */ +#define ANA_COMP_vect_num 10 +#define ANA_COMP_vect _VECTOR(10) +#define SIG_ANA_COMP _VECTOR(10) +#define SIG_COMPARATOR _VECTOR(10) + +/* ADC Conversion Complete */ +#define ADC_vect_num 11 +#define ADC_vect _VECTOR(11) +#define SIG_ADC _VECTOR(11) + +/* Watchdog Time-Out */ +#define WDT_vect_num 12 +#define WDT_vect _VECTOR(12) +#define SIG_WDT _VECTOR(12) + +/* External Interrupt 1 */ +#define INT1_vect_num 13 +#define INT1_vect _VECTOR(13) +#define SIG_INTERRUPT1 _VECTOR(13) + +/* Timer/Counter0 Compare Match A */ +#define TIMER0_COMPA_vect_num 14 +#define TIMER0_COMPA_vect _VECTOR(14) +#define SIG_OUTPUT_COMPARE0A _VECTOR(14) + +/* Timer/Counter0 Compare Match B */ +#define TIMER0_COMPB_vect_num 15 +#define TIMER0_COMPB_vect _VECTOR(15) +#define SIG_OUTPUT_COMPARE0B _VECTOR(15) + +/* ADC Conversion Complete */ +#define TIMER0_CAPT_vect_num 16 +#define TIMER0_CAPT_vect _VECTOR(16) +#define SIG_INPUT_CAPTURE0 _VECTOR(16) + +/* Timer/Counter1 Compare Match D */ +#define TIMER1_COMPD_vect_num 17 +#define TIMER1_COMPD_vect _VECTOR(17) +#define SIG_OUTPUT_COMPARE0D _VECTOR(17) + +/* Timer/Counter1 Fault Protection */ +#define FAULT_PROTECTION_vect_num 18 +#define FAULT_PROTECTION_vect _VECTOR(18) + +#define _VECTORS_SIZE 38 + +#endif /* _AVR_IOTNx61_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb1286.h b/hardware/tools/avr/avr/include/avr/iousb1286.h new file mode 100644 index 0000000000000000000000000000000000000000..b67e5b3d5a2023527a97669bc3dbc248d8cacd67 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb1286.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2006 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb1286.h - definitions for AT90USB1286 */ + +#ifndef _AVR_AT90USB1286_H_ +#define _AVR_AT90USB1286_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x20FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB1286_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb1287.h b/hardware/tools/avr/avr/include/avr/iousb1287.h new file mode 100644 index 0000000000000000000000000000000000000000..076d47866d0e3c1b75b3b27699ccef11ea02c236 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb1287.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2006 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb1287.h - definitions for AT90USB1287 */ + +#ifndef _AVR_AT90USB1287_H_ +#define _AVR_AT90USB1287_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x20FF +#define XRAMEND 0xFFFF +#define E2END 0xFFF +#define E2PAGESIZE 8 +#define FLASHEND 0x1FFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB1287_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb162.h b/hardware/tools/avr/avr/include/avr/iousb162.h new file mode 100644 index 0000000000000000000000000000000000000000..5c02eb298ea0996e2b6655232259ac1fd7375454 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb162.h @@ -0,0 +1,101 @@ +/* Copyright (c) 2007 Anatoly Sokolov + Copyright (c) 2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb162.h - definitions for AT90USB162 */ + +#ifndef _AVR_AT90USB162_H_ +#define _AVR_AT90USB162_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x100 +#define RAMEND 0x2FF +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x3FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_RSTDSBL (unsigned char)~_BV(6) +#define FUSE_DWEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB162_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb646.h b/hardware/tools/avr/avr/include/avr/iousb646.h new file mode 100644 index 0000000000000000000000000000000000000000..ce9fcb5bcc8c0aaad0ed68b496384a282af09600 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb646.h @@ -0,0 +1,102 @@ +/* Copyright (c) 2006 Anatoly Sokolov + Copyright (c) 2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb646.h - definitions for AT90USB646 */ + +#ifndef _AVR_AT90USB646_H_ +#define _AVR_AT90USB646_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF +#define XRAMEND 0xFFFF +#define E2END 0x7FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB646_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb647.h b/hardware/tools/avr/avr/include/avr/iousb647.h new file mode 100644 index 0000000000000000000000000000000000000000..638fd352979c8dda350cd8a768a758a44f476d9c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb647.h @@ -0,0 +1,102 @@ +/* Copyright (c) 2006 Anatoly Sokolov + Copyright (c) 2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb647.h - definitions for AT90USB647 */ + +#ifndef _AVR_AT90USB647_H_ +#define _AVR_AT90USB647_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 256 +#define RAMSTART 0x100 +#define RAMEND 0x10FF +#define XRAMEND 0xFFFF +#define E2END 0x7FF +#define E2PAGESIZE 8 +#define FLASHEND 0xFFFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_JTAGEN (unsigned char)~_BV(6) +#define FUSE_OCDEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + + +/* Signature */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x82 + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_ADC (0x01<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB647_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousb82.h b/hardware/tools/avr/avr/include/avr/iousb82.h new file mode 100644 index 0000000000000000000000000000000000000000..8f8e8eccfadb9d8ba7a0f869b315ebbe21d2e459 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousb82.h @@ -0,0 +1,95 @@ +/* Copyright (c) 2007 Anatoly Sokolov + Copyright (c) 2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ + +/* avr/iousb82.h - definitions for AT90USB82 */ + +#ifndef _AVR_AT90USB82_H_ +#define _AVR_AT90USB82_H_ 1 + +#include + +/* Constants */ +#define SPM_PAGESIZE 128 +#define RAMSTART 0x100 +#define RAMEND 0x2FF +#define XRAMEND RAMEND +#define E2END 0x1FF +#define E2PAGESIZE 4 +#define FLASHEND 0x1FFF + + +/* Fuses */ +#define FUSE_MEMORY_SIZE 3 + +/* Low Fuse Byte */ +#define FUSE_CKSEL0 (unsigned char)~_BV(0) +#define FUSE_CKSEL1 (unsigned char)~_BV(1) +#define FUSE_CKSEL2 (unsigned char)~_BV(2) +#define FUSE_CKSEL3 (unsigned char)~_BV(3) +#define FUSE_SUT0 (unsigned char)~_BV(4) +#define FUSE_SUT1 (unsigned char)~_BV(5) +#define FUSE_CKOUT (unsigned char)~_BV(6) +#define FUSE_CKDIV8 (unsigned char)~_BV(7) +#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) + +/* High Fuse Byte */ +#define FUSE_BOOTRST (unsigned char)~_BV(0) +#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +#define FUSE_EESAVE (unsigned char)~_BV(3) +#define FUSE_WDTON (unsigned char)~_BV(4) +#define FUSE_SPIEN (unsigned char)~_BV(5) +#define FUSE_RSTDSBL (unsigned char)~_BV(6) +#define FUSE_DWEN (unsigned char)~_BV(7) +#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) + +/* Extended Fuse Byte */ +#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +#define FUSE_HWBE (unsigned char)~_BV(3) +#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) + + +/* Lock Bits */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_BITS_0_EXIST +#define __BOOT_LOCK_BITS_1_EXIST + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +#endif /* _AVR_AT90USB82_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/iousbxx2.h b/hardware/tools/avr/avr/include/avr/iousbxx2.h new file mode 100644 index 0000000000000000000000000000000000000000..2f0e3918b0604e83e7234dfbf30d751eb02d71f3 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iousbxx2.h @@ -0,0 +1,807 @@ +/* Copyright (c) 2007 Anatoly Sokolov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */ + +/* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ + +#ifndef _AVR_IOUSBXX2_H_ +#define _AVR_IOUSBXX2_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iousbxx2.h" +#else +# error "Attempt to include more than one file." +#endif + +/* Registers and associated bit numbers */ + +/* Reserved [0x00..0x02] */ + +#define PINB _SFR_IO8(0X03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +/* Reserved [0xC..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 5 +#define OCF1C 3 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +/* Reserved [0x17..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF1 1 +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0x20) + +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRASY 1 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8(0x24) +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +#define TCCR0B _SFR_IO8(0x25) +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0X28) + +#define PLLCSR _SFR_IO8(0x29) +#define PLLP2 4 +#define PLLP1 3 +#define PLLP0 2 +#define PLLE 1 +#define PLOCK 0 + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +#define DWDR _SFR_IO8(0x31) +#define IDRD 7 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8(0x34) +#define USBRF 5 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8(0x35) +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define SIGRD 5 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x38..0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +#define WDTCKD _SFR_MEM8(0x62) +#define WDEWIF 3 +#define WDEWIE 2 +#define WCLKD1 1 +#define WCLKD0 0 + +#define REGCR _SFR_MEM8(0x63) +#define REGDIS 0 + +#define PRR0 _SFR_MEM8(0x64) +#define PRTIM0 5 +#define PRTIM1 3 +#define PRSPI 2 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iousbxx6_7.h" +#else +# error "Attempt to include more than one file." +#endif + +#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) +# define __AT90USBxx6__ 1 +#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) +# define __AT90USBxx7__ 1 +#endif + +/* Registers and associated bit numbers */ + +#define PINA _SFR_IO8(0X00) +#define PINA7 7 +#define PINA6 6 +#define PINA5 5 +#define PINA4 4 +#define PINA3 3 +#define PINA2 2 +#define PINA1 1 +#define PINA0 0 + +#define DDRA _SFR_IO8(0X01) +#define DDA7 7 +#define DDA6 6 +#define DDA5 5 +#define DDA4 4 +#define DDA3 3 +#define DDA2 2 +#define DDA1 1 +#define DDA0 0 + +#define PORTA _SFR_IO8(0X02) +#define PA7 7 +#define PA6 6 +#define PA5 5 +#define PA4 4 +#define PA3 3 +#define PA2 2 +#define PA1 1 +#define PA0 0 + +#define PINB _SFR_IO8(0X03) +#define PINB7 7 +#define PINB6 6 +#define PINB5 5 +#define PINB4 4 +#define PINB3 3 +#define PINB2 2 +#define PINB1 1 +#define PINB0 0 + +#define DDRB _SFR_IO8(0x04) +#define DDB7 7 +#define DDB6 6 +#define DDB5 5 +#define DDB4 4 +#define DDB3 3 +#define DDB2 2 +#define DDB1 1 +#define DDB0 0 + +#define PORTB _SFR_IO8(0x05) +#define PB7 7 +#define PB6 6 +#define PB5 5 +#define PB4 4 +#define PB3 3 +#define PB2 2 +#define PB1 1 +#define PB0 0 + +#define PINC _SFR_IO8(0x06) +#define PINC7 7 +#define PINC6 6 +#define PINC5 5 +#define PINC4 4 +#define PINC3 3 +#define PINC2 2 +#define PINC1 1 +#define PINC0 0 + +#define DDRC _SFR_IO8(0x07) +#define DDC7 7 +#define DDC6 6 +#define DDC5 5 +#define DDC4 4 +#define DDC3 3 +#define DDC2 2 +#define DDC1 1 +#define DDC0 0 + +#define PORTC _SFR_IO8(0x08) +#define PC7 7 +#define PC6 6 +#define PC5 5 +#define PC4 4 +#define PC3 3 +#define PC2 2 +#define PC1 1 +#define PC0 0 + +#define PIND _SFR_IO8(0x09) +#define PIND7 7 +#define PIND6 6 +#define PIND5 5 +#define PIND4 4 +#define PIND3 3 +#define PIND2 2 +#define PIND1 1 +#define PIND0 0 + +#define DDRD _SFR_IO8(0x0A) +#define DDD7 7 +#define DDD6 6 +#define DDD5 5 +#define DDD4 4 +#define DDD3 3 +#define DDD2 2 +#define DDD1 1 +#define DDD0 0 + +#define PORTD _SFR_IO8(0x0B) +#define PD7 7 +#define PD6 6 +#define PD5 5 +#define PD4 4 +#define PD3 3 +#define PD2 2 +#define PD1 1 +#define PD0 0 + +#define PINE _SFR_IO8(0x0C) +#define PINE7 7 +#define PINE6 6 +#define PINE5 5 +#define PINE4 4 +#define PINE3 3 +#define PINE2 2 +#define PINE1 1 +#define PINE0 0 + +#define DDRE _SFR_IO8(0x0D) +#define DDE7 7 +#define DDE6 6 +#define DDE5 5 +#define DDE4 4 +#define DDE3 3 +#define DDE2 2 +#define DDE1 1 +#define DDE0 0 + +#define PORTE _SFR_IO8(0x0E) +#define PE7 7 +#define PE6 6 +#define PE5 5 +#define PE4 4 +#define PE3 3 +#define PE2 2 +#define PE1 1 +#define PE0 0 + +#define PINF _SFR_IO8(0x0F) +#define PINF7 7 +#define PINF6 6 +#define PINF5 5 +#define PINF4 4 +#define PINF3 3 +#define PINF2 2 +#define PINF1 1 +#define PINF0 0 + +#define DDRF _SFR_IO8(0x10) +#define DDF7 7 +#define DDF6 6 +#define DDF5 5 +#define DDF4 4 +#define DDF3 3 +#define DDF2 2 +#define DDF1 1 +#define DDF0 0 + +#define PORTF _SFR_IO8(0x11) +#define PF7 7 +#define PF6 6 +#define PF5 5 +#define PF4 4 +#define PF3 3 +#define PF2 2 +#define PF1 1 +#define PF0 0 + +/* Reserved [0x12..0x14] */ + +#define TIFR0 _SFR_IO8(0x15) +#define OCF0B 2 +#define OCF0A 1 +#define TOV0 0 + +#define TIFR1 _SFR_IO8(0x16) +#define ICF1 5 +#define OCF1C 3 +#define OCF1B 2 +#define OCF1A 1 +#define TOV1 0 + +#define TIFR2 _SFR_IO8(0x17) +#define OCF2B 2 +#define OCF2A 1 +#define TOV2 0 + +#define TIFR3 _SFR_IO8(0x18) +#define ICF3 5 +#define OCF3C 3 +#define OCF3B 2 +#define OCF3A 1 +#define TOV3 0 + +/* Reserved [0x19..0x1A] */ + +#define PCIFR _SFR_IO8(0x1B) +#define PCIF0 0 + +#define EIFR _SFR_IO8(0x1C) +#define INTF7 7 +#define INTF6 6 +#define INTF5 5 +#define INTF4 4 +#define INTF3 3 +#define INTF2 2 +#define INTF1 1 +#define INTF0 0 + +#define EIMSK _SFR_IO8(0x1D) +#define INT7 7 +#define INT6 6 +#define INT5 5 +#define INT4 4 +#define INT3 3 +#define INT2 2 +#define INT1 1 +#define INT0 0 + +#define GPIOR0 _SFR_IO8(0x1E) + +#define EECR _SFR_IO8(0x1F) +#define EEPM1 5 +#define EEPM0 4 +#define EERIE 3 +#define EEMPE 2 +#define EEPE 1 +#define EERE 0 + +#define EEDR _SFR_IO8(0x20) + +#define EEAR _SFR_IO16(0x21) +#define EEARL _SFR_IO8(0x21) +#define EEARH _SFR_IO8(0x22) + +/* 6-char sequence denoting where to find the EEPROM registers in memory space. + Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM + subroutines. + First two letters: EECR address. + Second two letters: EEDR address. + Last two letters: EEAR address. */ +#define __EEPROM_REG_LOCATIONS__ 1F2021 + +#define GTCCR _SFR_IO8(0x23) +#define TSM 7 +#define PSRASY 1 +#define PSRSYNC 0 + +#define TCCR0A _SFR_IO8(0x24) +#define COM0A1 7 +#define COM0A0 6 +#define COM0B1 5 +#define COM0B0 4 +#define WGM01 1 +#define WGM00 0 + +#define TCCR0B _SFR_IO8(0x25) +#define FOC0A 7 +#define FOC0B 6 +#define WGM02 3 +#define CS02 2 +#define CS01 1 +#define CS00 0 + +#define TCNT0 _SFR_IO8(0X26) + +#define OCR0A _SFR_IO8(0x27) + +#define OCR0B _SFR_IO8(0X28) + +#define PLLCSR _SFR_IO8(0x29) +#define PLLP2 4 +#define PLLP1 3 +#define PLLP0 2 +#define PLLE 1 +#define PLOCK 0 + +#define GPIOR1 _SFR_IO8(0x2A) + +#define GPIOR2 _SFR_IO8(0x2B) + +#define SPCR _SFR_IO8(0x2C) +#define SPIE 7 +#define SPE 6 +#define DORD 5 +#define MSTR 4 +#define CPOL 3 +#define CPHA 2 +#define SPR1 1 +#define SPR0 0 + +#define SPSR _SFR_IO8(0x2D) +#define SPIF 7 +#define WCOL 6 +#define SPI2X 0 + +#define SPDR _SFR_IO8(0x2E) + +/* Reserved [0x2F] */ + +#define ACSR _SFR_IO8(0x30) +#define ACD 7 +#define ACBG 6 +#define ACO 5 +#define ACI 4 +#define ACIE 3 +#define ACIC 2 +#define ACIS1 1 +#define ACIS0 0 + +#define MONDR _SFR_IO8(0x31) +#define OCDR _SFR_IO8(0x31) +#define IDRD 7 +#define OCDR7 7 +#define OCDR6 6 +#define OCDR5 5 +#define OCDR4 4 +#define OCDR3 3 +#define OCDR2 2 +#define OCDR1 1 +#define OCDR0 0 + +/* Reserved [0x32] */ + +#define SMCR _SFR_IO8(0x33) +#define SM2 3 +#define SM1 2 +#define SM0 1 +#define SE 0 + +#define MCUSR _SFR_IO8(0x34) +#define JTRF 4 +#define WDRF 3 +#define BORF 2 +#define EXTRF 1 +#define PORF 0 + +#define MCUCR _SFR_IO8(0x35) +#define JTD 7 +#define PUD 4 +#define IVSEL 1 +#define IVCE 0 + +/* Reserved [0x36] */ + +#define SPMCSR _SFR_IO8(0x37) +#define SPMIE 7 +#define RWWSB 6 +#define SIGRD 5 +#define RWWSRE 4 +#define BLBSET 3 +#define PGWRT 2 +#define PGERS 1 +#define SPMEN 0 + +/* Reserved [0x38..0x3A] */ + +#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) +#define RAMPZ _SFR_IO8(0x3B) +#endif + +/* Reserved [0x3C] */ + +/* SP [0x3D..0x3E] */ +/* SREG [0x3F] */ + +#define WDTCSR _SFR_MEM8(0x60) +#define WDIF 7 +#define WDIE 6 +#define WDP3 5 +#define WDCE 4 +#define WDE 3 +#define WDP2 2 +#define WDP1 1 +#define WDP0 0 + +#define CLKPR _SFR_MEM8(0x61) +#define CLKPCE 7 +#define CLKPS3 3 +#define CLKPS2 2 +#define CLKPS1 1 +#define CLKPS0 0 + +/* Reserved [0x62..0x63] */ + +#define PRR0 _SFR_MEM8(0x64) +#define PRTWI 7 +#define PRTIM2 6 +#define PRTIM0 5 +#define PRTIM1 3 +#define PRSPI 2 +#define PRADC 0 + +#define __AVR_HAVE_PRR0 ((1<, never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128a1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega128A1_H_ +#define _AVR_ATxmega128A1_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ +#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ +#define PORTK (*(PORT_t *) 0x0720) /* Port K */ +#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACA - Digital to Analog Converter A */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_TIMCTRL _SFR_MEM8(0x0304) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_GAINCAL _SFR_MEM8(0x0308) +#define DACA_OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* EBI - External Bus Interface */ +#define EBI_CTRL _SFR_MEM8(0x0440) +#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +#define EBI_REFRESH _SFR_MEM16(0x0444) +#define EBI_INITDLY _SFR_MEM16(0x0446) +#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWID - Two-Wire Interface D */ +#define TWID_CTRL _SFR_MEM8(0x0490) +#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* TWIF - Two-Wire Interface F */ +#define TWIF_CTRL _SFR_MEM8(0x04B0) +#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTH - Port H */ +#define PORTH_DIR _SFR_MEM8(0x06E0) +#define PORTH_DIRSET _SFR_MEM8(0x06E1) +#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +#define PORTH_OUT _SFR_MEM8(0x06E4) +#define PORTH_OUTSET _SFR_MEM8(0x06E5) +#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +#define PORTH_IN _SFR_MEM8(0x06E8) +#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) + +/* PORTJ - Port J */ +#define PORTJ_DIR _SFR_MEM8(0x0700) +#define PORTJ_DIRSET _SFR_MEM8(0x0701) +#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +#define PORTJ_OUT _SFR_MEM8(0x0704) +#define PORTJ_OUTSET _SFR_MEM8(0x0705) +#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +#define PORTJ_IN _SFR_MEM8(0x0708) +#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) + +/* PORTK - Port K */ +#define PORTK_DIR _SFR_MEM8(0x0720) +#define PORTK_DIRSET _SFR_MEM8(0x0721) +#define PORTK_DIRCLR _SFR_MEM8(0x0722) +#define PORTK_DIRTGL _SFR_MEM8(0x0723) +#define PORTK_OUT _SFR_MEM8(0x0724) +#define PORTK_OUTSET _SFR_MEM8(0x0725) +#define PORTK_OUTCLR _SFR_MEM8(0x0726) +#define PORTK_OUTTGL _SFR_MEM8(0x0727) +#define PORTK_IN _SFR_MEM8(0x0728) +#define PORTK_INTCTRL _SFR_MEM8(0x0729) +#define PORTK_INT0MASK _SFR_MEM8(0x072A) +#define PORTK_INT1MASK _SFR_MEM8(0x072B) +#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) + +/* PORTQ - Port Q */ +#define PORTQ_DIR _SFR_MEM8(0x07C0) +#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +#define PORTQ_OUT _SFR_MEM8(0x07C4) +#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +#define PORTQ_IN _SFR_MEM8(0x07C8) +#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TCF1 - Timer/Counter F1 */ +#define TCF1_CTRLA _SFR_MEM8(0x0B40) +#define TCF1_CTRLB _SFR_MEM8(0x0B41) +#define TCF1_CTRLC _SFR_MEM8(0x0B42) +#define TCF1_CTRLD _SFR_MEM8(0x0B43) +#define TCF1_CTRLE _SFR_MEM8(0x0B44) +#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +#define TCF1_TEMP _SFR_MEM8(0x0B4F) +#define TCF1_CNT _SFR_MEM16(0x0B60) +#define TCF1_PER _SFR_MEM16(0x0B66) +#define TCF1_CCA _SFR_MEM16(0x0B68) +#define TCF1_CCB _SFR_MEM16(0x0B6A) +#define TCF1_PERBUF _SFR_MEM16(0x0B76) +#define TCF1_CCABUF _SFR_MEM16(0x0B78) +#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TWID interrupt vectors */ +#define TWID_TWIS_vect_num 75 +#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +#define TWID_TWIM_vect_num 76 +#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTQ interrupt vectors */ +#define PORTQ_INT0_vect_num 94 +#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +#define PORTQ_INT1_vect_num 95 +#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ + +/* PORTH interrupt vectors */ +#define PORTH_INT0_vect_num 96 +#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +#define PORTH_INT1_vect_num 97 +#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ + +/* PORTJ interrupt vectors */ +#define PORTJ_INT0_vect_num 98 +#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +#define PORTJ_INT1_vect_num 99 +#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ + +/* PORTK interrupt vectors */ +#define PORTK_INT0_vect_num 100 +#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +#define PORTK_INT1_vect_num 101 +#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TWIF interrupt vectors */ +#define TWIF_TWIS_vect_num 106 +#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +#define TWIF_TWIM_vect_num 107 +#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF1 interrupt vectors */ +#define TCF1_OVF_vect_num 114 +#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +#define TCF1_ERR_vect_num 115 +#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +#define TCF1_CCA_vect_num 116 +#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +#define TCF1_CCB_vect_num 117 +#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ + +/* SPIF interrupt vectors */ +#define SPIF_INT_vect_num 118 +#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USARTF1 interrupt vectors */ +#define USARTF1_RXC_vect_num 122 +#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +#define USARTF1_DRE_vect_num 123 +#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +#define USARTF1_TXC_vect_num 124 +#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (125 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16777216) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EXTERNAL_SRAM_START (0x4000) +#define EXTERNAL_SRAM_SIZE (16760832) +#define EXTERNAL_SRAM_PAGE_SIZE (0) +#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND EXTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x4C + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega128A1_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128a1u.h b/hardware/tools/avr/avr/include/avr/iox128a1u.h new file mode 100644 index 0000000000000000000000000000000000000000..72f0ce8f3ece6a8cda2bc0b58ad20d87188c6a55 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128a1u.h @@ -0,0 +1,8305 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128a1u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED +#define _AVR_ATXMEGA128A1U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASPACE_enum +{ + EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASPACE_t; + +/* SRAM Wait State Selection */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* SDRAM Load Mode to Active delay */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* SDRAM Row Cycle Delay */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* SDRAM Row to Precharge Delay */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* SDRAM Write Recovery Delay */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* SDRAM Exit Self Refresh to Active Delay */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* SDRAM Row to Column Delay */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ +#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ +#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ +#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* EBI - External Bus Interface */ +#define EBI_CTRL _SFR_MEM8(0x0440) +#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +#define EBI_REFRESH _SFR_MEM16(0x0444) +#define EBI_INITDLY _SFR_MEM16(0x0446) +#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWID_CTRL _SFR_MEM8(0x0490) +#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* TWI - Two-Wire Interface */ +#define TWIF_CTRL _SFR_MEM8(0x04B0) +#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTH_DIR _SFR_MEM8(0x06E0) +#define PORTH_DIRSET _SFR_MEM8(0x06E1) +#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +#define PORTH_OUT _SFR_MEM8(0x06E4) +#define PORTH_OUTSET _SFR_MEM8(0x06E5) +#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +#define PORTH_IN _SFR_MEM8(0x06E8) +#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_REMAP _SFR_MEM8(0x06EE) +#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) + +/* PORT - I/O Ports */ +#define PORTJ_DIR _SFR_MEM8(0x0700) +#define PORTJ_DIRSET _SFR_MEM8(0x0701) +#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +#define PORTJ_OUT _SFR_MEM8(0x0704) +#define PORTJ_OUTSET _SFR_MEM8(0x0705) +#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +#define PORTJ_IN _SFR_MEM8(0x0708) +#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_REMAP _SFR_MEM8(0x070E) +#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) + +/* PORT - I/O Ports */ +#define PORTK_DIR _SFR_MEM8(0x0720) +#define PORTK_DIRSET _SFR_MEM8(0x0721) +#define PORTK_DIRCLR _SFR_MEM8(0x0722) +#define PORTK_DIRTGL _SFR_MEM8(0x0723) +#define PORTK_OUT _SFR_MEM8(0x0724) +#define PORTK_OUTSET _SFR_MEM8(0x0725) +#define PORTK_OUTCLR _SFR_MEM8(0x0726) +#define PORTK_OUTTGL _SFR_MEM8(0x0727) +#define PORTK_IN _SFR_MEM8(0x0728) +#define PORTK_INTCTRL _SFR_MEM8(0x0729) +#define PORTK_INT0MASK _SFR_MEM8(0x072A) +#define PORTK_INT1MASK _SFR_MEM8(0x072B) +#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_REMAP _SFR_MEM8(0x072E) +#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) + +/* PORT - I/O Ports */ +#define PORTQ_DIR _SFR_MEM8(0x07C0) +#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +#define PORTQ_OUT _SFR_MEM8(0x07C4) +#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +#define PORTQ_IN _SFR_MEM8(0x07C8) +#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_REMAP _SFR_MEM8(0x07CE) +#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCF1_CTRLA _SFR_MEM8(0x0B40) +#define TCF1_CTRLB _SFR_MEM8(0x0B41) +#define TCF1_CTRLC _SFR_MEM8(0x0B42) +#define TCF1_CTRLD _SFR_MEM8(0x0B43) +#define TCF1_CTRLE _SFR_MEM8(0x0B44) +#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +#define TCF1_TEMP _SFR_MEM8(0x0B4F) +#define TCF1_CNT _SFR_MEM16(0x0B60) +#define TCF1_PER _SFR_MEM16(0x0B66) +#define TCF1_CCA _SFR_MEM16(0x0B68) +#define TCF1_CCB _SFR_MEM16(0x0B6A) +#define TCF1_PERBUF _SFR_MEM16(0x0B76) +#define TCF1_CCABUF _SFR_MEM16(0x0B78) +#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ +#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ +#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ +#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ +#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ +#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ +#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ +#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ +#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ +#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ +#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ +#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TWID interrupt vectors */ +#define TWID_TWIS_vect_num 75 +#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +#define TWID_TWIM_vect_num 76 +#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTQ interrupt vectors */ +#define PORTQ_INT0_vect_num 94 +#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +#define PORTQ_INT1_vect_num 95 +#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ + +/* PORTH interrupt vectors */ +#define PORTH_INT0_vect_num 96 +#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +#define PORTH_INT1_vect_num 97 +#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ + +/* PORTJ interrupt vectors */ +#define PORTJ_INT0_vect_num 98 +#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +#define PORTJ_INT1_vect_num 99 +#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ + +/* PORTK interrupt vectors */ +#define PORTK_INT0_vect_num 100 +#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +#define PORTK_INT1_vect_num 101 +#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TWIF interrupt vectors */ +#define TWIF_TWIS_vect_num 106 +#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +#define TWIF_TWIM_vect_num 107 +#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* TCF1 interrupt vectors */ +#define TCF1_OVF_vect_num 114 +#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +#define TCF1_ERR_vect_num 115 +#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +#define TCF1_CCA_vect_num 116 +#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +#define TCF1_CCB_vect_num 117 +#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ + +/* SPIF interrupt vectors */ +#define SPIF_INT_vect_num 118 +#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USARTF1 interrupt vectors */ +#define USARTF1_RXC_vect_num 122 +#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +#define USARTF1_DRE_vect_num 123 +#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +#define USARTF1_TXC_vect_num 124 +#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16777216) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x4C + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128a3.h b/hardware/tools/avr/avr/include/avr/iox128a3.h new file mode 100644 index 0000000000000000000000000000000000000000..14723b31391f7142857dc0a7e1dd8ec6a760d2a7 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128a3.h @@ -0,0 +1,6987 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox128a3.h - definitions for ATxmega128A3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128a3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega128A3_H_ +#define _AVR_ATxmega128A3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (122 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega128A3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128a3u.h b/hardware/tools/avr/avr/include/avr/iox128a3u.h new file mode 100644 index 0000000000000000000000000000000000000000..489caa06190571940f7674af76a2975f16fc506e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128a3u.h @@ -0,0 +1,7697 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128a3u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED +#define _AVR_ATXMEGA128A3U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128a4u.h b/hardware/tools/avr/avr/include/avr/iox128a4u.h new file mode 100644 index 0000000000000000000000000000000000000000..6365392b1fa3e75f946baf8a8fbd5cda95c4384f --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128a4u.h @@ -0,0 +1,7309 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128a4u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED +#define _AVR_ATXMEGA128A4U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x46 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128b1.h b/hardware/tools/avr/avr/include/avr/iox128b1.h new file mode 100644 index 0000000000000000000000000000000000000000..f3f41f4d5deba592ed22aa650d3160bed6120527 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128b1.h @@ -0,0 +1,6872 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128b1.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128B1_H_INCLUDED +#define _AVR_ATXMEGA128B1_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +PR - Power Reduction +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t reserved_0x04; + register8_t PRPE; /* Power Reduction Port E */ +} PR_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ + PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ + PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +LCD - LCD Controller +-------------------------------------------------------------------------- +*/ + +/* LCD Controller */ +typedef struct LCD_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t INTCTRL; /* Interrupt Enable Register */ + register8_t INTFLAG; /* Interrupt Flag Register */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t CTRLH; /* Control Register H */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t DATA0; /* LCD Data Register 0 */ + register8_t DATA1; /* LCD Data Register 1 */ + register8_t DATA2; /* LCD Data Register 2 */ + register8_t DATA3; /* LCD Data Register 3 */ + register8_t DATA4; /* LCD Data Register 4 */ + register8_t DATA5; /* LCD Data Register 5 */ + register8_t DATA6; /* LCD Data Register 6 */ + register8_t DATA7; /* LCD Data Register 7 */ + register8_t DATA8; /* LCD Data Register 8 */ + register8_t DATA9; /* LCD Data Register 9 */ + register8_t DATA10; /* LCD Data Register 10 */ + register8_t DATA11; /* LCD Data Register 11 */ + register8_t DATA12; /* LCD Data Register 12 */ + register8_t DATA13; /* LCD Data Register 13 */ + register8_t DATA14; /* LCD Data Register 14 */ + register8_t DATA15; /* LCD Data Register 15 */ + register8_t DATA16; /* LCD Data Register 16 */ + register8_t DATA17; /* LCD Data Register 17 */ + register8_t DATA18; /* LCD Data Register 18 */ + register8_t DATA19; /* LCD Data Register 19 */ +} LCD_t; + +/* LCD Blink Rate */ +typedef enum LCD_BLINKRATE_enum +{ + LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ + LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ + LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ + LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ +} LCD_BLINKRATE_t; + +/* LCD Clock Divide */ +typedef enum LCD_CLKDIV_enum +{ + LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ + LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ + LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ + LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ + LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ + LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ + LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ + LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ +} LCD_CLKDIV_t; + +/* Duty Select */ +typedef enum LCD_DUTY_enum +{ + LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ + LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ + LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ + LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ +} LCD_DUTY_t; + +/* LCD Prescaler Select */ +typedef enum LCD_PRESC_enum +{ + LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ + LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ +} LCD_PRESC_t; + +/* Type of Digit */ +typedef enum LCD_TDG_enum +{ + LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ + LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ + LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ + LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ +} LCD_TDG_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ +#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPE _SFR_MEM8(0x0075) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) +#define ACB_CURRCTRL _SFR_MEM8(0x0398) +#define ACB_CURRCALIB _SFR_MEM8(0x0399) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x06C0) +#define PORTG_DIRSET _SFR_MEM8(0x06C1) +#define PORTG_DIRCLR _SFR_MEM8(0x06C2) +#define PORTG_DIRTGL _SFR_MEM8(0x06C3) +#define PORTG_OUT _SFR_MEM8(0x06C4) +#define PORTG_OUTSET _SFR_MEM8(0x06C5) +#define PORTG_OUTCLR _SFR_MEM8(0x06C6) +#define PORTG_OUTTGL _SFR_MEM8(0x06C7) +#define PORTG_IN _SFR_MEM8(0x06C8) +#define PORTG_INTCTRL _SFR_MEM8(0x06C9) +#define PORTG_INT0MASK _SFR_MEM8(0x06CA) +#define PORTG_INT1MASK _SFR_MEM8(0x06CB) +#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) +#define PORTG_REMAP _SFR_MEM8(0x06CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) + +/* PORT - I/O Ports */ +#define PORTM_DIR _SFR_MEM8(0x0760) +#define PORTM_DIRSET _SFR_MEM8(0x0761) +#define PORTM_DIRCLR _SFR_MEM8(0x0762) +#define PORTM_DIRTGL _SFR_MEM8(0x0763) +#define PORTM_OUT _SFR_MEM8(0x0764) +#define PORTM_OUTSET _SFR_MEM8(0x0765) +#define PORTM_OUTCLR _SFR_MEM8(0x0766) +#define PORTM_OUTTGL _SFR_MEM8(0x0767) +#define PORTM_IN _SFR_MEM8(0x0768) +#define PORTM_INTCTRL _SFR_MEM8(0x0769) +#define PORTM_INT0MASK _SFR_MEM8(0x076A) +#define PORTM_INT1MASK _SFR_MEM8(0x076B) +#define PORTM_INTFLAGS _SFR_MEM8(0x076C) +#define PORTM_REMAP _SFR_MEM8(0x076E) +#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) +#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) +#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) +#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) +#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) +#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) +#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) +#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* LCD - LCD Controller */ +#define LCD_CTRLA _SFR_MEM8(0x0D00) +#define LCD_CTRLB _SFR_MEM8(0x0D01) +#define LCD_CTRLC _SFR_MEM8(0x0D02) +#define LCD_INTCTRL _SFR_MEM8(0x0D03) +#define LCD_INTFLAG _SFR_MEM8(0x0D04) +#define LCD_CTRLD _SFR_MEM8(0x0D05) +#define LCD_CTRLE _SFR_MEM8(0x0D06) +#define LCD_CTRLF _SFR_MEM8(0x0D07) +#define LCD_CTRLG _SFR_MEM8(0x0D08) +#define LCD_CTRLH _SFR_MEM8(0x0D09) +#define LCD_DATA0 _SFR_MEM8(0x0D10) +#define LCD_DATA1 _SFR_MEM8(0x0D11) +#define LCD_DATA2 _SFR_MEM8(0x0D12) +#define LCD_DATA3 _SFR_MEM8(0x0D13) +#define LCD_DATA4 _SFR_MEM8(0x0D14) +#define LCD_DATA5 _SFR_MEM8(0x0D15) +#define LCD_DATA6 _SFR_MEM8(0x0D16) +#define LCD_DATA7 _SFR_MEM8(0x0D17) +#define LCD_DATA8 _SFR_MEM8(0x0D18) +#define LCD_DATA9 _SFR_MEM8(0x0D19) +#define LCD_DATA10 _SFR_MEM8(0x0D1A) +#define LCD_DATA11 _SFR_MEM8(0x0D1B) +#define LCD_DATA12 _SFR_MEM8(0x0D1C) +#define LCD_DATA13 _SFR_MEM8(0x0D1D) +#define LCD_DATA14 _SFR_MEM8(0x0D1E) +#define LCD_DATA15 _SFR_MEM8(0x0D1F) +#define LCD_DATA16 _SFR_MEM8(0x0D20) +#define LCD_DATA17 _SFR_MEM8(0x0D21) +#define LCD_DATA18 _SFR_MEM8(0x0D22) +#define LCD_DATA19 _SFR_MEM8(0x0D23) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* PR - Power Reduction */ +/* PR.PRGEN bit masks and bit positions */ +#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ +#define PR_LCD_bp 7 /* LCD Module bit position. */ + +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ +#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ +#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ + +#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ +#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* LCD - LCD Controller */ +/* LCD.CTRLA bit masks and bit positions */ +#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ +#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ + +#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ +#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ + +#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ +#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ + +#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ +#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ + +#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ +#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ + +#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ +#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ + +#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ +#define LCD_SEGON_bp 1 /* Segments On bit position. */ + +#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ +#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ + +/* LCD.CTRLB bit masks and bit positions */ +#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ +#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ + +#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ +#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ +#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ +#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ +#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ +#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ +#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ +#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ + +#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ +#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ + +#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ +#define LCD_DUTY_gp 0 /* Duty Select group position. */ +#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ +#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ +#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ +#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ + +/* LCD.CTRLC bit masks and bit positions */ +#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ +#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ +#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ +#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ +#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ +#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ +#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ +#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ +#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ +#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ +#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ +#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ +#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ +#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ + +/* LCD.INTCTRL bit masks and bit positions */ +#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ +#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ +#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ +#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ +#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ +#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ +#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ +#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ +#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ +#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ +#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ +#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ + +#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ +#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* LCD.INTFLAG bit masks and bit positions */ +#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ +#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ + +/* LCD.CTRLD bit masks and bit positions */ +#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ +#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ + +#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ +#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ +#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ +#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ +#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ +#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ + +/* LCD.CTRLE bit masks and bit positions */ +#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ +#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ +#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ +#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ +#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ +#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ +#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ +#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ +#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ +#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ + +#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ +#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ +#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ +#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ +#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ +#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ +#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ +#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ +#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ +#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ + +/* LCD.CTRLF bit masks and bit positions */ +#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ +#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ +#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ +#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ +#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ +#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ +#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ +#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ +#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ +#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ +#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ +#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ +#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ +#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ + +/* LCD.CTRLG bit masks and bit positions */ +#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ +#define LCD_TDG_gp 6 /* Type of Digit group position. */ +#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ +#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ +#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ +#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ + +#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ +#define LCD_STSEG_gp 0 /* Start Segment group position. */ +#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ +#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ +#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ +#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ +#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ +#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ +#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ +#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ +#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ +#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ +#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ +#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ + +/* LCD.CTRLH bit masks and bit positions */ +#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ +#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ + +#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ +#define LCD_DCODE_gp 0 /* Display Code group position. */ +#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ +#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ +#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ +#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ +#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ +#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ +#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ +#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ +#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ +#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ +#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ +#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ +#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ +#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 31 +#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 32 +#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ + +/* LCD interrupt vectors */ +#define LCD_INT_vect_num 35 +#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 36 +#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 37 +#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ +#define NVM_SPM_vect_num 38 +#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 39 +#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 40 +#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 41 +#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 42 +#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 43 +#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 44 +#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 48 +#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 49 +#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ + +/* PORTG interrupt vectors */ +#define PORTG_INT0_vect_num 50 +#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ +#define PORTG_INT1_vect_num 51 +#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ + +/* PORTM interrupt vectors */ +#define PORTM_INT0_vect_num 52 +#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ +#define PORTM_INT1_vect_num 53 +#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 54 +#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 55 +#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 58 +#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 58 +#define TCE2_LUNF_vect _VECTOR(58) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 59 +#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 59 +#define TCE2_HUNF_vect _VECTOR(59) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 60 +#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 60 +#define TCE2_LCMPA_vect _VECTOR(60) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 61 +#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 61 +#define TCE2_LCMPB_vect _VECTOR(61) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 62 +#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 62 +#define TCE2_LCMPC_vect _VECTOR(62) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 63 +#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 63 +#define TCE2_LCMPD_vect _VECTOR(63) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 69 +#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 70 +#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 71 +#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 75 +#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 76 +#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 77 +#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 78 +#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 79 +#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 80 +#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (81 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x4D + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_LCD +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128b3.h b/hardware/tools/avr/avr/include/avr/iox128b3.h new file mode 100644 index 0000000000000000000000000000000000000000..45f1d14f5d8c3e003d06c2973d877b3df247d0ad --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128b3.h @@ -0,0 +1,6288 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128b3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128B3_H_INCLUDED +#define _AVR_ATXMEGA128B3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +PR - Power Reduction +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t reserved_0x04; + register8_t PRPE; /* Power Reduction Port E */ +} PR_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ + PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ + PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +LCD - LCD Controller +-------------------------------------------------------------------------- +*/ + +/* LCD Controller */ +typedef struct LCD_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t INTCTRL; /* Interrupt Enable Register */ + register8_t INTFLAG; /* Interrupt Flag Register */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t CTRLH; /* Control Register H */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t DATA0; /* LCD Data Register 0 */ + register8_t DATA1; /* LCD Data Register 1 */ + register8_t DATA2; /* LCD Data Register 2 */ + register8_t DATA3; /* LCD Data Register 3 */ + register8_t DATA4; /* LCD Data Register 4 */ + register8_t DATA5; /* LCD Data Register 5 */ + register8_t DATA6; /* LCD Data Register 6 */ + register8_t DATA7; /* LCD Data Register 7 */ + register8_t DATA8; /* LCD Data Register 8 */ + register8_t DATA9; /* LCD Data Register 9 */ + register8_t DATA10; /* LCD Data Register 10 */ + register8_t DATA11; /* LCD Data Register 11 */ + register8_t DATA12; /* LCD Data Register 12 */ + register8_t DATA13; /* LCD Data Register 13 */ + register8_t DATA14; /* LCD Data Register 14 */ + register8_t DATA15; /* LCD Data Register 15 */ + register8_t DATA16; /* LCD Data Register 16 */ + register8_t DATA17; /* LCD Data Register 17 */ + register8_t DATA18; /* LCD Data Register 18 */ + register8_t DATA19; /* LCD Data Register 19 */ +} LCD_t; + +/* LCD Blink Rate */ +typedef enum LCD_BLINKRATE_enum +{ + LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ + LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ + LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ + LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ +} LCD_BLINKRATE_t; + +/* LCD Clock Divide */ +typedef enum LCD_CLKDIV_enum +{ + LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ + LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ + LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ + LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ + LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ + LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ + LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ + LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ +} LCD_CLKDIV_t; + +/* Duty Select */ +typedef enum LCD_DUTY_enum +{ + LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ + LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ + LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ + LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ +} LCD_DUTY_t; + +/* LCD Prescaler Select */ +typedef enum LCD_PRESC_enum +{ + LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ + LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ +} LCD_PRESC_t; + +/* Type of Digit */ +typedef enum LCD_TDG_enum +{ + LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ + LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ + LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ + LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ +} LCD_TDG_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ +#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPE _SFR_MEM8(0x0075) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) +#define ACB_CURRCTRL _SFR_MEM8(0x0398) +#define ACB_CURRCALIB _SFR_MEM8(0x0399) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x06C0) +#define PORTG_DIRSET _SFR_MEM8(0x06C1) +#define PORTG_DIRCLR _SFR_MEM8(0x06C2) +#define PORTG_DIRTGL _SFR_MEM8(0x06C3) +#define PORTG_OUT _SFR_MEM8(0x06C4) +#define PORTG_OUTSET _SFR_MEM8(0x06C5) +#define PORTG_OUTCLR _SFR_MEM8(0x06C6) +#define PORTG_OUTTGL _SFR_MEM8(0x06C7) +#define PORTG_IN _SFR_MEM8(0x06C8) +#define PORTG_INTCTRL _SFR_MEM8(0x06C9) +#define PORTG_INT0MASK _SFR_MEM8(0x06CA) +#define PORTG_INT1MASK _SFR_MEM8(0x06CB) +#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) +#define PORTG_REMAP _SFR_MEM8(0x06CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) + +/* PORT - I/O Ports */ +#define PORTM_DIR _SFR_MEM8(0x0760) +#define PORTM_DIRSET _SFR_MEM8(0x0761) +#define PORTM_DIRCLR _SFR_MEM8(0x0762) +#define PORTM_DIRTGL _SFR_MEM8(0x0763) +#define PORTM_OUT _SFR_MEM8(0x0764) +#define PORTM_OUTSET _SFR_MEM8(0x0765) +#define PORTM_OUTCLR _SFR_MEM8(0x0766) +#define PORTM_OUTTGL _SFR_MEM8(0x0767) +#define PORTM_IN _SFR_MEM8(0x0768) +#define PORTM_INTCTRL _SFR_MEM8(0x0769) +#define PORTM_INT0MASK _SFR_MEM8(0x076A) +#define PORTM_INT1MASK _SFR_MEM8(0x076B) +#define PORTM_INTFLAGS _SFR_MEM8(0x076C) +#define PORTM_REMAP _SFR_MEM8(0x076E) +#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) +#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) +#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) +#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) +#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) +#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) +#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) +#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* LCD - LCD Controller */ +#define LCD_CTRLA _SFR_MEM8(0x0D00) +#define LCD_CTRLB _SFR_MEM8(0x0D01) +#define LCD_CTRLC _SFR_MEM8(0x0D02) +#define LCD_INTCTRL _SFR_MEM8(0x0D03) +#define LCD_INTFLAG _SFR_MEM8(0x0D04) +#define LCD_CTRLD _SFR_MEM8(0x0D05) +#define LCD_CTRLE _SFR_MEM8(0x0D06) +#define LCD_CTRLF _SFR_MEM8(0x0D07) +#define LCD_CTRLG _SFR_MEM8(0x0D08) +#define LCD_CTRLH _SFR_MEM8(0x0D09) +#define LCD_DATA0 _SFR_MEM8(0x0D10) +#define LCD_DATA1 _SFR_MEM8(0x0D11) +#define LCD_DATA2 _SFR_MEM8(0x0D12) +#define LCD_DATA3 _SFR_MEM8(0x0D13) +#define LCD_DATA4 _SFR_MEM8(0x0D14) +#define LCD_DATA5 _SFR_MEM8(0x0D15) +#define LCD_DATA6 _SFR_MEM8(0x0D16) +#define LCD_DATA7 _SFR_MEM8(0x0D17) +#define LCD_DATA8 _SFR_MEM8(0x0D18) +#define LCD_DATA9 _SFR_MEM8(0x0D19) +#define LCD_DATA10 _SFR_MEM8(0x0D1A) +#define LCD_DATA11 _SFR_MEM8(0x0D1B) +#define LCD_DATA12 _SFR_MEM8(0x0D1C) +#define LCD_DATA13 _SFR_MEM8(0x0D1D) +#define LCD_DATA14 _SFR_MEM8(0x0D1E) +#define LCD_DATA15 _SFR_MEM8(0x0D1F) +#define LCD_DATA16 _SFR_MEM8(0x0D20) +#define LCD_DATA17 _SFR_MEM8(0x0D21) +#define LCD_DATA18 _SFR_MEM8(0x0D22) +#define LCD_DATA19 _SFR_MEM8(0x0D23) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* PR - Power Reduction */ +/* PR.PRGEN bit masks and bit positions */ +#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ +#define PR_LCD_bp 7 /* LCD Module bit position. */ + +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ +#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ +#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ + +#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ +#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* LCD - LCD Controller */ +/* LCD.CTRLA bit masks and bit positions */ +#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ +#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ + +#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ +#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ + +#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ +#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ + +#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ +#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ + +#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ +#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ + +#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ +#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ + +#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ +#define LCD_SEGON_bp 1 /* Segments On bit position. */ + +#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ +#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ + +/* LCD.CTRLB bit masks and bit positions */ +#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ +#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ + +#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ +#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ +#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ +#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ +#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ +#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ +#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ +#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ + +#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ +#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ + +#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ +#define LCD_DUTY_gp 0 /* Duty Select group position. */ +#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ +#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ +#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ +#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ + +/* LCD.CTRLC bit masks and bit positions */ +#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ +#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ +#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ +#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ +#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ +#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ +#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ +#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ +#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ +#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ +#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ +#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ +#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ +#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ + +/* LCD.INTCTRL bit masks and bit positions */ +#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ +#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ +#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ +#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ +#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ +#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ +#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ +#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ +#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ +#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ +#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ +#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ + +#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ +#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* LCD.INTFLAG bit masks and bit positions */ +#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ +#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ + +/* LCD.CTRLD bit masks and bit positions */ +#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ +#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ + +#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ +#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ +#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ +#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ +#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ +#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ + +/* LCD.CTRLE bit masks and bit positions */ +#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ +#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ +#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ +#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ +#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ +#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ +#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ +#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ +#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ +#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ + +#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ +#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ +#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ +#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ +#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ +#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ +#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ +#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ +#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ +#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ + +/* LCD.CTRLF bit masks and bit positions */ +#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ +#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ +#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ +#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ +#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ +#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ +#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ +#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ +#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ +#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ +#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ +#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ +#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ +#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ + +/* LCD.CTRLG bit masks and bit positions */ +#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ +#define LCD_TDG_gp 6 /* Type of Digit group position. */ +#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ +#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ +#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ +#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ + +#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ +#define LCD_STSEG_gp 0 /* Start Segment group position. */ +#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ +#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ +#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ +#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ +#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ +#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ +#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ +#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ +#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ +#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ +#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ +#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ + +/* LCD.CTRLH bit masks and bit positions */ +#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ +#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ + +#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ +#define LCD_DCODE_gp 0 /* Display Code group position. */ +#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ +#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ +#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ +#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ +#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ +#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ +#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ +#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ +#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ +#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ +#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ +#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ +#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ +#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 31 +#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 32 +#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ + +/* LCD interrupt vectors */ +#define LCD_INT_vect_num 35 +#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 36 +#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 37 +#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ +#define NVM_SPM_vect_num 38 +#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 39 +#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 40 +#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 41 +#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 42 +#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 43 +#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 44 +#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 48 +#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 49 +#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ + +/* PORTG interrupt vectors */ +#define PORTG_INT0_vect_num 50 +#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ +#define PORTG_INT1_vect_num 51 +#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ + +/* PORTM interrupt vectors */ +#define PORTM_INT0_vect_num 52 +#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ +#define PORTM_INT1_vect_num 53 +#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (54 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x4B + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_LCD +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128c3.h b/hardware/tools/avr/avr/include/avr/iox128c3.h new file mode 100644 index 0000000000000000000000000000000000000000..6bc51ef7090d8eaf257cd31bc5027260e660aa1a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128c3.h @@ -0,0 +1,6264 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128C3_H_INCLUDED +#define _AVR_ATXMEGA128C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x52 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128d3.h b/hardware/tools/avr/avr/include/avr/iox128d3.h new file mode 100644 index 0000000000000000000000000000000000000000..15d4f33d96383c2911bfa1dc92c00825ddf2e545 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128d3.h @@ -0,0 +1,5749 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ + +/* avr/iox128d3.h - definitions for ATxmega128D3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128d3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega128D3_H_ +#define _AVR_ATxmega128D3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ + register8_t CTRL; /* Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_CTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x48 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega128D3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox128d4.h b/hardware/tools/avr/avr/include/avr/iox128d4.h new file mode 100644 index 0000000000000000000000000000000000000000..0d818f716ab08039d45608d56634db11c2882a68 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox128d4.h @@ -0,0 +1,5562 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox128d4.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA128D4_H_INCLUDED +#define _AVR_ATXMEGA128D4_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - Port Configuration */ +/* VPORT.INTFLAGS bit masks and bit positions */ +/* VPORT_INT1IF Predefined. */ +/* VPORT_INT1IF Predefined. */ + +/* VPORT_INT0IF Predefined. */ +/* VPORT_INT0IF Predefined. */ + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ +#define PORT_SPI_bp 5 /* SPI Remap bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ +#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (91 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (139264) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (131072) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x20000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (8192) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x47 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox16a4.h b/hardware/tools/avr/avr/include/avr/iox16a4.h new file mode 100644 index 0000000000000000000000000000000000000000..dbef5eb562c9fd66766adf58bd3c5ba476b52a84 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox16a4.h @@ -0,0 +1,6748 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox16a4.h - definitions for ATxmega16A4 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16a4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega16A4_H_ +#define _AVR_ATxmega16A4_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ + BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ + BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ + BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (94 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega16A4_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox16a4u.h b/hardware/tools/avr/avr/include/avr/iox16a4u.h new file mode 100644 index 0000000000000000000000000000000000000000..bf79d55a9fa739e02ca86beaf562efc83fa15536 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox16a4u.h @@ -0,0 +1,7309 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16a4u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA16A4U_H_INCLUDED +#define _AVR_ATXMEGA16A4U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox16c4.h b/hardware/tools/avr/avr/include/avr/iox16c4.h new file mode 100644 index 0000000000000000000000000000000000000000..32043b9fded0910d7e23692b24cf13e872268cf1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox16c4.h @@ -0,0 +1,6078 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16c4.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA16C4_H_INCLUDED +#define _AVR_ATXMEGA16C4_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x43 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox16d4.h b/hardware/tools/avr/avr/include/avr/iox16d4.h new file mode 100644 index 0000000000000000000000000000000000000000..5aa0ef90c5c7205b6c6d5c1857d9a857ec18ffdf --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox16d4.h @@ -0,0 +1,5717 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox16d4.h - definitions for ATxmega16D4 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16d4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega16D4_H_ +#define _AVR_ATxmega16D4_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0, INPUTMODE[1:0] = 10 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1, INPUTMODE[1:0] = 10 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2, INPUTMODE[1:0] = 10 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3, INPUTMODE[1:0] = 10 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4, INPUTMODE[1:0] = 11 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5, INPUTMODE[1:0] = 11 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6, INPUTMODE[1:0] = 11 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7, INPUTMODE[1:0] = 11 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ + +#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ +#define ADC_CURRENT1_bp 6 /* Current bit position. */ +#define ADC_CURRENT0_bp 5 /* Current bit position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (91 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega16D4_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox16e5.h b/hardware/tools/avr/avr/include/avr/iox16e5.h new file mode 100644 index 0000000000000000000000000000000000000000..7649c5fbe694e2033137a70c0e6a8342afed08c8 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox16e5.h @@ -0,0 +1,7699 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox16e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA16E5_H_INCLUDED +#define _AVR_ATXMEGA16E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (20480) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (16384) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x4000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (10240) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (512) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (2048) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (512) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x94 +#define SIGNATURE_2 0x45 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox192a3.h b/hardware/tools/avr/avr/include/avr/iox192a3.h new file mode 100644 index 0000000000000000000000000000000000000000..e6917cb16206af50ba5efc1b60ccb3b8822f8cac --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox192a3.h @@ -0,0 +1,6987 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ + +/* avr/iox192a3.h - definitions for ATxmega192A3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox192a3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega192A3_H_ +#define _AVR_ATxmega192A3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (122 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (204800) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (196608) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x2E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x30000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16777216) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x44 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega192A3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox192a3u.h b/hardware/tools/avr/avr/include/avr/iox192a3u.h new file mode 100644 index 0000000000000000000000000000000000000000..bd53330bdba518ddf5bb20fdef953e96b6b20761 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox192a3u.h @@ -0,0 +1,7697 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox192a3u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA192A3U_H_INCLUDED +#define _AVR_ATXMEGA192A3U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (204800) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (196608) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x2E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x30000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x44 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox192c3.h b/hardware/tools/avr/avr/include/avr/iox192c3.h new file mode 100644 index 0000000000000000000000000000000000000000..fc61ec465b67c47ef1fa992e401ff2f98fc620fd --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox192c3.h @@ -0,0 +1,6264 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox192c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA192C3_H_INCLUDED +#define _AVR_ATXMEGA192C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (204800) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (196608) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x2E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x30000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16384) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x51 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox192d3.h b/hardware/tools/avr/avr/include/avr/iox192d3.h new file mode 100644 index 0000000000000000000000000000000000000000..4f5c8bb36f6ad88a664ed526f2912601ba40398a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox192d3.h @@ -0,0 +1,5749 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ + +/* avr/iox192d3.h - definitions for ATxmega192D3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox192d3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega192D3_H_ +#define _AVR_ATxmega192D3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (204800) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (196608) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x2E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x30000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x97 +#define SIGNATURE_2 0x49 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega192D3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256a3.h b/hardware/tools/avr/avr/include/avr/iox256a3.h new file mode 100644 index 0000000000000000000000000000000000000000..9fd58f726157f95373da1df4ef2a2d29a9f8e06e --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256a3.h @@ -0,0 +1,6987 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox256a3.h - definitions for ATxmega256A3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256a3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega256A3_H_ +#define _AVR_ATxmega256A3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (122 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega256A3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256a3b.h b/hardware/tools/avr/avr/include/avr/iox256a3b.h new file mode 100644 index 0000000000000000000000000000000000000000..f5a917e71a201f082bdb548220e6704064fcae6b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256a3b.h @@ -0,0 +1,6983 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox256a3b.h - definitions for ATxmega256A3B */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256a3b.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega256A3B_H_ +#define _AVR_ATxmega256A3B_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated*/ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC32 - 32-bit Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* 32-bit Real-Time Clounter */ +typedef struct RTC32_struct +{ + register8_t CTRL; /* Control Register */ + register8_t SYNCCTRL; /* Synchronization Control/Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _DWORDREGISTER(CNT); /* Count Register */ + _DWORDREGISTER(PER); /* Period Register */ + _DWORDREGISTER(COMP); /* Compare Register */ +} RTC32_t; + +/* Compare Interrupt level */ +typedef enum RTC32_COMPINTLVL_enum +{ + RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC32_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC32_OVFINTLVL_enum +{ + RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC32_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +VBAT - VBAT Battery Backup Module +-------------------------------------------------------------------------- +*/ + +/* VBAT Battery Backup Module */ +typedef struct VBAT_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t BACKUP0; /* Battery Bacup Register 0 */ + register8_t BACKUP1; /* Battery Backup Register 1 */ +} VBAT_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* VBAT - VBAT Battery Backup Module */ +#define VBAT_CTRL _SFR_MEM8(0x00F0) +#define VBAT_STATUS _SFR_MEM8(0x00F1) +#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) +#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC32 - 32-bit Real-Time Counter */ +#define RTC32_CTRL _SFR_MEM8(0x0420) +#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) +#define RTC32_INTCTRL _SFR_MEM8(0x0422) +#define RTC32_INTFLAGS _SFR_MEM8(0x0423) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC32 - 32-bit Real-Time Counter */ +/* RTC32.CTRL bit masks and bit positions */ +#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ +#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ + + +/* RTC32.SYNCCTRL bit masks and bit positions */ +#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ +#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ + +#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC32.INTCTRL bit masks and bit positions */ +#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC32.INTFLAGS bit masks and bit positions */ +#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* VBAT - VBAT Battery Backup Module */ +/* VBAT.CTRL bit masks and bit positions */ +#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ +#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ + +#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ +#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ + +#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ +#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ + +#define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ +#define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ + +#define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ +#define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ + + +/* VBAT.STATUS bit masks and bit positions */ +#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ +#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ + +#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ +#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ + +#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ +#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ + +#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ +#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ + +#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ +#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC32 interrupt vectors */ +#define RTC32_OVF_vect_num 10 +#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC32_COMP_vect_num 11 +#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (122 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x43 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega256A3B_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256a3bu.h b/hardware/tools/avr/avr/include/avr/iox256a3bu.h new file mode 100644 index 0000000000000000000000000000000000000000..12a3fa471538daab48449c73ee6eed333b2a636d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256a3bu.h @@ -0,0 +1,7706 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256a3bu.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA256A3BU_H_INCLUDED +#define _AVR_ATXMEGA256A3BU_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +VBAT - Battery Backup Module +-------------------------------------------------------------------------- +*/ + +/* Battery Backup Module */ +typedef struct VBAT_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t BACKUP0; /* Backup Register 0 */ + register8_t BACKUP1; /* Backup Register 1 */ +} VBAT_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC32 - 32-bit Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* 32-bit Real-Time Counter */ +typedef struct RTC32_struct +{ + register8_t CTRL; /* Control Register */ + register8_t SYNCCTRL; /* Synchronization Control/Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _DWORDREGISTER(CNT); /* Count Register */ + _DWORDREGISTER(PER); /* Period Register */ + _DWORDREGISTER(COMP); /* Compare Register */ +} RTC32_t; + +/* Compare Interrupt level */ +typedef enum RTC32_COMPINTLVL_enum +{ + RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC32_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC32_OVFINTLVL_enum +{ + RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC32_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define VBAT (*(VBAT_t *) 0x00F0) /* Battery Backup Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* VBAT - Battery Backup Module */ +#define VBAT_CTRL _SFR_MEM8(0x00F0) +#define VBAT_STATUS _SFR_MEM8(0x00F1) +#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) +#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC32 - 32-bit Real-Time Counter */ +#define RTC32_CTRL _SFR_MEM8(0x0420) +#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) +#define RTC32_INTCTRL _SFR_MEM8(0x0422) +#define RTC32_INTFLAGS _SFR_MEM8(0x0423) +#define RTC32_CNT _SFR_MEM32(0x0424) +#define RTC32_PER _SFR_MEM32(0x0428) +#define RTC32_COMP _SFR_MEM32(0x042C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* VBAT - Battery Backup Module */ +/* VBAT.CTRL bit masks and bit positions */ +#define VBAT_HIGHESR_bm 0x20 /* 32-kHz Crystal Oscillator High Power Mode bit mask. */ +#define VBAT_HIGHESR_bp 5 /* 32-kHz Crystal Oscillator High Power Mode bit position. */ + +#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ +#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ + +#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ +#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ + +#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ +#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ + +#define VBAT_ACCEN_bm 0x02 /* Access Enable bit mask. */ +#define VBAT_ACCEN_bp 1 /* Access Enable bit position. */ + +#define VBAT_RESET_bm 0x01 /* Reset bit mask. */ +#define VBAT_RESET_bp 0 /* Reset bit position. */ + +/* VBAT.STATUS bit masks and bit positions */ +#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ +#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ + +#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ +#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ + +#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ +#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ + +#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ +#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ + +#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ +#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC32 - 32-bit Real-Time Counter */ +/* RTC32.CTRL bit masks and bit positions */ +#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ +#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ + +/* RTC32.SYNCCTRL bit masks and bit positions */ +#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ +#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ + +#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC32.INTCTRL bit masks and bit positions */ +#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC32.INTFLAGS bit masks and bit positions */ +#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC32 interrupt vectors */ +#define RTC32_OVF_vect_num 10 +#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC32_COMP_vect_num 11 +#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x43 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256a3u.h b/hardware/tools/avr/avr/include/avr/iox256a3u.h new file mode 100644 index 0000000000000000000000000000000000000000..c7ee9a7dec26289d52f725b23da27f0e941623e0 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256a3u.h @@ -0,0 +1,7697 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256a3u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA256A3U_H_INCLUDED +#define _AVR_ATXMEGA256A3U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256c3.h b/hardware/tools/avr/avr/include/avr/iox256c3.h new file mode 100644 index 0000000000000000000000000000000000000000..a856f629341f2672dbe9bdfacbfeaaa571e20b1b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256c3.h @@ -0,0 +1,6264 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA256C3_H_INCLUDED +#define _AVR_ATXMEGA256C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x46 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox256d3.h b/hardware/tools/avr/avr/include/avr/iox256d3.h new file mode 100644 index 0000000000000000000000000000000000000000..e303cac20e432c2ba46c91b4155d8a736a4de316 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox256d3.h @@ -0,0 +1,5709 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ + +/* avr/iox256d3.h - definitions for ATxmega256D3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox256d3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega256D3_H_ +#define _AVR_ATxmega256D3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* ACD Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ +#define ADC_EVACT_bp 0 /* Event Action Select bit position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (270336) +#define PROGMEM_PAGE_SIZE (512) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (262144) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x3E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x40000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (24576) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (16384) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x44 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega256D3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32a4.h b/hardware/tools/avr/avr/include/avr/iox32a4.h new file mode 100644 index 0000000000000000000000000000000000000000..c74862a746d2c6d2c97218233ee681920ad244df --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32a4.h @@ -0,0 +1,6747 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox32a4.h - definitions for ATxmega32A4 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32a4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega32A4_H_ +#define _AVR_ATxmega32A4_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ + BODLVL_2V7_gc = (0x03<<0), /* 2.7 V */ + BODLVL_3V0_gc = (0x02<<0), /* 3.0 V */ + BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ + BODLVL_3V5_gc = (0x00<<0), /* 3.5 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (94 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x07000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega32A4_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32a4u.h b/hardware/tools/avr/avr/include/avr/iox32a4u.h new file mode 100644 index 0000000000000000000000000000000000000000..b74fa592ccf3b0d1f8b22bf7fe627435b73a9937 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32a4u.h @@ -0,0 +1,7309 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32a4u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32A4U_H_INCLUDED +#define _AVR_ATXMEGA32A4U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32c3.h b/hardware/tools/avr/avr/include/avr/iox32c3.h new file mode 100644 index 0000000000000000000000000000000000000000..16f47c4c9574e0697a249bfd0afa96b5ea4692f2 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32c3.h @@ -0,0 +1,6264 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32C3_H_INCLUDED +#define _AVR_ATXMEGA32C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x49 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32c4.h b/hardware/tools/avr/avr/include/avr/iox32c4.h new file mode 100644 index 0000000000000000000000000000000000000000..28a15b31247e8a3a2ae7001d71423355a060b05a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32c4.h @@ -0,0 +1,6078 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32c4.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32C4_H_INCLUDED +#define _AVR_ATXMEGA32C4_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x44 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32d3.h b/hardware/tools/avr/avr/include/avr/iox32d3.h new file mode 100644 index 0000000000000000000000000000000000000000..c3dc8878c21b90f0cd0709665c4e54ce90448ba9 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32d3.h @@ -0,0 +1,5105 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32d3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32D3_H_INCLUDED +#define _AVR_ATXMEGA32D3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* 32.768kHz Timer Oscillator Pin Selection */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register (available for PORTC to PORTF only) */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI Remap bit mask. */ +#define PORT_SPI_bp 5 /* SPI Remap bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 Remap bit mask. */ +#define PORT_USART0_bp 4 /* USART0 Remap bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ +#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ + +#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ +#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4A + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32d4.h b/hardware/tools/avr/avr/include/avr/iox32d4.h new file mode 100644 index 0000000000000000000000000000000000000000..9de38fcfd9dfa8a431758521b31639ce55fd17cc --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32d4.h @@ -0,0 +1,5685 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox32d4.h - definitions for ATxmega32D4 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32d4.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega32D4_H_ +#define _AVR_ATxmega32D4_H_ 1 + + +/* Ungrouped common registers */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* DACB - Digital to Analog Converter B */ + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ + +#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ +#define ADC_CURRENT1_bp 6 /* Current bit position. */ +#define ADC_CURRENT0_bp 5 /* Current bit position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (91 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega32D4_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox32e5.h b/hardware/tools/avr/avr/include/avr/iox32e5.h new file mode 100644 index 0000000000000000000000000000000000000000..dbcf80323b00fd38f05808f4f23051aff626fdbe --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox32e5.h @@ -0,0 +1,7699 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox32e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA32E5_H_INCLUDED +#define _AVR_ATXMEGA32E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (36864) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (32768) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x7000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x8000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (1024) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (1024) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x95 +#define SIGNATURE_2 0x4C + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox384c3.h b/hardware/tools/avr/avr/include/avr/iox384c3.h new file mode 100644 index 0000000000000000000000000000000000000000..937728112127dfaf0189ae8f77b2ff6df9bc22e8 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox384c3.h @@ -0,0 +1,6849 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox384c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA384C3_H_INCLUDED +#define _AVR_ATXMEGA384C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH01_gc = (0x01<<0), /* Channel 0 > channel 1 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ +#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ + +#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ +#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (401408) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (393216) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x5E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x60000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (40960) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (32768) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x45 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox384d3.h b/hardware/tools/avr/avr/include/avr/iox384d3.h new file mode 100644 index 0000000000000000000000000000000000000000..042e1f513a878b0f5d2e8d7068a1e8f362967989 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox384d3.h @@ -0,0 +1,5833 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox384d3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA384D3_H_INCLUDED +#define _AVR_ATXMEGA384D3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (401408) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (393216) +#define APP_SECTION_PAGE_SIZE (512) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x5E000) +#define APPTABLE_SECTION_SIZE (8192) +#define APPTABLE_SECTION_PAGE_SIZE (512) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x60000) +#define BOOT_SECTION_SIZE (8192) +#define BOOT_SECTION_PAGE_SIZE (512) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (40960) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (4096) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (32768) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (4096) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (512) +#define USER_SIGNATURES_PAGE_SIZE (512) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (512) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 512 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x98 +#define SIGNATURE_2 0x47 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64a1.h b/hardware/tools/avr/avr/include/avr/iox64a1.h new file mode 100644 index 0000000000000000000000000000000000000000..b62b1d6788ea9bbe32d8f91df81df85f113476d1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64a1.h @@ -0,0 +1,7236 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ + +/* avr/iox64a1.h - definitions for ATxmega64A1 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64a1.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega64A1_H_ +#define _AVR_ATxmega64A1_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACA (*(DAC_t *) 0x0300) /* Digitalto Analog Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ +#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ +#define PORTK (*(PORT_t *) 0x0720) /* Port K */ +#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACA - Digitalto Analog Converter A */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_TIMCTRL _SFR_MEM8(0x0304) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_GAINCAL _SFR_MEM8(0x0308) +#define DACA_OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* EBI - External Bus Interface */ +#define EBI_CTRL _SFR_MEM8(0x0440) +#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +#define EBI_REFRESH _SFR_MEM16(0x0444) +#define EBI_INITDLY _SFR_MEM16(0x0446) +#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWID - Two-Wire Interface D */ +#define TWID_CTRL _SFR_MEM8(0x0490) +#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* TWIF - Two-Wire Interface F */ +#define TWIF_CTRL _SFR_MEM8(0x04B0) +#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTH - Port H */ +#define PORTH_DIR _SFR_MEM8(0x06E0) +#define PORTH_DIRSET _SFR_MEM8(0x06E1) +#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +#define PORTH_OUT _SFR_MEM8(0x06E4) +#define PORTH_OUTSET _SFR_MEM8(0x06E5) +#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +#define PORTH_IN _SFR_MEM8(0x06E8) +#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) + +/* PORTJ - Port J */ +#define PORTJ_DIR _SFR_MEM8(0x0700) +#define PORTJ_DIRSET _SFR_MEM8(0x0701) +#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +#define PORTJ_OUT _SFR_MEM8(0x0704) +#define PORTJ_OUTSET _SFR_MEM8(0x0705) +#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +#define PORTJ_IN _SFR_MEM8(0x0708) +#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) + +/* PORTK - Port K */ +#define PORTK_DIR _SFR_MEM8(0x0720) +#define PORTK_DIRSET _SFR_MEM8(0x0721) +#define PORTK_DIRCLR _SFR_MEM8(0x0722) +#define PORTK_DIRTGL _SFR_MEM8(0x0723) +#define PORTK_OUT _SFR_MEM8(0x0724) +#define PORTK_OUTSET _SFR_MEM8(0x0725) +#define PORTK_OUTCLR _SFR_MEM8(0x0726) +#define PORTK_OUTTGL _SFR_MEM8(0x0727) +#define PORTK_IN _SFR_MEM8(0x0728) +#define PORTK_INTCTRL _SFR_MEM8(0x0729) +#define PORTK_INT0MASK _SFR_MEM8(0x072A) +#define PORTK_INT1MASK _SFR_MEM8(0x072B) +#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) + +/* PORTQ - Port Q */ +#define PORTQ_DIR _SFR_MEM8(0x07C0) +#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +#define PORTQ_OUT _SFR_MEM8(0x07C4) +#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +#define PORTQ_IN _SFR_MEM8(0x07C8) +#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TCF1 - Timer/Counter F1 */ +#define TCF1_CTRLA _SFR_MEM8(0x0B40) +#define TCF1_CTRLB _SFR_MEM8(0x0B41) +#define TCF1_CTRLC _SFR_MEM8(0x0B42) +#define TCF1_CTRLD _SFR_MEM8(0x0B43) +#define TCF1_CTRLE _SFR_MEM8(0x0B44) +#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +#define TCF1_TEMP _SFR_MEM8(0x0B4F) +#define TCF1_CNT _SFR_MEM16(0x0B60) +#define TCF1_PER _SFR_MEM16(0x0B66) +#define TCF1_CCA _SFR_MEM16(0x0B68) +#define TCF1_CCB _SFR_MEM16(0x0B6A) +#define TCF1_PERBUF _SFR_MEM16(0x0B76) +#define TCF1_CCABUF _SFR_MEM16(0x0B78) +#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TWID interrupt vectors */ +#define TWID_TWIS_vect_num 75 +#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +#define TWID_TWIM_vect_num 76 +#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTQ interrupt vectors */ +#define PORTQ_INT0_vect_num 94 +#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +#define PORTQ_INT1_vect_num 95 +#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ + +/* PORTH interrupt vectors */ +#define PORTH_INT0_vect_num 96 +#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +#define PORTH_INT1_vect_num 97 +#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ + +/* PORTJ interrupt vectors */ +#define PORTJ_INT0_vect_num 98 +#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +#define PORTJ_INT1_vect_num 99 +#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ + +/* PORTK interrupt vectors */ +#define PORTK_INT0_vect_num 100 +#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +#define PORTK_INT1_vect_num 101 +#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TWIF interrupt vectors */ +#define TWIF_TWIS_vect_num 106 +#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +#define TWIF_TWIM_vect_num 107 +#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF1 interrupt vectors */ +#define TCF1_OVF_vect_num 114 +#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +#define TCF1_ERR_vect_num 115 +#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +#define TCF1_CCA_vect_num 116 +#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +#define TCF1_CCB_vect_num 117 +#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ + +/* SPIF interrupt vectors */ +#define SPIF_INT_vect_num 118 +#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USARTF1 interrupt vectors */ +#define USARTF1_RXC_vect_num 122 +#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +#define USARTF1_DRE_vect_num 123 +#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +#define USARTF1_TXC_vect_num 124 +#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (125 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x0F000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16777216) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EXTERNAL_SRAM_START (0x3000) +#define EXTERNAL_SRAM_SIZE (16764928) +#define EXTERNAL_SRAM_PAGE_SIZE (0) +#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND EXTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x4E + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega64A1_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64a1u.h b/hardware/tools/avr/avr/include/avr/iox64a1u.h new file mode 100644 index 0000000000000000000000000000000000000000..45d7f529ccc0fb7e35b737786c959749bda67de5 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64a1u.h @@ -0,0 +1,8305 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64a1u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED +#define _AVR_ATXMEGA64A1U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASPACE_enum +{ + EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASPACE_t; + +/* SRAM Wait State Selection */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* SDRAM Load Mode to Active delay */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* SDRAM Row Cycle Delay */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* SDRAM Row to Precharge Delay */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* SDRAM Write Recovery Delay */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* SDRAM Exit Self Refresh to Active Delay */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* SDRAM Row to Column Delay */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* SDA hold time */ +typedef enum SDA_HOLD_TIME_enum +{ + SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ + SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ + SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ + SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ +} SDA_HOLD_TIME_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ +#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ +#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ +#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* EBI - External Bus Interface */ +#define EBI_CTRL _SFR_MEM8(0x0440) +#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +#define EBI_REFRESH _SFR_MEM16(0x0444) +#define EBI_INITDLY _SFR_MEM16(0x0446) +#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWID_CTRL _SFR_MEM8(0x0490) +#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* TWI - Two-Wire Interface */ +#define TWIF_CTRL _SFR_MEM8(0x04B0) +#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTH_DIR _SFR_MEM8(0x06E0) +#define PORTH_DIRSET _SFR_MEM8(0x06E1) +#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +#define PORTH_OUT _SFR_MEM8(0x06E4) +#define PORTH_OUTSET _SFR_MEM8(0x06E5) +#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +#define PORTH_IN _SFR_MEM8(0x06E8) +#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +#define PORTH_REMAP _SFR_MEM8(0x06EE) +#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) + +/* PORT - I/O Ports */ +#define PORTJ_DIR _SFR_MEM8(0x0700) +#define PORTJ_DIRSET _SFR_MEM8(0x0701) +#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +#define PORTJ_OUT _SFR_MEM8(0x0704) +#define PORTJ_OUTSET _SFR_MEM8(0x0705) +#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +#define PORTJ_IN _SFR_MEM8(0x0708) +#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +#define PORTJ_REMAP _SFR_MEM8(0x070E) +#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) + +/* PORT - I/O Ports */ +#define PORTK_DIR _SFR_MEM8(0x0720) +#define PORTK_DIRSET _SFR_MEM8(0x0721) +#define PORTK_DIRCLR _SFR_MEM8(0x0722) +#define PORTK_DIRTGL _SFR_MEM8(0x0723) +#define PORTK_OUT _SFR_MEM8(0x0724) +#define PORTK_OUTSET _SFR_MEM8(0x0725) +#define PORTK_OUTCLR _SFR_MEM8(0x0726) +#define PORTK_OUTTGL _SFR_MEM8(0x0727) +#define PORTK_IN _SFR_MEM8(0x0728) +#define PORTK_INTCTRL _SFR_MEM8(0x0729) +#define PORTK_INT0MASK _SFR_MEM8(0x072A) +#define PORTK_INT1MASK _SFR_MEM8(0x072B) +#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +#define PORTK_REMAP _SFR_MEM8(0x072E) +#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) + +/* PORT - I/O Ports */ +#define PORTQ_DIR _SFR_MEM8(0x07C0) +#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +#define PORTQ_OUT _SFR_MEM8(0x07C4) +#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +#define PORTQ_IN _SFR_MEM8(0x07C8) +#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +#define PORTQ_REMAP _SFR_MEM8(0x07CE) +#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCF1_CTRLA _SFR_MEM8(0x0B40) +#define TCF1_CTRLB _SFR_MEM8(0x0B41) +#define TCF1_CTRLC _SFR_MEM8(0x0B42) +#define TCF1_CTRLD _SFR_MEM8(0x0B43) +#define TCF1_CTRLE _SFR_MEM8(0x0B44) +#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +#define TCF1_TEMP _SFR_MEM8(0x0B4F) +#define TCF1_CNT _SFR_MEM16(0x0B60) +#define TCF1_PER _SFR_MEM16(0x0B66) +#define TCF1_CCA _SFR_MEM16(0x0B68) +#define TCF1_CCB _SFR_MEM16(0x0B6A) +#define TCF1_PERBUF _SFR_MEM16(0x0B76) +#define TCF1_CCABUF _SFR_MEM16(0x0B78) +#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ +#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ +#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ +#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ +#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ +#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ +#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ +#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ +#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ +#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ +#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ +#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TWID interrupt vectors */ +#define TWID_TWIS_vect_num 75 +#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +#define TWID_TWIM_vect_num 76 +#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTQ interrupt vectors */ +#define PORTQ_INT0_vect_num 94 +#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +#define PORTQ_INT1_vect_num 95 +#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ + +/* PORTH interrupt vectors */ +#define PORTH_INT0_vect_num 96 +#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +#define PORTH_INT1_vect_num 97 +#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ + +/* PORTJ interrupt vectors */ +#define PORTJ_INT0_vect_num 98 +#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +#define PORTJ_INT1_vect_num 99 +#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ + +/* PORTK interrupt vectors */ +#define PORTK_INT0_vect_num 100 +#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +#define PORTK_INT1_vect_num 101 +#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TWIF interrupt vectors */ +#define TWIF_TWIS_vect_num 106 +#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +#define TWIF_TWIM_vect_num 107 +#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* TCF1 interrupt vectors */ +#define TCF1_OVF_vect_num 114 +#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +#define TCF1_ERR_vect_num 115 +#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +#define TCF1_CCA_vect_num 116 +#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +#define TCF1_CCB_vect_num 117 +#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ + +/* SPIF interrupt vectors */ +#define SPIF_INT_vect_num 118 +#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USARTF1 interrupt vectors */ +#define USARTF1_RXC_vect_num 122 +#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +#define USARTF1_DRE_vect_num 123 +#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +#define USARTF1_TXC_vect_num 124 +#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (16777216) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x4E + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64a3.h b/hardware/tools/avr/avr/include/avr/iox64a3.h new file mode 100644 index 0000000000000000000000000000000000000000..f656d85942626ea29d8e64d69fbe2d37a884aa76 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64a3.h @@ -0,0 +1,6987 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ + +/* avr/iox64a3.h - definitions for ATxmega64A3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64a3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega64A3_H_ +#define _AVR_ATxmega64A3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ + BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t TIMCTRL; /* Timing Control */ + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t GAINCAL; /* Gain Calibration */ + register8_t OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + +/* Conversion interval */ +typedef enum DAC_CONINTVAL_enum +{ + DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ + DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ + DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ + DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ + DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ + DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ + DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ + DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +} DAC_CONINTVAL_t; + +/* Refresh rate */ +typedef enum DAC_REFRESH_enum +{ + DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ + DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ + DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ + DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ + DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ + DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ + DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ + DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ + DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ + DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ + DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ + DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ + DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ + DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +} DAC_REFRESH_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* AES - AES Crypto Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) + +/* ADCB - Analog to Digital Converter B */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) + +/* DACB - Digital to Analog Converter B */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_TIMCTRL _SFR_MEM8(0x0324) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_GAINCAL _SFR_MEM8(0x0328) +#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TCD1 - Timer/Counter D1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRESD - High-Resolution Extension D */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TCE1 - Timer/Counter E1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRESE - High-Resolution Extension E */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* HIRESF - High-Resolution Extension F */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + +/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +#define USARTF1_DATA _SFR_MEM8(0x0BB0) +#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) + +/* SPIF - Serial Peripheral Interface F */ +#define SPIF_CTRL _SFR_MEM8(0x0BC0) +#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +#define SPIF_STATUS _SFR_MEM8(0x0BC2) +#define SPIF_DATA _SFR_MEM8(0x0BC3) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC_bm Predefined. */ +/* PR_DAC_bp Predefined. */ + +/* PR_ADC_bm Predefined. */ +/* PR_ADC_bp Predefined. */ + +/* PR_AC_bm Predefined. */ +/* PR_AC_bp Predefined. */ + + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART1_bm Predefined. */ +/* PR_USART1_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_HIRES_bm Predefined. */ +/* PR_HIRES_bp Predefined. */ + +/* PR_TC1_bm Predefined. */ +/* PR_TC1_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + + +/* DAC.TIMCTRL bit masks and bit positions */ +#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ + +#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ + + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ + +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRL bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (122 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x0F000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega64A3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64a3u.h b/hardware/tools/avr/avr/include/avr/iox64a3u.h new file mode 100644 index 0000000000000000000000000000000000000000..0d230d869181ccda7dedb908989a27f540b2816a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64a3u.h @@ -0,0 +1,7697 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64a3u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64A3U_H_INCLUDED +#define _AVR_ATXMEGA64A3U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ +#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ +#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CH1RES _SFR_MEM16(0x0252) +#define ADCB_CH2RES _SFR_MEM16(0x0254) +#define ADCB_CH3RES _SFR_MEM16(0x0256) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) +#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +#define ADCB_CH1_RES _SFR_MEM16(0x026C) +#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) +#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +#define ADCB_CH2_RES _SFR_MEM16(0x0274) +#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) +#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +#define ADCB_CH3_RES _SFR_MEM16(0x027C) +#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCE1_CTRLA _SFR_MEM8(0x0A40) +#define TCE1_CTRLB _SFR_MEM8(0x0A41) +#define TCE1_CTRLC _SFR_MEM8(0x0A42) +#define TCE1_CTRLD _SFR_MEM8(0x0A43) +#define TCE1_CTRLE _SFR_MEM8(0x0A44) +#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +#define TCE1_TEMP _SFR_MEM8(0x0A4F) +#define TCE1_CNT _SFR_MEM16(0x0A60) +#define TCE1_PER _SFR_MEM16(0x0A66) +#define TCE1_CCA _SFR_MEM16(0x0A68) +#define TCE1_CCB _SFR_MEM16(0x0A6A) +#define TCE1_PERBUF _SFR_MEM16(0x0A76) +#define TCE1_CCABUF _SFR_MEM16(0x0A78) +#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE1_DATA _SFR_MEM8(0x0AB0) +#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) + +/* SPI - Serial Peripheral Interface */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + +/* HIRES - High-Resolution Extension */ +#define HIRESF_CTRLA _SFR_MEM8(0x0B90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTF0_DATA _SFR_MEM8(0x0BA0) +#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 36 +#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 37 +#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 38 +#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 39 +#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +#define ADCB_CH1_vect_num 40 +#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +#define ADCB_CH2_vect_num 41 +#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +#define ADCB_CH3_vect_num 42 +#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* TCE1 interrupt vectors */ +#define TCE1_OVF_vect_num 53 +#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +#define TCE1_ERR_vect_num 54 +#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +#define TCE1_CCA_vect_num 55 +#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +#define TCE1_CCB_vect_num 56 +#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ + +/* SPIE interrupt vectors */ +#define SPIE_INT_vect_num 57 +#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* USARTE1 interrupt vectors */ +#define USARTE1_RXC_vect_num 61 +#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +#define USARTE1_DRE_vect_num 62 +#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +#define USARTE1_TXC_vect_num 63 +#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USARTF0 interrupt vectors */ +#define USARTF0_RXC_vect_num 119 +#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +#define USARTF0_DRE_vect_num 120 +#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +#define USARTF0_TXC_vect_num 121 +#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x42 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64a4u.h b/hardware/tools/avr/avr/include/avr/iox64a4u.h new file mode 100644 index 0000000000000000000000000000000000000000..b8632ac9c52d1f4582bd4852aab32dfe4834a077 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64a4u.h @@ -0,0 +1,7309 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64a4u.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64A4U_H_INCLUDED +#define _AVR_ATXMEGA64A4U_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t EBIOUT; /* EBI Output register */ + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* EBI Address Output Port */ +typedef enum PORTCFG_EBIADROUT_enum +{ + PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ + PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ + PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ + PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ +} PORTCFG_EBIADROUT_t; + +/* EBI Chip Select Output Port */ +typedef enum PORTCFG_EBICSOUT_enum +{ + PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ + PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ + PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ + PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ +} PORTCFG_EBICSOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t SRCADDR2; /* Channel Source Address 2 */ + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t DESTADDR2; /* Channel Destination Address 2 */ + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ + DMA_CH_t CH2; /* DMA Channel 2 */ + DMA_CH_t CH3; /* DMA Channel 3 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ + DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ + DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ + DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ + DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ + DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ + DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ + DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ + DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ + DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ + DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ + DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ + DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ + DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ + DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ + DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ + DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ + DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ + DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ + DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ + DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ + DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ + DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ + DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ + DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ + DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ + DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ + DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ + DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ + DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ + DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ + DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ + DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ + DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ + EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ + EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ + EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ + EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ + EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + _WORDREGISTER(CH1RES); /* Channel 1 Result */ + _WORDREGISTER(CH2RES); /* Channel 2 Result */ + _WORDREGISTER(CH3RES); /* Channel 3 Result */ + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ + ADC_CH_t CH1; /* ADC Channel 1 */ + ADC_CH_t CH2; /* ADC Channel 2 */ + ADC_CH_t CH3; /* ADC Channel 3 */ +} ADC_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ + ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ + ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Current Limitation Mode */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ +} ADC_CURRLIMIT_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ + ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ + ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ + ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ + ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ + ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ + ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* DMA request selection */ +typedef enum ADC_DMASEL_enum +{ + ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ + ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ + ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ + ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +} ADC_DMASEL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ + register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ + register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ +#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) +#define GPIO_GPIO4 _SFR_MEM8(0x0004) +#define GPIO_GPIO5 _SFR_MEM8(0x0005) +#define GPIO_GPIO6 _SFR_MEM8(0x0006) +#define GPIO_GPIO7 _SFR_MEM8(0x0007) +#define GPIO_GPIO8 _SFR_MEM8(0x0008) +#define GPIO_GPIO9 _SFR_MEM8(0x0009) +#define GPIO_GPIOA _SFR_MEM8(0x000A) +#define GPIO_GPIOB _SFR_MEM8(0x000B) +#define GPIO_GPIOC _SFR_MEM8(0x000C) +#define GPIO_GPIOD _SFR_MEM8(0x000D) +#define GPIO_GPIOE _SFR_MEM8(0x000E) +#define GPIO_GPIOF _SFR_MEM8(0x000F) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) +#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) +#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) +#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CH1RES _SFR_MEM16(0x0212) +#define ADCA_CH2RES _SFR_MEM16(0x0214) +#define ADCA_CH3RES _SFR_MEM16(0x0216) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +#define ADCA_CH1_RES _SFR_MEM16(0x022C) +#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) +#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +#define ADCA_CH2_RES _SFR_MEM16(0x0234) +#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) +#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +#define ADCA_CH3_RES _SFR_MEM16(0x023C) +#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) + +/* DAC - Digital-to-Analog Converter */ +#define DACB_CTRLA _SFR_MEM8(0x0320) +#define DACB_CTRLB _SFR_MEM8(0x0321) +#define DACB_CTRLC _SFR_MEM8(0x0322) +#define DACB_EVCTRL _SFR_MEM8(0x0323) +#define DACB_STATUS _SFR_MEM8(0x0325) +#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +#define DACB_CH0DATA _SFR_MEM16(0x0338) +#define DACB_CH1DATA _SFR_MEM16(0x033A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC1_DATA _SFR_MEM8(0x08B0) +#define USARTC1_STATUS _SFR_MEM8(0x08B1) +#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCD1_CTRLA _SFR_MEM8(0x0940) +#define TCD1_CTRLB _SFR_MEM8(0x0941) +#define TCD1_CTRLC _SFR_MEM8(0x0942) +#define TCD1_CTRLD _SFR_MEM8(0x0943) +#define TCD1_CTRLE _SFR_MEM8(0x0944) +#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +#define TCD1_TEMP _SFR_MEM8(0x094F) +#define TCD1_CNT _SFR_MEM16(0x0960) +#define TCD1_PER _SFR_MEM16(0x0966) +#define TCD1_CCA _SFR_MEM16(0x0968) +#define TCD1_CCB _SFR_MEM16(0x096A) +#define TCD1_PERBUF _SFR_MEM16(0x0976) +#define TCD1_CCABUF _SFR_MEM16(0x0978) +#define TCD1_CCBBUF _SFR_MEM16(0x097A) + +/* HIRES - High-Resolution Extension */ +#define HIRESD_CTRLA _SFR_MEM8(0x0990) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD1_DATA _SFR_MEM8(0x09B0) +#define USARTD1_STATUS _SFR_MEM8(0x09B1) +#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* HIRES - High-Resolution Extension */ +#define HIRESE_CTRLA _SFR_MEM8(0x0A90) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +#define PR_EBI_bp 3 /* External Bus Interface bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_DAC Predefined. */ +/* PR_DAC Predefined. */ + +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART1 Predefined. */ +/* PR_USART1 Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_HIRES Predefined. */ +/* PR_HIRES Predefined. */ + +/* PR_TC1 Predefined. */ +/* PR_TC1 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ +#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ + +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ +#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EBIOUT bit masks and bit positions */ +#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ +#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ +#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ +#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ +#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ +#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ + +#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ +#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ +#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ +#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ +#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ +#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ + +#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ + +#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ + +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ + +#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_QDIRM Predefined. */ +/* EVSYS_QDIRM Predefined. */ + +/* EVSYS_QDIEN Predefined. */ +/* EVSYS_QDIEN Predefined. */ + +/* EVSYS_QDEN Predefined. */ +/* EVSYS_QDEN Predefined. */ + +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ +#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ + +#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ + +#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ + +#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ + +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ + +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ + +#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ + +#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ + +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HSMODE Predefined. */ +/* AC_HSMODE Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +#define DMA_CH2_vect_num 8 +#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +#define DMA_CH3_vect_num 9 +#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USARTC1 interrupt vectors */ +#define USARTC1_RXC_vect_num 28 +#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +#define USARTC1_DRE_vect_num 29 +#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +#define USARTC1_TXC_vect_num 30 +#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 31 +#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +#define ADCA_CH1_vect_num 72 +#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +#define ADCA_CH2_vect_num 73 +#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +#define ADCA_CH3_vect_num 74 +#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* TCD1 interrupt vectors */ +#define TCD1_OVF_vect_num 83 +#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +#define TCD1_ERR_vect_num 84 +#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +#define TCD1_CCA_vect_num 85 +#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +#define TCD1_CCB_vect_num 86 +#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* USARTD1 interrupt vectors */ +#define USARTD1_RXC_vect_num 91 +#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +#define USARTD1_DRE_vect_num 92 +#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +#define USARTD1_TXC_vect_num 93 +#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x46 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_EBI_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_EBI +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_DAC +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_TWI +#define __AVR_HAVE_PRPD_USART1 +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_HIRES +#define __AVR_HAVE_PRPD_TC1 +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART1 +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_SPI +#define __AVR_HAVE_PRPE_HIRES +#define __AVR_HAVE_PRPE_TC1 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_TWI +#define __AVR_HAVE_PRPF_USART1 +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_SPI +#define __AVR_HAVE_PRPF_HIRES +#define __AVR_HAVE_PRPF_TC1 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64b1.h b/hardware/tools/avr/avr/include/avr/iox64b1.h new file mode 100644 index 0000000000000000000000000000000000000000..6f44899c86c9a83dbc8d8e371b02628901fb3b2d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64b1.h @@ -0,0 +1,6454 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64b1.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64B1_H_INCLUDED +#define _AVR_ATXMEGA64B1_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +PR - Power Reduction +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t reserved_0x04; + register8_t PRPE; /* Power Reduction Port E */ +} PR_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ + PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ + PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +LCD - LCD Controller +-------------------------------------------------------------------------- +*/ + +/* LCD Controller */ +typedef struct LCD_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t INTCTRL; /* Interrupt Enable Register */ + register8_t INTFLAG; /* Interrupt Flag Register */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t CTRLH; /* Control Register H */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t DATA0; /* LCD Data Register 0 */ + register8_t DATA1; /* LCD Data Register 1 */ + register8_t DATA2; /* LCD Data Register 2 */ + register8_t DATA3; /* LCD Data Register 3 */ + register8_t DATA4; /* LCD Data Register 4 */ + register8_t DATA5; /* LCD Data Register 5 */ + register8_t DATA6; /* LCD Data Register 6 */ + register8_t DATA7; /* LCD Data Register 7 */ + register8_t DATA8; /* LCD Data Register 8 */ + register8_t DATA9; /* LCD Data Register 9 */ + register8_t DATA10; /* LCD Data Register 10 */ + register8_t DATA11; /* LCD Data Register 11 */ + register8_t DATA12; /* LCD Data Register 12 */ + register8_t DATA13; /* LCD Data Register 13 */ + register8_t DATA14; /* LCD Data Register 14 */ + register8_t DATA15; /* LCD Data Register 15 */ + register8_t DATA16; /* LCD Data Register 16 */ + register8_t DATA17; /* LCD Data Register 17 */ + register8_t DATA18; /* LCD Data Register 18 */ + register8_t DATA19; /* LCD Data Register 19 */ +} LCD_t; + +/* LCD Blink Rate */ +typedef enum LCD_BLINKRATE_enum +{ + LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ + LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ + LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ + LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ +} LCD_BLINKRATE_t; + +/* LCD Clock Divide */ +typedef enum LCD_CLKDIV_enum +{ + LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ + LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ + LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ + LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ + LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ + LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ + LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ + LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ +} LCD_CLKDIV_t; + +/* Duty Select */ +typedef enum LCD_DUTY_enum +{ + LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ + LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ + LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ + LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ +} LCD_DUTY_t; + +/* LCD Prescaler Select */ +typedef enum LCD_PRESC_enum +{ + LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ + LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ +} LCD_PRESC_t; + +/* Type of Digit */ +typedef enum LCD_TDG_enum +{ + LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ + LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ + LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ + LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ +} LCD_TDG_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ +#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPE _SFR_MEM8(0x0075) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) +#define ACB_CURRCTRL _SFR_MEM8(0x0398) +#define ACB_CURRCALIB _SFR_MEM8(0x0399) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x06C0) +#define PORTG_DIRSET _SFR_MEM8(0x06C1) +#define PORTG_DIRCLR _SFR_MEM8(0x06C2) +#define PORTG_DIRTGL _SFR_MEM8(0x06C3) +#define PORTG_OUT _SFR_MEM8(0x06C4) +#define PORTG_OUTSET _SFR_MEM8(0x06C5) +#define PORTG_OUTCLR _SFR_MEM8(0x06C6) +#define PORTG_OUTTGL _SFR_MEM8(0x06C7) +#define PORTG_IN _SFR_MEM8(0x06C8) +#define PORTG_INTCTRL _SFR_MEM8(0x06C9) +#define PORTG_INT0MASK _SFR_MEM8(0x06CA) +#define PORTG_INT1MASK _SFR_MEM8(0x06CB) +#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) +#define PORTG_REMAP _SFR_MEM8(0x06CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) + +/* PORT - I/O Ports */ +#define PORTM_DIR _SFR_MEM8(0x0760) +#define PORTM_DIRSET _SFR_MEM8(0x0761) +#define PORTM_DIRCLR _SFR_MEM8(0x0762) +#define PORTM_DIRTGL _SFR_MEM8(0x0763) +#define PORTM_OUT _SFR_MEM8(0x0764) +#define PORTM_OUTSET _SFR_MEM8(0x0765) +#define PORTM_OUTCLR _SFR_MEM8(0x0766) +#define PORTM_OUTTGL _SFR_MEM8(0x0767) +#define PORTM_IN _SFR_MEM8(0x0768) +#define PORTM_INTCTRL _SFR_MEM8(0x0769) +#define PORTM_INT0MASK _SFR_MEM8(0x076A) +#define PORTM_INT1MASK _SFR_MEM8(0x076B) +#define PORTM_INTFLAGS _SFR_MEM8(0x076C) +#define PORTM_REMAP _SFR_MEM8(0x076E) +#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) +#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) +#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) +#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) +#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) +#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) +#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) +#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* LCD - LCD Controller */ +#define LCD_CTRLA _SFR_MEM8(0x0D00) +#define LCD_CTRLB _SFR_MEM8(0x0D01) +#define LCD_CTRLC _SFR_MEM8(0x0D02) +#define LCD_INTCTRL _SFR_MEM8(0x0D03) +#define LCD_INTFLAG _SFR_MEM8(0x0D04) +#define LCD_CTRLD _SFR_MEM8(0x0D05) +#define LCD_CTRLE _SFR_MEM8(0x0D06) +#define LCD_CTRLF _SFR_MEM8(0x0D07) +#define LCD_CTRLG _SFR_MEM8(0x0D08) +#define LCD_CTRLH _SFR_MEM8(0x0D09) +#define LCD_DATA0 _SFR_MEM8(0x0D10) +#define LCD_DATA1 _SFR_MEM8(0x0D11) +#define LCD_DATA2 _SFR_MEM8(0x0D12) +#define LCD_DATA3 _SFR_MEM8(0x0D13) +#define LCD_DATA4 _SFR_MEM8(0x0D14) +#define LCD_DATA5 _SFR_MEM8(0x0D15) +#define LCD_DATA6 _SFR_MEM8(0x0D16) +#define LCD_DATA7 _SFR_MEM8(0x0D17) +#define LCD_DATA8 _SFR_MEM8(0x0D18) +#define LCD_DATA9 _SFR_MEM8(0x0D19) +#define LCD_DATA10 _SFR_MEM8(0x0D1A) +#define LCD_DATA11 _SFR_MEM8(0x0D1B) +#define LCD_DATA12 _SFR_MEM8(0x0D1C) +#define LCD_DATA13 _SFR_MEM8(0x0D1D) +#define LCD_DATA14 _SFR_MEM8(0x0D1E) +#define LCD_DATA15 _SFR_MEM8(0x0D1F) +#define LCD_DATA16 _SFR_MEM8(0x0D20) +#define LCD_DATA17 _SFR_MEM8(0x0D21) +#define LCD_DATA18 _SFR_MEM8(0x0D22) +#define LCD_DATA19 _SFR_MEM8(0x0D23) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* PR - Power Reduction */ +/* PR.PRGEN bit masks and bit positions */ +#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ +#define PR_LCD_bp 7 /* LCD Module bit position. */ + +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ +#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ +#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ + +#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ +#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* LCD - LCD Controller */ +/* LCD.CTRLA bit masks and bit positions */ +#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ +#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ + +#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ +#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ + +#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ +#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ + +#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ +#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ + +#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ +#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ + +#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ +#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ + +#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ +#define LCD_SEGON_bp 1 /* Segments On bit position. */ + +#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ +#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ + +/* LCD.CTRLB bit masks and bit positions */ +#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ +#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ + +#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ +#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ +#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ +#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ +#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ +#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ +#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ +#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ + +#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ +#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ + +#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ +#define LCD_DUTY_gp 0 /* Duty Select group position. */ +#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ +#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ +#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ +#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ + +/* LCD.CTRLC bit masks and bit positions */ +#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ +#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ +#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ +#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ +#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ +#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ +#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ +#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ +#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ +#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ +#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ +#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ +#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ +#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ + +/* LCD.INTCTRL bit masks and bit positions */ +#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ +#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ +#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ +#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ +#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ +#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ +#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ +#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ +#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ +#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ +#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ +#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ + +#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ +#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* LCD.INTFLAG bit masks and bit positions */ +#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ +#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ + +/* LCD.CTRLD bit masks and bit positions */ +#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ +#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ + +#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ +#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ +#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ +#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ +#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ +#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ + +/* LCD.CTRLE bit masks and bit positions */ +#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ +#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ +#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ +#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ +#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ +#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ +#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ +#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ +#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ +#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ + +#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ +#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ +#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ +#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ +#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ +#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ +#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ +#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ +#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ +#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ + +/* LCD.CTRLF bit masks and bit positions */ +#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ +#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ +#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ +#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ +#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ +#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ +#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ +#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ +#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ +#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ +#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ +#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ +#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ +#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ + +/* LCD.CTRLG bit masks and bit positions */ +#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ +#define LCD_TDG_gp 6 /* Type of Digit group position. */ +#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ +#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ +#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ +#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ + +#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ +#define LCD_STSEG_gp 0 /* Start Segment group position. */ +#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ +#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ +#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ +#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ +#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ +#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ +#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ +#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ +#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ +#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ +#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ +#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ + +/* LCD.CTRLH bit masks and bit positions */ +#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ +#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ + +#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ +#define LCD_DCODE_gp 0 /* Display Code group position. */ +#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ +#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ +#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ +#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ +#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ +#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ +#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ +#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ +#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ +#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ +#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ +#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ +#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ +#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 31 +#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 32 +#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ + +/* LCD interrupt vectors */ +#define LCD_INT_vect_num 35 +#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 36 +#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 37 +#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ +#define NVM_SPM_vect_num 38 +#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 39 +#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 40 +#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 41 +#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 42 +#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 43 +#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 44 +#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 48 +#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 49 +#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ + +/* PORTG interrupt vectors */ +#define PORTG_INT0_vect_num 50 +#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ +#define PORTG_INT1_vect_num 51 +#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ + +/* PORTM interrupt vectors */ +#define PORTM_INT0_vect_num 52 +#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ +#define PORTM_INT1_vect_num 53 +#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 54 +#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 55 +#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 58 +#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 59 +#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ +#define TCE0_CCA_vect_num 60 +#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 61 +#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 62 +#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 63 +#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 69 +#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 70 +#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 71 +#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 75 +#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 76 +#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 77 +#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 78 +#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 79 +#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 80 +#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (81 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x52 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_LCD +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64b3.h b/hardware/tools/avr/avr/include/avr/iox64b3.h new file mode 100644 index 0000000000000000000000000000000000000000..1cdf5de7b5ebdeec776b8b8871e34d9bc2713b12 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64b3.h @@ -0,0 +1,6288 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64b3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64B3_H_INCLUDED +#define _AVR_ATXMEGA64B3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ + OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +PR - Power Reduction +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t PRPB; /* Power Reduction Port B */ + register8_t PRPC; /* Power Reduction Port C */ + register8_t reserved_0x04; + register8_t PRPE; /* Power Reduction Port E */ +} PR_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ + PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ + PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ +} PORTCFG_EVOUT_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +AES - AES Module +-------------------------------------------------------------------------- +*/ + +/* AES Module */ +typedef struct AES_struct +{ + register8_t CTRL; /* AES Control Register */ + register8_t STATUS; /* AES Status Register */ + register8_t STATE; /* AES State Register */ + register8_t KEY; /* AES Key Register */ + register8_t INTCTRL; /* AES Interrupt Control Register */ +} AES_t; + +/* Interrupt level */ +typedef enum AES_INTLVL_enum +{ + AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} AES_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +DMA - DMA Controller +-------------------------------------------------------------------------- +*/ + +/* DMA Channel */ +typedef struct DMA_CH_struct +{ + register8_t CTRLA; /* Channel Control */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Address Control */ + register8_t TRIGSRC; /* Channel Trigger Source */ + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ + register8_t REPCNT; /* Channel Repeat Count */ + register8_t reserved_0x07; + register8_t SRCADDR0; /* Channel Source Address 0 */ + register8_t SRCADDR1; /* Channel Source Address 1 */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t DESTADDR0; /* Channel Destination Address 0 */ + register8_t DESTADDR1; /* Channel Destination Address 1 */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} DMA_CH_t; + + +/* DMA Controller */ +typedef struct DMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + DMA_CH_t CH0; /* DMA Channel 0 */ + DMA_CH_t CH1; /* DMA Channel 1 */ +} DMA_t; + +/* Burst mode */ +typedef enum DMA_CH_BURSTLEN_enum +{ + DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ + DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ + DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ + DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +} DMA_CH_BURSTLEN_t; + +/* Source address reload mode */ +typedef enum DMA_CH_SRCRELOAD_enum +{ + DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ + DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ + DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ + DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +} DMA_CH_SRCRELOAD_t; + +/* Source addressing mode */ +typedef enum DMA_CH_SRCDIR_enum +{ + DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ + DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ + DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +} DMA_CH_SRCDIR_t; + +/* Destination adress reload mode */ +typedef enum DMA_CH_DESTRELOAD_enum +{ + DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ + DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ + DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ + DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +} DMA_CH_DESTRELOAD_t; + +/* Destination adressing mode */ +typedef enum DMA_CH_DESTDIR_enum +{ + DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +} DMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum DMA_CH_TRIGSRC_enum +{ + DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ + DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ + DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ + DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ + DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ + DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ + DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ + DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ + DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ + DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ + DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ + DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ + DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ + DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ + DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ + DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ + DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ + DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ + DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ + DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ + DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ + DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ + DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ + DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +} DMA_CH_TRIGSRC_t; + +/* Double buffering mode */ +typedef enum DMA_DBUFMODE_enum +{ + DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ + DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +} DMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum DMA_PRIMODE_enum +{ + DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ + DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ +} DMA_PRIMODE_t; + +/* Interrupt level */ +typedef enum DMA_CH_ERRINTLVL_enum +{ + DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ + DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ + DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +} DMA_CH_ERRINTLVL_t; + +/* Interrupt level */ +typedef enum DMA_CH_TRNINTLVL_enum +{ + DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ + DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ + DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +} DMA_CH_TRNINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ + EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ + EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +LCD - LCD Controller +-------------------------------------------------------------------------- +*/ + +/* LCD Controller */ +typedef struct LCD_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t INTCTRL; /* Interrupt Enable Register */ + register8_t INTFLAG; /* Interrupt Flag Register */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t CTRLH; /* Control Register H */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t DATA0; /* LCD Data Register 0 */ + register8_t DATA1; /* LCD Data Register 1 */ + register8_t DATA2; /* LCD Data Register 2 */ + register8_t DATA3; /* LCD Data Register 3 */ + register8_t DATA4; /* LCD Data Register 4 */ + register8_t DATA5; /* LCD Data Register 5 */ + register8_t DATA6; /* LCD Data Register 6 */ + register8_t DATA7; /* LCD Data Register 7 */ + register8_t DATA8; /* LCD Data Register 8 */ + register8_t DATA9; /* LCD Data Register 9 */ + register8_t DATA10; /* LCD Data Register 10 */ + register8_t DATA11; /* LCD Data Register 11 */ + register8_t DATA12; /* LCD Data Register 12 */ + register8_t DATA13; /* LCD Data Register 13 */ + register8_t DATA14; /* LCD Data Register 14 */ + register8_t DATA15; /* LCD Data Register 15 */ + register8_t DATA16; /* LCD Data Register 16 */ + register8_t DATA17; /* LCD Data Register 17 */ + register8_t DATA18; /* LCD Data Register 18 */ + register8_t DATA19; /* LCD Data Register 19 */ +} LCD_t; + +/* LCD Blink Rate */ +typedef enum LCD_BLINKRATE_enum +{ + LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ + LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ + LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ + LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ +} LCD_BLINKRATE_t; + +/* LCD Clock Divide */ +typedef enum LCD_CLKDIV_enum +{ + LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ + LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ + LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ + LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ + LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ + LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ + LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ + LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ +} LCD_CLKDIV_t; + +/* Duty Select */ +typedef enum LCD_DUTY_enum +{ + LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ + LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ + LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ + LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ +} LCD_DUTY_t; + +/* LCD Prescaler Select */ +typedef enum LCD_PRESC_enum +{ + LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ + LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ +} LCD_PRESC_t; + +/* Type of Digit */ +typedef enum LCD_TDG_enum +{ + LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ + LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ + LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ + LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ +} LCD_TDG_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* JTAG User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; + register8_t reserved_0x40; + register8_t reserved_0x41; + register8_t reserved_0x42; + register8_t reserved_0x43; + register8_t reserved_0x44; + register8_t reserved_0x45; + register8_t reserved_0x46; + register8_t reserved_0x47; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define AES (*(AES_t *) 0x00C0) /* AES Module */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ +#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) +#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPB _SFR_MEM8(0x0072) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPE _SFR_MEM8(0x0075) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* AES - AES Module */ +#define AES_CTRL _SFR_MEM8(0x00C0) +#define AES_STATUS _SFR_MEM8(0x00C1) +#define AES_STATE _SFR_MEM8(0x00C2) +#define AES_KEY _SFR_MEM8(0x00C3) +#define AES_INTCTRL _SFR_MEM8(0x00C4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* DMA - DMA Controller */ +#define DMA_CTRL _SFR_MEM8(0x0100) +#define DMA_INTFLAGS _SFR_MEM8(0x0103) +#define DMA_STATUS _SFR_MEM8(0x0104) +#define DMA_TEMP _SFR_MEM16(0x0106) +#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCB_CTRLA _SFR_MEM8(0x0240) +#define ADCB_CTRLB _SFR_MEM8(0x0241) +#define ADCB_REFCTRL _SFR_MEM8(0x0242) +#define ADCB_EVCTRL _SFR_MEM8(0x0243) +#define ADCB_PRESCALER _SFR_MEM8(0x0244) +#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +#define ADCB_TEMP _SFR_MEM8(0x0247) +#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) +#define ADCB_CAL _SFR_MEM16(0x024C) +#define ADCB_CH0RES _SFR_MEM16(0x0250) +#define ADCB_CMP _SFR_MEM16(0x0258) +#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +#define ADCB_CH0_RES _SFR_MEM16(0x0264) +#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) + +/* AC - Analog Comparator */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) +#define ACB_CURRCTRL _SFR_MEM8(0x0398) +#define ACB_CURRCALIB _SFR_MEM8(0x0399) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTG_DIR _SFR_MEM8(0x06C0) +#define PORTG_DIRSET _SFR_MEM8(0x06C1) +#define PORTG_DIRCLR _SFR_MEM8(0x06C2) +#define PORTG_DIRTGL _SFR_MEM8(0x06C3) +#define PORTG_OUT _SFR_MEM8(0x06C4) +#define PORTG_OUTSET _SFR_MEM8(0x06C5) +#define PORTG_OUTCLR _SFR_MEM8(0x06C6) +#define PORTG_OUTTGL _SFR_MEM8(0x06C7) +#define PORTG_IN _SFR_MEM8(0x06C8) +#define PORTG_INTCTRL _SFR_MEM8(0x06C9) +#define PORTG_INT0MASK _SFR_MEM8(0x06CA) +#define PORTG_INT1MASK _SFR_MEM8(0x06CB) +#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) +#define PORTG_REMAP _SFR_MEM8(0x06CE) +#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) +#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) +#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) +#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) +#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) +#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) +#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) +#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) + +/* PORT - I/O Ports */ +#define PORTM_DIR _SFR_MEM8(0x0760) +#define PORTM_DIRSET _SFR_MEM8(0x0761) +#define PORTM_DIRCLR _SFR_MEM8(0x0762) +#define PORTM_DIRTGL _SFR_MEM8(0x0763) +#define PORTM_OUT _SFR_MEM8(0x0764) +#define PORTM_OUTSET _SFR_MEM8(0x0765) +#define PORTM_OUTCLR _SFR_MEM8(0x0766) +#define PORTM_OUTTGL _SFR_MEM8(0x0767) +#define PORTM_IN _SFR_MEM8(0x0768) +#define PORTM_INTCTRL _SFR_MEM8(0x0769) +#define PORTM_INT0MASK _SFR_MEM8(0x076A) +#define PORTM_INT1MASK _SFR_MEM8(0x076B) +#define PORTM_INTFLAGS _SFR_MEM8(0x076C) +#define PORTM_REMAP _SFR_MEM8(0x076E) +#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) +#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) +#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) +#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) +#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) +#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) +#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) +#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* LCD - LCD Controller */ +#define LCD_CTRLA _SFR_MEM8(0x0D00) +#define LCD_CTRLB _SFR_MEM8(0x0D01) +#define LCD_CTRLC _SFR_MEM8(0x0D02) +#define LCD_INTCTRL _SFR_MEM8(0x0D03) +#define LCD_INTFLAG _SFR_MEM8(0x0D04) +#define LCD_CTRLD _SFR_MEM8(0x0D05) +#define LCD_CTRLE _SFR_MEM8(0x0D06) +#define LCD_CTRLF _SFR_MEM8(0x0D07) +#define LCD_CTRLG _SFR_MEM8(0x0D08) +#define LCD_CTRLH _SFR_MEM8(0x0D09) +#define LCD_DATA0 _SFR_MEM8(0x0D10) +#define LCD_DATA1 _SFR_MEM8(0x0D11) +#define LCD_DATA2 _SFR_MEM8(0x0D12) +#define LCD_DATA3 _SFR_MEM8(0x0D13) +#define LCD_DATA4 _SFR_MEM8(0x0D14) +#define LCD_DATA5 _SFR_MEM8(0x0D15) +#define LCD_DATA6 _SFR_MEM8(0x0D16) +#define LCD_DATA7 _SFR_MEM8(0x0D17) +#define LCD_DATA8 _SFR_MEM8(0x0D18) +#define LCD_DATA9 _SFR_MEM8(0x0D19) +#define LCD_DATA10 _SFR_MEM8(0x0D1A) +#define LCD_DATA11 _SFR_MEM8(0x0D1B) +#define LCD_DATA12 _SFR_MEM8(0x0D1C) +#define LCD_DATA13 _SFR_MEM8(0x0D1D) +#define LCD_DATA14 _SFR_MEM8(0x0D1E) +#define LCD_DATA15 _SFR_MEM8(0x0D1F) +#define LCD_DATA16 _SFR_MEM8(0x0D20) +#define LCD_DATA17 _SFR_MEM8(0x0D21) +#define LCD_DATA18 _SFR_MEM8(0x0D22) +#define LCD_DATA19 _SFR_MEM8(0x0D23) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* PR - Power Reduction */ +/* PR.PRGEN bit masks and bit positions */ +#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ +#define PR_LCD_bp 7 /* LCD Module bit position. */ + +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPB bit masks and bit positions */ +/* PR_ADC Predefined. */ +/* PR_ADC Predefined. */ + +/* PR_AC Predefined. */ +/* PR_AC Predefined. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ +#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ +#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ +#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ +#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ +#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ + +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ +#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ + +/* AES - AES Module */ +/* AES.CTRL bit masks and bit positions */ +#define AES_START_bm 0x80 /* Start/Run bit mask. */ +#define AES_START_bp 7 /* Start/Run bit position. */ + +#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ + +#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +#define AES_RESET_bp 5 /* AES Software Reset bit position. */ + +#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ + +#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ + +/* AES.STATUS bit masks and bit positions */ +#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +#define AES_ERROR_bp 7 /* AES Error bit position. */ + +#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ + +/* AES.INTCTRL bit masks and bit positions */ +#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* DMA - DMA Controller */ +/* DMA_CH.CTRLA bit masks and bit positions */ +#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ +#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ + +#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ +#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ + +#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ + +/* DMA_CH.CTRLB bit masks and bit positions */ +#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ + +#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ + +#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ + +#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ + +#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ + +/* DMA_CH.ADDRCTRL bit masks and bit positions */ +#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ + +#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ + +#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ + +#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ + +/* DMA_CH.TRIGSRC bit masks and bit positions */ +#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* DMA.CTRL bit masks and bit positions */ +#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define DMA_ENABLE_bp 7 /* Enable bit position. */ + +#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define DMA_RESET_bp 6 /* Software Reset bit position. */ + +#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ +#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ + +#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ +#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ + +/* DMA.INTFLAGS bit masks and bit positions */ +#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ + +#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* DMA.STATUS bit masks and bit positions */ +#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ + +#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ + +#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ + +#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* LCD - LCD Controller */ +/* LCD.CTRLA bit masks and bit positions */ +#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ +#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ + +#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ +#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ + +#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ +#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ + +#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ +#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ + +#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ +#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ + +#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ +#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ + +#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ +#define LCD_SEGON_bp 1 /* Segments On bit position. */ + +#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ +#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ + +/* LCD.CTRLB bit masks and bit positions */ +#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ +#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ + +#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ +#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ +#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ +#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ +#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ +#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ +#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ +#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ + +#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ +#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ + +#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ +#define LCD_DUTY_gp 0 /* Duty Select group position. */ +#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ +#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ +#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ +#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ + +/* LCD.CTRLC bit masks and bit positions */ +#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ +#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ +#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ +#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ +#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ +#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ +#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ +#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ +#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ +#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ +#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ +#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ +#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ +#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ + +/* LCD.INTCTRL bit masks and bit positions */ +#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ +#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ +#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ +#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ +#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ +#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ +#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ +#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ +#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ +#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ +#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ +#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ + +#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ +#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* LCD.INTFLAG bit masks and bit positions */ +#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ +#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ + +/* LCD.CTRLD bit masks and bit positions */ +#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ +#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ + +#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ +#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ +#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ +#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ +#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ +#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ + +/* LCD.CTRLE bit masks and bit positions */ +#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ +#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ +#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ +#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ +#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ +#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ +#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ +#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ +#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ +#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ + +#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ +#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ +#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ +#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ +#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ +#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ +#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ +#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ +#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ +#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ + +/* LCD.CTRLF bit masks and bit positions */ +#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ +#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ +#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ +#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ +#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ +#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ +#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ +#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ +#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ +#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ +#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ +#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ +#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ +#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ + +/* LCD.CTRLG bit masks and bit positions */ +#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ +#define LCD_TDG_gp 6 /* Type of Digit group position. */ +#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ +#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ +#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ +#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ + +#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ +#define LCD_STSEG_gp 0 /* Start Segment group position. */ +#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ +#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ +#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ +#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ +#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ +#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ +#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ +#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ +#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ +#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ +#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ +#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ + +/* LCD.CTRLH bit masks and bit positions */ +#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ +#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ + +#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ +#define LCD_DCODE_gp 0 /* Display Code group position. */ +#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ +#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ +#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ +#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ +#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ +#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ +#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ +#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ +#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ +#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ +#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ +#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ +#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ +#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* DMA interrupt vectors */ +#define DMA_CH0_vect_num 6 +#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +#define DMA_CH1_vect_num 7 +#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 31 +#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 32 +#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ + +/* LCD interrupt vectors */ +#define LCD_INT_vect_num 35 +#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ + +/* AES interrupt vectors */ +#define AES_INT_vect_num 36 +#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 37 +#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ +#define NVM_SPM_vect_num 38 +#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 39 +#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 40 +#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ + +/* ACB interrupt vectors */ +#define ACB_AC0_vect_num 41 +#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ +#define ACB_AC1_vect_num 42 +#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ +#define ACB_ACW_vect_num 43 +#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ + +/* ADCB interrupt vectors */ +#define ADCB_CH0_vect_num 44 +#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 48 +#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 49 +#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ + +/* PORTG interrupt vectors */ +#define PORTG_INT0_vect_num 50 +#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ +#define PORTG_INT1_vect_num 51 +#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ + +/* PORTM interrupt vectors */ +#define PORTM_INT0_vect_num 52 +#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ +#define PORTM_INT1_vect_num 53 +#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (54 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x51 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_LCD_bm|PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_LCD +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPB */ +#define __AVR_HAVE_PRPB (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPB_ADC +#define __AVR_HAVE_PRPB_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64c3.h b/hardware/tools/avr/avr/include/avr/iox64c3.h new file mode 100644 index 0000000000000000000000000000000000000000..c6c1d683575306efa7c750cc7dedbb9471a68692 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64c3.h @@ -0,0 +1,6264 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64c3.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64C3_H_INCLUDED +#define _AVR_ATXMEGA64C3_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t USBCTRL; /* USB Control Register */ +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + +/* USB Prescaler Division Factor */ +typedef enum CLK_USBPSDIV_enum +{ + CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ + CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ + CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ + CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ + CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ + CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +} CLK_USBPSDIV_t; + +/* USB Clock Source */ +typedef enum CLK_USBSRC_enum +{ + CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ + CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ +} CLK_USBSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ + OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +USB - USB +-------------------------------------------------------------------------- +*/ + +/* USB Endpoint */ +typedef struct USB_EP_struct +{ + register8_t STATUS; /* Endpoint Status */ + register8_t CTRL; /* Endpoint Control */ + _WORDREGISTER(CNT); /* USB Endpoint Counter */ + _WORDREGISTER(DATAPTR); /* Data Pointer */ + _WORDREGISTER(AUXDATA); /* Auxiliary Data */ +} USB_EP_t; + + +/* Universal Serial Bus */ +typedef struct USB_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t FIFOWP; /* FIFO Write Pointer Register */ + register8_t FIFORP; /* FIFO Read Pointer Register */ + _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ + register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ + register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ + register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t reserved_0x20; + register8_t reserved_0x21; + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t CAL0; /* Calibration Byte 0 */ + register8_t CAL1; /* Calibration Byte 1 */ +} USB_t; + + +/* USB Endpoint Table */ +typedef struct USB_EP_TABLE_struct +{ + USB_EP_t EP0OUT; /* Endpoint 0 */ + USB_EP_t EP0IN; /* Endpoint 0 */ + USB_EP_t EP1OUT; /* Endpoint 1 */ + USB_EP_t EP1IN; /* Endpoint 1 */ + USB_EP_t EP2OUT; /* Endpoint 2 */ + USB_EP_t EP2IN; /* Endpoint 2 */ + USB_EP_t EP3OUT; /* Endpoint 3 */ + USB_EP_t EP3IN; /* Endpoint 3 */ + USB_EP_t EP4OUT; /* Endpoint 4 */ + USB_EP_t EP4IN; /* Endpoint 4 */ + USB_EP_t EP5OUT; /* Endpoint 5 */ + USB_EP_t EP5IN; /* Endpoint 5 */ + USB_EP_t EP6OUT; /* Endpoint 6 */ + USB_EP_t EP6IN; /* Endpoint 6 */ + USB_EP_t EP7OUT; /* Endpoint 7 */ + USB_EP_t EP7IN; /* Endpoint 7 */ + USB_EP_t EP8OUT; /* Endpoint 8 */ + USB_EP_t EP8IN; /* Endpoint 8 */ + USB_EP_t EP9OUT; /* Endpoint 9 */ + USB_EP_t EP9IN; /* Endpoint 9 */ + USB_EP_t EP10OUT; /* Endpoint 10 */ + USB_EP_t EP10IN; /* Endpoint 10 */ + USB_EP_t EP11OUT; /* Endpoint 11 */ + USB_EP_t EP11IN; /* Endpoint 11 */ + USB_EP_t EP12OUT; /* Endpoint 12 */ + USB_EP_t EP12IN; /* Endpoint 12 */ + USB_EP_t EP13OUT; /* Endpoint 13 */ + USB_EP_t EP13IN; /* Endpoint 13 */ + USB_EP_t EP14OUT; /* Endpoint 14 */ + USB_EP_t EP14IN; /* Endpoint 14 */ + USB_EP_t EP15OUT; /* Endpoint 15 */ + USB_EP_t EP15IN; /* Endpoint 15 */ + register8_t reserved_0x100; + register8_t reserved_0x101; + register8_t reserved_0x102; + register8_t reserved_0x103; + register8_t reserved_0x104; + register8_t reserved_0x105; + register8_t reserved_0x106; + register8_t reserved_0x107; + register8_t reserved_0x108; + register8_t reserved_0x109; + register8_t reserved_0x10A; + register8_t reserved_0x10B; + register8_t reserved_0x10C; + register8_t reserved_0x10D; + register8_t reserved_0x10E; + register8_t reserved_0x10F; + register8_t FRAMENUML; /* Frame Number Low Byte */ + register8_t FRAMENUMH; /* Frame Number High Byte */ +} USB_EP_TABLE_t; + +/* Interrupt level */ +typedef enum USB_INTLVL_enum +{ + USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ + USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + USB_INTLVL_HI_gc = (0x03<<0), /* High level */ +} USB_INTLVL_t; + +/* USB Endpoint Type */ +typedef enum USB_EP_TYPE_enum +{ + USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ + USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ + USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ + USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +} USB_EP_TYPE_t; + +/* USB Endpoint Buffersize */ +typedef enum USB_EP_BUFSIZE_enum +{ + USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ + USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ + USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ + USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ + USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ + USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ + USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ + USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ +} USB_EP_BUFSIZE_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t USBCAL0; /* USB Calibration Byte 0 */ + register8_t USBCAL1; /* USB Calibration Byte 1 */ + register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ + register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ +#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ +#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) +#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) +#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) +#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) +#define CLK_USBCTRL _SFR_MEM8(0x0044) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* USB - Universal Serial Bus */ +#define USB_CTRLA _SFR_MEM8(0x04C0) +#define USB_CTRLB _SFR_MEM8(0x04C1) +#define USB_STATUS _SFR_MEM8(0x04C2) +#define USB_ADDR _SFR_MEM8(0x04C3) +#define USB_FIFOWP _SFR_MEM8(0x04C4) +#define USB_FIFORP _SFR_MEM8(0x04C5) +#define USB_EPPTR _SFR_MEM16(0x04C6) +#define USB_INTCTRLA _SFR_MEM8(0x04C8) +#define USB_INTCTRLB _SFR_MEM8(0x04C9) +#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +#define USB_CAL0 _SFR_MEM8(0x04FA) +#define USB_CAL1 _SFR_MEM8(0x04FB) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_REMAP _SFR_MEM8(0x06AE) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCE2_CTRLA _SFR_MEM8(0x0A00) +#define TCE2_CTRLB _SFR_MEM8(0x0A01) +#define TCE2_CTRLC _SFR_MEM8(0x0A02) +#define TCE2_CTRLE _SFR_MEM8(0x0A04) +#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE2_CTRLF _SFR_MEM8(0x0A09) +#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE2_LCNT _SFR_MEM8(0x0A20) +#define TCE2_HCNT _SFR_MEM8(0x0A21) +#define TCE2_LPER _SFR_MEM8(0x0A26) +#define TCE2_HPER _SFR_MEM8(0x0A27) +#define TCE2_LCMPA _SFR_MEM8(0x0A28) +#define TCE2_HCMPA _SFR_MEM8(0x0A29) +#define TCE2_LCMPB _SFR_MEM8(0x0A2A) +#define TCE2_HCMPB _SFR_MEM8(0x0A2B) +#define TCE2_LCMPC _SFR_MEM8(0x0A2C) +#define TCE2_HCMPC _SFR_MEM8(0x0A2D) +#define TCE2_LCMPD _SFR_MEM8(0x0A2E) +#define TCE2_HCMPD _SFR_MEM8(0x0A2F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCF2_CTRLA _SFR_MEM8(0x0B00) +#define TCF2_CTRLB _SFR_MEM8(0x0B01) +#define TCF2_CTRLC _SFR_MEM8(0x0B02) +#define TCF2_CTRLE _SFR_MEM8(0x0B04) +#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF2_CTRLF _SFR_MEM8(0x0B09) +#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF2_LCNT _SFR_MEM8(0x0B20) +#define TCF2_HCNT _SFR_MEM8(0x0B21) +#define TCF2_LPER _SFR_MEM8(0x0B26) +#define TCF2_HPER _SFR_MEM8(0x0B27) +#define TCF2_LCMPA _SFR_MEM8(0x0B28) +#define TCF2_HCMPA _SFR_MEM8(0x0B29) +#define TCF2_LCMPB _SFR_MEM8(0x0B2A) +#define TCF2_HCMPB _SFR_MEM8(0x0B2B) +#define TCF2_LCMPC _SFR_MEM8(0x0B2C) +#define TCF2_HCMPC _SFR_MEM8(0x0B2D) +#define TCF2_LCMPD _SFR_MEM8(0x0B2E) +#define TCF2_HCMPD _SFR_MEM8(0x0B2F) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* CLK.USBCTRL bit masks and bit positions */ +#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ + +#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ + +#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_USB_bm 0x40 /* USB bit mask. */ +#define PR_USB_bp 6 /* USB bit position. */ + +#define PR_AES_bm 0x10 /* AES bit mask. */ +#define PR_AES_bp 4 /* AES bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +#define PR_DMA_bp 0 /* DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +#define PR_USART1_bp 5 /* Port C USART1 bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* USB - USB */ +/* USB_EP.STATUS bit masks and bit positions */ +#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ +#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ + +#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ +#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ + +#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ +#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ + +#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ +#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ + +#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ +#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ + +#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ +#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ + +#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ + +#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ + +#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ + +#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ + +#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ + +/* USB_EP.CTRL bit masks and bit positions */ +#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ + +#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ + +#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ + +#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ + +#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ +#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ + +#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ +#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ +#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ +#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ +#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ +#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ +#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ +#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ + +/* USB_EP.CNT bit masks and bit positions */ +#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ +#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ + +/* USB.CTRLA bit masks and bit positions */ +#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +#define USB_ENABLE_bp 7 /* USB Enable bit position. */ + +#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +#define USB_SPEED_bp 6 /* Speed Select bit position. */ + +#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ + +#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ + +#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ + +/* USB.CTRLB bit masks and bit positions */ +#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ + +#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ + +#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +#define USB_GNACK_bp 1 /* Global NACK bit position. */ + +#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +#define USB_ATTACH_bp 0 /* Attach bit position. */ + +/* USB.STATUS bit masks and bit positions */ +#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ + +#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +#define USB_RESUME_bp 2 /* Resume bit position. */ + +#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ + +#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ + +/* USB.ADDR bit masks and bit positions */ +#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +#define USB_ADDR_gp 0 /* Device Address group position. */ +#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ + +/* USB.FIFOWP bit masks and bit positions */ +#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ + +/* USB.FIFORP bit masks and bit positions */ +#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ + +/* USB.INTCTRLA bit masks and bit positions */ +#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ + +#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ + +#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ + +#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ + +#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* USB.INTCTRLB bit masks and bit positions */ +#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ + +#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ + +/* USB.INTFLAGSACLR bit masks and bit positions */ +#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ + +#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ + +#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ + +#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ + +#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ + +#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ + +#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ + +#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ + +/* USB.INTFLAGSASET bit masks and bit positions */ +/* USB_SOFIF Predefined. */ +/* USB_SOFIF Predefined. */ + +/* USB_SUSPENDIF Predefined. */ +/* USB_SUSPENDIF Predefined. */ + +/* USB_RESUMEIF Predefined. */ +/* USB_RESUMEIF Predefined. */ + +/* USB_RSTIF Predefined. */ +/* USB_RSTIF Predefined. */ + +/* USB_CRCIF Predefined. */ +/* USB_CRCIF Predefined. */ + +/* USB_UNFIF Predefined. */ +/* USB_UNFIF Predefined. */ + +/* USB_OVFIF Predefined. */ +/* USB_OVFIF Predefined. */ + +/* USB_STALLIF Predefined. */ +/* USB_STALLIF Predefined. */ + +/* USB.INTFLAGSBCLR bit masks and bit positions */ +#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ + +#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ + +/* USB.INTFLAGSBSET bit masks and bit positions */ +/* USB_TRNIF Predefined. */ +/* USB_TRNIF Predefined. */ + +/* USB_SETUPIF Predefined. */ +/* USB_SETUPIF Predefined. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LUNF_vect_num 47 +#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_HUNF_vect_num 48 +#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPA_vect_num 49 +#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPB_vect_num 50 +#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPC_vect_num 51 +#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* TCE2 interrupt vectors */ +#define TCE2_LCMPD_vect_num 52 +#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LUNF_vect_num 108 +#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_HUNF_vect_num 109 +#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPA_vect_num 110 +#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPB_vect_num 111 +#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPC_vect_num 112 +#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ + +/* TCF0 interrupt vectors */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + +/* TCF2 interrupt vectors */ +#define TCF2_LCMPD_vect_num 113 +#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ + +/* USB interrupt vectors */ +#define USB_BUSEVENT_vect_num 125 +#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ +#define USB_TRNCOMPL_vect_num 126 +#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (127 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xE000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x49 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_USB_bm|PR_AES_bm|PR_RTC_bm|PR_EVSYS_bm|PR_DMA_bm) +#define __AVR_HAVE_PRGEN_USB +#define __AVR_HAVE_PRGEN_AES +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_DMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART1_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART1 +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64d3.h b/hardware/tools/avr/avr/include/avr/iox64d3.h new file mode 100644 index 0000000000000000000000000000000000000000..5c3ff34f5a877b034cf86f4dbd14aebba14c184b --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64d3.h @@ -0,0 +1,5764 @@ +/* Copyright (c) 2009-2010 Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ + +/* avr/iox64d3.h - definitions for ATxmega64D3 */ + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64d3.h" +#else +# error "Attempt to include more than one file." +#endif + + +#ifndef _AVR_ATxmega64D3_H_ +#define _AVR_ATxmega64D3_H_ 1 + + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ +} CLK_t; + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) + + +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control REgister */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ + WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ + WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t JTAGUID; /* JTAG User ID */ + register8_t reserved_0x05; + register8_t MCUCR; /* MCU Control */ + register8_t reserved_0x07; + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ + EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ + EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ + EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ + EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ + EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ + EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ + EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ + EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ + EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ + EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits */ +} NVM_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCKBITS; /* Lock Bits */ +} NVM_LOCKBITS_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t FUSEBYTE0; /* User ID */ + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ + register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ + register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ + register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ + register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ + register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; +} NVM_PROD_SIGNATURES_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +} NVM_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brown Out Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Comparator 0 Control */ + register8_t AC1CTRL; /* Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t reserved_0x6; + register8_t reserved_0x7; +} ADC_CH_t; + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +} ADC_REFSEL_t; + +/* Channel sweep selection */ +typedef enum ADC_SWEEP_enum +{ + ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +} ADC_SWEEP_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ + ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ + ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ + ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ + ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ + ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ + ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* EBI Chip Select Module */ +typedef struct EBI_CS_struct +{ + register8_t CTRLA; /* Chip Select Control Register A */ + register8_t CTRLB; /* Chip Select Control Register B */ + _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +} EBI_CS_t; + +/* +-------------------------------------------------------------------------- +EBI - External Bus Interface +-------------------------------------------------------------------------- +*/ + +/* External Bus Interface */ +typedef struct EBI_struct +{ + register8_t CTRL; /* Control */ + register8_t SDRAMCTRLA; /* SDRAM Control Register A */ + register8_t reserved_0x02; + register8_t reserved_0x03; + _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ + _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ + register8_t SDRAMCTRLB; /* SDRAM Control Register B */ + register8_t SDRAMCTRLC; /* SDRAM Control Register C */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EBI_CS_t CS0; /* Chip Select 0 */ + EBI_CS_t CS1; /* Chip Select 1 */ + EBI_CS_t CS2; /* Chip Select 2 */ + EBI_CS_t CS3; /* Chip Select 3 */ +} EBI_t; + +/* Chip Select adress space */ +typedef enum EBI_CS_ASIZE_enum +{ + EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ + EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ + EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ + EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ + EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ + EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ + EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ + EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ + EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ + EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ + EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ + EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ + EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ + EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ + EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ + EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ + EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +} EBI_CS_ASIZE_t; + +/* */ +typedef enum EBI_CS_SRWS_enum +{ + EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_CS_SRWS_t; + +/* Chip Select address mode */ +typedef enum EBI_CS_MODE_enum +{ + EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ + EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ + EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ + EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +} EBI_CS_MODE_t; + +/* Chip Select SDRAM mode */ +typedef enum EBI_CS_SDMODE_enum +{ + EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ + EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +} EBI_CS_SDMODE_t; + +/* */ +typedef enum EBI_SDDATAW_enum +{ + EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ + EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +} EBI_SDDATAW_t; + +/* */ +typedef enum EBI_LPCMODE_enum +{ + EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ + EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +} EBI_LPCMODE_t; + +/* */ +typedef enum EBI_SRMODE_enum +{ + EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ + EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ + EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ + EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +} EBI_SRMODE_t; + +/* */ +typedef enum EBI_IFMODE_enum +{ + EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ + EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ + EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ + EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +} EBI_IFMODE_t; + +/* */ +typedef enum EBI_SDCOL_enum +{ + EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ + EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ + EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ + EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +} EBI_SDCOL_t; + +/* */ +typedef enum EBI_MRDLY_enum +{ + EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_MRDLY_t; + +/* */ +typedef enum EBI_ROWCYCDLY_enum +{ + EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ROWCYCDLY_t; + +/* */ +typedef enum EBI_RPDLY_enum +{ + EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_RPDLY_t; + +/* */ +typedef enum EBI_WRDLY_enum +{ + EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ + EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ + EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ + EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +} EBI_WRDLY_t; + +/* */ +typedef enum EBI_ESRDLY_enum +{ + EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ + EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ + EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ + EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ + EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ + EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ + EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ + EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +} EBI_ESRDLY_t; + +/* */ +typedef enum EBI_ROWCOLDLY_enum +{ + EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ + EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ + EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ + EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ + EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ + EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ + EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ + EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +} EBI_ROWCOLDLY_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ +} PORTCFG_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Virtual Port 0 Mapping */ +typedef enum PORTCFG_VP0MAP_enum +{ + PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP0MAP_t; + +/* Virtual Port 1 Mapping */ +typedef enum PORTCFG_VP1MAP_enum +{ + PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP1MAP_t; + +/* Virtual Port 2 Mapping */ +typedef enum PORTCFG_VP2MAP_enum +{ + PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP2MAP_t; + +/* Virtual Port 3 Mapping */ +typedef enum PORTCFG_VP3MAP_enum +{ + PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP3MAP_t; + +/* Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x05; + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ + register8_t CTRL; /* Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +#define GPIO_GPIORA _SFR_MEM8(0x000A) +#define GPIO_GPIORB _SFR_MEM8(0x000B) +#define GPIO_GPIORC _SFR_MEM8(0x000C) +#define GPIO_GPIORD _SFR_MEM8(0x000D) +#define GPIO_GPIORE _SFR_MEM8(0x000E) +#define GPIO_GPIORF _SFR_MEM8(0x000F) + +/* VPORT0 - Virtual Port 0 */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT1 - Virtual Port 1 */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT2 - Virtual Port 2 */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT3 - Virtual Port 3 */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU Registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator Control */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset Controller */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_JTAGUID _SFR_MEM8(0x0094) +#define MCU_MCUCR _SFR_MEM8(0x0096) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - Port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non Volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADCA - Analog to Digital Converter A */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) + +/* DACB - Digital to Analog Converter B */ + +/* ACA - Analog Comparator A */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* ACB - Analog Comparator B */ +#define ACB_AC0CTRL _SFR_MEM8(0x0390) +#define ACB_AC1CTRL _SFR_MEM8(0x0391) +#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +#define ACB_CTRLA _SFR_MEM8(0x0394) +#define ACB_CTRLB _SFR_MEM8(0x0395) +#define ACB_WINCTRL _SFR_MEM8(0x0396) +#define ACB_STATUS _SFR_MEM8(0x0397) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWIC - Two-Wire Interface C */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWIE - Two-Wire Interface E */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORTA - Port A */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORTB - Port B */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORTC - Port C */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORTD - Port D */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORTE - Port E */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORTF - Port F */ +#define PORTF_DIR _SFR_MEM8(0x06A0) +#define PORTF_DIRSET _SFR_MEM8(0x06A1) +#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +#define PORTF_OUT _SFR_MEM8(0x06A4) +#define PORTF_OUTSET _SFR_MEM8(0x06A5) +#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +#define PORTF_IN _SFR_MEM8(0x06A8) +#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) + +/* PORTR - Port R */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TCC0 - Timer/Counter C0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TCC1 - Timer/Counter C1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEXC - Advanced Waveform Extension C */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRESC - High-Resolution Extension C */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPIC - Serial Peripheral Interface C */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_CTRL _SFR_MEM8(0x08FA) + +/* TCD0 - Timer/Counter D0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPID - Serial Peripheral Interface D */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TCE0 - Timer/Counter E0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + +/* AWEXE - Advanced Waveform Extension E */ +#define AWEXE_CTRL _SFR_MEM8(0x0A80) +#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +#define AWEXE_STATUS _SFR_MEM8(0x0A84) +#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +#define AWEXE_DTLS _SFR_MEM8(0x0A88) +#define AWEXE_DTHS _SFR_MEM8(0x0A89) +#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) + +/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +#define USARTE0_DATA _SFR_MEM8(0x0AA0) +#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) + +/* SPIE - Serial Peripheral Interface E */ +#define SPIE_CTRL _SFR_MEM8(0x0AC0) +#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +#define SPIE_STATUS _SFR_MEM8(0x0AC2) +#define SPIE_DATA _SFR_MEM8(0x0AC3) + +/* TCF0 - Timer/Counter F0 */ +#define TCF0_CTRLA _SFR_MEM8(0x0B00) +#define TCF0_CTRLB _SFR_MEM8(0x0B01) +#define TCF0_CTRLC _SFR_MEM8(0x0B02) +#define TCF0_CTRLD _SFR_MEM8(0x0B03) +#define TCF0_CTRLE _SFR_MEM8(0x0B04) +#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +#define TCF0_TEMP _SFR_MEM8(0x0B0F) +#define TCF0_CNT _SFR_MEM16(0x0B20) +#define TCF0_PER _SFR_MEM16(0x0B26) +#define TCF0_CCA _SFR_MEM16(0x0B28) +#define TCF0_CCB _SFR_MEM16(0x0B2A) +#define TCF0_CCC _SFR_MEM16(0x0B2C) +#define TCF0_CCD _SFR_MEM16(0x0B2E) +#define TCF0_PERBUF _SFR_MEM16(0x0B36) +#define TCF0_CCABUF _SFR_MEM16(0x0B38) +#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) + + + +/*================== Bitfield Definitions ================== */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR1 bit masks and bit positions */ +#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ + + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ + + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_SPI_bm Predefined. */ +/* PR_SPI_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI_bm Predefined. */ +/* PR_TWI_bp Predefined. */ + +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0_bm Predefined. */ +/* PR_USART0_bp Predefined. */ + +/* PR_TC0_bm Predefined. */ +/* PR_TC0_bp Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ + + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ + + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ + + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ + + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ + + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ + + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + + +/* MCU - MCU Control */ +/* MCU.MCUCR bit masks and bit positions */ +#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ + + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ + +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX_gm Predefined. */ +/* EVSYS_CHMUX_gp Predefined. */ +/* EVSYS_CHMUX0_bm Predefined. */ +/* EVSYS_CHMUX0_bp Predefined. */ +/* EVSYS_CHMUX1_bm Predefined. */ +/* EVSYS_CHMUX1_bp Predefined. */ +/* EVSYS_CHMUX2_bm Predefined. */ +/* EVSYS_CHMUX2_bp Predefined. */ +/* EVSYS_CHMUX3_bm Predefined. */ +/* EVSYS_CHMUX3_bp Predefined. */ +/* EVSYS_CHMUX4_bm Predefined. */ +/* EVSYS_CHMUX4_bp Predefined. */ +/* EVSYS_CHMUX5_bm Predefined. */ +/* EVSYS_CHMUX5_bp Predefined. */ +/* EVSYS_CHMUX6_bm Predefined. */ +/* EVSYS_CHMUX6_bp Predefined. */ +/* EVSYS_CHMUX7_bm Predefined. */ +/* EVSYS_CHMUX7_bp Predefined. */ + + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_QDIRM_gm Predefined. */ +/* EVSYS_QDIRM_gp Predefined. */ +/* EVSYS_QDIRM0_bm Predefined. */ +/* EVSYS_QDIRM0_bp Predefined. */ +/* EVSYS_QDIRM1_bm Predefined. */ +/* EVSYS_QDIRM1_bp Predefined. */ + +/* EVSYS_QDIEN_bm Predefined. */ +/* EVSYS_QDIEN_bp Predefined. */ + +/* EVSYS_QDEN_bm Predefined. */ +/* EVSYS_QDEN_bp Predefined. */ + +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT_gm Predefined. */ +/* EVSYS_DIGFILT_gp Predefined. */ +/* EVSYS_DIGFILT0_bm Predefined. */ +/* EVSYS_DIGFILT0_bp Predefined. */ +/* EVSYS_DIGFILT1_bm Predefined. */ +/* EVSYS_DIGFILT1_bp Predefined. */ +/* EVSYS_DIGFILT2_bm Predefined. */ +/* EVSYS_DIGFILT2_bp Predefined. */ + + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0xFF /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +#define NVM_CMD7_bp 7 /* Command bit 7 position. */ + + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ + + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ + +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ + + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE_gm Predefined. */ +/* AC_INTMODE_gp Predefined. */ +/* AC_INTMODE0_bm Predefined. */ +/* AC_INTMODE0_bp Predefined. */ +/* AC_INTMODE1_bm Predefined. */ +/* AC_INTMODE1_bp Predefined. */ + +/* AC_INTLVL_gm Predefined. */ +/* AC_INTLVL_gp Predefined. */ +/* AC_INTLVL0_bm Predefined. */ +/* AC_INTLVL0_bp Predefined. */ +/* AC_INTLVL1_bm Predefined. */ +/* AC_INTLVL1_bp Predefined. */ + +/* AC_HSMODE_bm Predefined. */ +/* AC_HSMODE_bp Predefined. */ + +/* AC_HYSMODE_gm Predefined. */ +/* AC_HYSMODE_gp Predefined. */ +/* AC_HYSMODE0_bm Predefined. */ +/* AC_HYSMODE0_bp Predefined. */ +/* AC_HYSMODE1_bm Predefined. */ +/* AC_HYSMODE1_bp Predefined. */ + +/* AC_ENABLE_bm Predefined. */ +/* AC_ENABLE_bp Predefined. */ + + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS_gm Predefined. */ +/* AC_MUXPOS_gp Predefined. */ +/* AC_MUXPOS0_bm Predefined. */ +/* AC_MUXPOS0_bp Predefined. */ +/* AC_MUXPOS1_bm Predefined. */ +/* AC_MUXPOS1_bp Predefined. */ +/* AC_MUXPOS2_bm Predefined. */ +/* AC_MUXPOS2_bp Predefined. */ + +/* AC_MUXNEG_gm Predefined. */ +/* AC_MUXNEG_gp Predefined. */ +/* AC_MUXNEG0_bm Predefined. */ +/* AC_MUXNEG0_bp Predefined. */ +/* AC_MUXNEG1_bm Predefined. */ +/* AC_MUXNEG1_bp Predefined. */ +/* AC_MUXNEG2_bm Predefined. */ +/* AC_MUXNEG2_bp Predefined. */ + + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ + + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ + + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ + + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ + +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* EBI - External Bus Interface */ +/* EBI_CS.CTRLA bit masks and bit positions */ +#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ + +#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ + + +/* EBI_CS.CTRLB bit masks and bit positions */ +#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ + +#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ + +#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ + +#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ + + +/* EBI.CTRL bit masks and bit positions */ +#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ + +#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ + +#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ + +#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ + + +/* EBI.SDRAMCTRLA bit masks and bit positions */ +#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ + +#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ + +#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ + + +/* EBI.SDRAMCTRLB bit masks and bit positions */ +#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ + +#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ + +#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ + + +/* EBI.SDRAMCTRLC bit masks and bit positions */ +#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ + +#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ + +#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ + + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + + +/* PORT - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + + +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN_bm Predefined. */ +/* PORT_SRLEN_bp Predefined. */ + +/* PORT_INVEN_bm Predefined. */ +/* PORT_INVEN_bp Predefined. */ + +/* PORT_OPC_gm Predefined. */ +/* PORT_OPC_gp Predefined. */ +/* PORT_OPC0_bm Predefined. */ +/* PORT_OPC0_bp Predefined. */ +/* PORT_OPC1_bm Predefined. */ +/* PORT_OPC1_bp Predefined. */ +/* PORT_OPC2_bm Predefined. */ +/* PORT_OPC2_bp Predefined. */ + +/* PORT_ISC_gm Predefined. */ +/* PORT_ISC_gp Predefined. */ +/* PORT_ISC0_bm Predefined. */ +/* PORT_ISC0_bp Predefined. */ +/* PORT_ISC1_bm Predefined. */ +/* PORT_ISC1_bp Predefined. */ +/* PORT_ISC2_bm Predefined. */ +/* PORT_ISC2_bp Predefined. */ + + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD_gm Predefined. */ +/* TC0_CMD_gp Predefined. */ +/* TC0_CMD0_bm Predefined. */ +/* TC0_CMD0_bp Predefined. */ +/* TC0_CMD1_bm Predefined. */ +/* TC0_CMD1_bp Predefined. */ + +/* TC0_LUPD_bm Predefined. */ +/* TC0_LUPD_bp Predefined. */ + +/* TC0_DIR_bm Predefined. */ +/* TC0_DIR_bp Predefined. */ + + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV_bm Predefined. */ +/* TC0_CCDBV_bp Predefined. */ + +/* TC0_CCCBV_bm Predefined. */ +/* TC0_CCCBV_bp Predefined. */ + +/* TC0_CCBBV_bm Predefined. */ +/* TC0_CCBBV_bp Predefined. */ + +/* TC0_CCABV_bm Predefined. */ +/* TC0_CCABV_bp Predefined. */ + +/* TC0_PERBV_bm Predefined. */ +/* TC0_PERBV_bp Predefined. */ + + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD_gm Predefined. */ +/* TC1_CMD_gp Predefined. */ +/* TC1_CMD0_bm Predefined. */ +/* TC1_CMD0_bp Predefined. */ +/* TC1_CMD1_bm Predefined. */ +/* TC1_CMD1_bp Predefined. */ + +/* TC1_LUPD_bm Predefined. */ +/* TC1_LUPD_bp Predefined. */ + +/* TC1_DIR_bm Predefined. */ +/* TC1_DIR_bp Predefined. */ + + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV_bm Predefined. */ +/* TC1_CCBBV_bp Predefined. */ + +/* TC1_CCABV_bm Predefined. */ +/* TC1_CCABV_bp Predefined. */ + +/* TC1_PERBV_bm Predefined. */ +/* TC1_PERBV_bp Predefined. */ + + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + + +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + + +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL_gm Predefined. */ +/* USART_BSEL_gp Predefined. */ +/* USART_BSEL0_bm Predefined. */ +/* USART_BSEL0_bp Predefined. */ +/* USART_BSEL1_bm Predefined. */ +/* USART_BSEL1_bp Predefined. */ +/* USART_BSEL2_bm Predefined. */ +/* USART_BSEL2_bp Predefined. */ +/* USART_BSEL3_bm Predefined. */ +/* USART_BSEL3_bp Predefined. */ + + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_XOSCF_vect_num 1 +#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +/* PORTF interrupt vectors */ +#define PORTF_INT0_vect_num 104 +#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +#define PORTF_INT1_vect_num 105 +#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ + +/* TCF0 interrupt vectors */ +#define TCF0_OVF_vect_num 108 +#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +#define TCF0_ERR_vect_num 109 +#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +#define TCF0_CCA_vect_num 110 +#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +#define TCF0_CCB_vect_num 111 +#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +#define TCF0_CCC_vect_num 112 +#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +#define TCF0_CCD_vect_num 113 +#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ + + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (114 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_PAGE_SIZE (256) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x0F000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_PAGE_SIZE (0) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define FUSE_START (0x0000) +#define FUSE_SIZE (6) +#define FUSE_PAGE_SIZE (0) +#define FUSE_END (FUSE_START + FUSE_SIZE - 1) + +#define LOCKBIT_START (0x0000) +#define LOCKBIT_SIZE (1) +#define LOCKBIT_PAGE_SIZE (0) +#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (0) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (52) +#define PROD_SIGNATURES_PAGE_SIZE (0) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define XRAMSTART EXTERNAL_SRAM_START +#define XRAMSIZE EXTERNAL_SRAM_SIZE +#define XRAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 */ +#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +#define FUSE0_DEFAULT (0xFF) + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x4A + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* _AVR_ATxmega64D3_H_ */ + diff --git a/hardware/tools/avr/avr/include/avr/iox64d4.h b/hardware/tools/avr/avr/include/avr/iox64d4.h new file mode 100644 index 0000000000000000000000000000000000000000..26c9d5e669e3a8205e85ed24e6eee98a155a82a1 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox64d4.h @@ -0,0 +1,5555 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox64d4.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA64D4_H_INCLUDED +#define _AVR_ATXMEGA64D4_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t PRPE; /* Power Reduction Port E */ + register8_t PRPF; /* Power Reduction Port F */ +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 2 MHz DFLL Calibration Reference */ +typedef enum OSC_RC2MCREF_enum +{ + OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC2MCREF_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t AWEXLOCK; /* AWEX Lock */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t VPCTRLA; /* Virtual Port Control Register A */ + register8_t VPCTRLB; /* Virtual Port Control Register B */ + register8_t CLKEVOUT; /* Clock and Event Out Register */ + register8_t reserved_0x05; + register8_t EVOUTSEL; /* Event Output Select */ +} PORTCFG_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP02MAP_enum +{ + PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ + PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ + PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ + PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ + PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ + PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ + PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ + PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ + PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ + PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ + PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ + PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ + PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ + PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ + PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ + PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +} PORTCFG_VP02MAP_t; + +/* Virtual Port Mapping */ +typedef enum PORTCFG_VP13MAP_enum +{ + PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ + PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ + PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ + PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ + PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ + PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ + PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ + PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ + PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ + PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ + PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ + PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ + PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ + PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ + PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ + PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +} PORTCFG_VP13MAP_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +} PORTCFG_CLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ + PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ +} EVSYS_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ + EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ + EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ + EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ + EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ + EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ + EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ + EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ + EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ + EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ + EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ + EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ + EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ + EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ + EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ + EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ + EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ + EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ + EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ + EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ + EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ + EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ + EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ + EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ + EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ + EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ + EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ + EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ + EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ + EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ + EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ + EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ + EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ + EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ + EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ + EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ + EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ + EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ + EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ + EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ + EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ + EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ + EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ + EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ + EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ + EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ + EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ + EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ + EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ + EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +} EVSYS_CHMUX_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t reserved_0x07; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +} ADC_CH_MUXNEG_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +} ADC_CH_INPUTMODE_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Counter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + + +/* +-------------------------------------------------------------------------- +PORT - I/O Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INT0MASK; /* Port Interrupt 0 Mask */ + register8_t INT1MASK; /* Port Interrupt 1 Mask */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* I/O Port Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt 0 Level */ +typedef enum PORT_INT0LVL_enum +{ + PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INT0LVL_t; + +/* Port Interrupt 1 Level */ +typedef enum PORT_INT1LVL_enum +{ + PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ + PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ + PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +} PORT_INT1LVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 0 */ +typedef struct TC0_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC0_t; + + +/* 16-bit Timer/Counter 1 */ +typedef struct TC1_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLFCLR; /* Control Register F Clear */ + register8_t CTRLFSET; /* Control Register F Set */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +} TC1_t; + +/* Clock Selection */ +typedef enum TC_CLKSEL_enum +{ + TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_CLKSEL_t; + +/* Waveform Generation Mode */ +typedef enum TC_WGMODE_enum +{ + TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ + TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ + TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ + TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC_WGMODE_t; + +/* Byte Mode */ +typedef enum TC_BYTEM_enum +{ + TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ + TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ +} TC_BYTEM_t; + +/* Event Action */ +typedef enum TC_EVACT_enum +{ + TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ + TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ + TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ + TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ + TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ + TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +} TC_EVACT_t; + +/* Event Selection */ +typedef enum TC_EVSEL_enum +{ + TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC_EVSEL_t; + +/* Error Interrupt Level */ +typedef enum TC_ERRINTLVL_enum +{ + TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC_OVFINTLVL_enum +{ + TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_OVFINTLVL_t; + +/* Compare or Capture D Interrupt Level */ +typedef enum TC_CCDINTLVL_enum +{ + TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC_CCDINTLVL_t; + +/* Compare or Capture C Interrupt Level */ +typedef enum TC_CCCINTLVL_enum +{ + TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC_CCCINTLVL_t; + +/* Compare or Capture B Interrupt Level */ +typedef enum TC_CCBINTLVL_enum +{ + TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC_CCBINTLVL_t; + +/* Compare or Capture A Interrupt Level */ +typedef enum TC_CCAINTLVL_enum +{ + TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC_CCAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC_CMD_enum +{ + TC_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC_CMD_t; + + +/* +-------------------------------------------------------------------------- +TC2 - 16-bit Timer/Counter type 2 +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter type 2 */ +typedef struct TC2_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t reserved_0x03; + register8_t CTRLE; /* Control Register E */ + register8_t reserved_0x05; + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t reserved_0x08; + register8_t CTRLF; /* Control Register F */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t LCNT; /* Low Byte Count */ + register8_t HCNT; /* High Byte Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t LPER; /* Low Byte Period */ + register8_t HPER; /* High Byte Period */ + register8_t LCMPA; /* Low Byte Compare A */ + register8_t HCMPA; /* High Byte Compare A */ + register8_t LCMPB; /* Low Byte Compare B */ + register8_t HCMPB; /* High Byte Compare B */ + register8_t LCMPC; /* Low Byte Compare C */ + register8_t HCMPC; /* High Byte Compare C */ + register8_t LCMPD; /* Low Byte Compare D */ + register8_t HCMPD; /* High Byte Compare D */ +} TC2_t; + +/* Clock Selection */ +typedef enum TC2_CLKSEL_enum +{ + TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +} TC2_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC2_BYTEM_enum +{ + TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ + TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ + TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ +} TC2_BYTEM_t; + +/* High Byte Underflow Interrupt Level */ +typedef enum TC2_HUNFINTLVL_enum +{ + TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_HUNFINTLVL_t; + +/* Low Byte Underflow Interrupt Level */ +typedef enum TC2_LUNFINTLVL_enum +{ + TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LUNFINTLVL_t; + +/* Low Byte Compare D Interrupt Level */ +typedef enum TC2_LCMPDINTLVL_enum +{ + TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC2_LCMPDINTLVL_t; + +/* Low Byte Compare C Interrupt Level */ +typedef enum TC2_LCMPCINTLVL_enum +{ + TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC2_LCMPCINTLVL_t; + +/* Low Byte Compare B Interrupt Level */ +typedef enum TC2_LCMPBINTLVL_enum +{ + TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC2_LCMPBINTLVL_t; + +/* Low Byte Compare A Interrupt Level */ +typedef enum TC2_LCMPAINTLVL_enum +{ + TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC2_LCMPAINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMD_enum +{ + TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC2_CMD_t; + +/* Timer/Counter Command */ +typedef enum TC2_CMDEN_enum +{ + TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ + TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ + TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ +} TC2_CMDEN_t; + + +/* +-------------------------------------------------------------------------- +AWEX - Timer/Counter Advanced Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Advanced Waveform Extension */ +typedef struct AWEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t FDEMASK; /* Fault Detection Event Mask */ + register8_t FDCTRL; /* Fault Detection Control Register */ + register8_t STATUS; /* Status Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t DTBOTH; /* Dead Time Both Sides */ + register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ + register8_t DTLS; /* Dead Time Low Side */ + register8_t DTHS; /* Dead Time High Side */ + register8_t DTLSBUF; /* Dead Time Low Side Buffer */ + register8_t DTHSBUF; /* Dead Time High Side Buffer */ + register8_t OUTOVEN; /* Output Override Enable */ +} AWEX_t; + +/* Fault Detect Action */ +typedef enum AWEX_FDACT_enum +{ + AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ + AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ + AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +} AWEX_FDACT_t; + + +/* +-------------------------------------------------------------------------- +HIRES - Timer/Counter High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register */ +} HIRES_t; + +/* High Resolution Enable */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ + HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ + HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +} NVM_FUSES_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* Timer Oscillator pin location */ +typedef enum TOSCSEL_enum +{ + TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ + TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ +} TOSCSEL_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +} BOD_t; + +/* BOD operation */ +typedef enum BODACT_enum +{ + BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BODACT_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WDP_enum +{ + WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ + WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ + WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ + WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ + WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ + WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ + WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ + WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ + WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ + WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ + WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ +} WDP_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +LOCKBIT - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ + register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t reserved_0x28; + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ +#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ +#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ +#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ +#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ +#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ +#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* DFLL - DFLL */ +#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) +#define PR_PRPE _SFR_MEM8(0x0075) +#define PR_PRPF _SFR_MEM8(0x0076) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_AWEXLOCK _SFR_MEM8(0x0099) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) + +/* TWI - Two-Wire Interface */ +#define TWIE_CTRL _SFR_MEM8(0x04A0) +#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INT0MASK _SFR_MEM8(0x060A) +#define PORTA_INT1MASK _SFR_MEM8(0x060B) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTB_DIR _SFR_MEM8(0x0620) +#define PORTB_DIRSET _SFR_MEM8(0x0621) +#define PORTB_DIRCLR _SFR_MEM8(0x0622) +#define PORTB_DIRTGL _SFR_MEM8(0x0623) +#define PORTB_OUT _SFR_MEM8(0x0624) +#define PORTB_OUTSET _SFR_MEM8(0x0625) +#define PORTB_OUTCLR _SFR_MEM8(0x0626) +#define PORTB_OUTTGL _SFR_MEM8(0x0627) +#define PORTB_IN _SFR_MEM8(0x0628) +#define PORTB_INTCTRL _SFR_MEM8(0x0629) +#define PORTB_INT0MASK _SFR_MEM8(0x062A) +#define PORTB_INT1MASK _SFR_MEM8(0x062B) +#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +#define PORTB_REMAP _SFR_MEM8(0x062E) +#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INT0MASK _SFR_MEM8(0x064A) +#define PORTC_INT1MASK _SFR_MEM8(0x064B) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INT0MASK _SFR_MEM8(0x066A) +#define PORTD_INT1MASK _SFR_MEM8(0x066B) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTE_DIR _SFR_MEM8(0x0680) +#define PORTE_DIRSET _SFR_MEM8(0x0681) +#define PORTE_DIRCLR _SFR_MEM8(0x0682) +#define PORTE_DIRTGL _SFR_MEM8(0x0683) +#define PORTE_OUT _SFR_MEM8(0x0684) +#define PORTE_OUTSET _SFR_MEM8(0x0685) +#define PORTE_OUTCLR _SFR_MEM8(0x0686) +#define PORTE_OUTTGL _SFR_MEM8(0x0687) +#define PORTE_IN _SFR_MEM8(0x0688) +#define PORTE_INTCTRL _SFR_MEM8(0x0689) +#define PORTE_INT0MASK _SFR_MEM8(0x068A) +#define PORTE_INT1MASK _SFR_MEM8(0x068B) +#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +#define PORTE_REMAP _SFR_MEM8(0x068E) +#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCC0_CTRLA _SFR_MEM8(0x0800) +#define TCC0_CTRLB _SFR_MEM8(0x0801) +#define TCC0_CTRLC _SFR_MEM8(0x0802) +#define TCC0_CTRLD _SFR_MEM8(0x0803) +#define TCC0_CTRLE _SFR_MEM8(0x0804) +#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +#define TCC0_TEMP _SFR_MEM8(0x080F) +#define TCC0_CNT _SFR_MEM16(0x0820) +#define TCC0_PER _SFR_MEM16(0x0826) +#define TCC0_CCA _SFR_MEM16(0x0828) +#define TCC0_CCB _SFR_MEM16(0x082A) +#define TCC0_CCC _SFR_MEM16(0x082C) +#define TCC0_CCD _SFR_MEM16(0x082E) +#define TCC0_PERBUF _SFR_MEM16(0x0836) +#define TCC0_CCABUF _SFR_MEM16(0x0838) +#define TCC0_CCBBUF _SFR_MEM16(0x083A) +#define TCC0_CCCBUF _SFR_MEM16(0x083C) +#define TCC0_CCDBUF _SFR_MEM16(0x083E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCC2_CTRLA _SFR_MEM8(0x0800) +#define TCC2_CTRLB _SFR_MEM8(0x0801) +#define TCC2_CTRLC _SFR_MEM8(0x0802) +#define TCC2_CTRLE _SFR_MEM8(0x0804) +#define TCC2_INTCTRLA _SFR_MEM8(0x0806) +#define TCC2_INTCTRLB _SFR_MEM8(0x0807) +#define TCC2_CTRLF _SFR_MEM8(0x0809) +#define TCC2_INTFLAGS _SFR_MEM8(0x080C) +#define TCC2_LCNT _SFR_MEM8(0x0820) +#define TCC2_HCNT _SFR_MEM8(0x0821) +#define TCC2_LPER _SFR_MEM8(0x0826) +#define TCC2_HPER _SFR_MEM8(0x0827) +#define TCC2_LCMPA _SFR_MEM8(0x0828) +#define TCC2_HCMPA _SFR_MEM8(0x0829) +#define TCC2_LCMPB _SFR_MEM8(0x082A) +#define TCC2_HCMPB _SFR_MEM8(0x082B) +#define TCC2_LCMPC _SFR_MEM8(0x082C) +#define TCC2_HCMPC _SFR_MEM8(0x082D) +#define TCC2_LCMPD _SFR_MEM8(0x082E) +#define TCC2_HCMPD _SFR_MEM8(0x082F) + +/* TC1 - 16-bit Timer/Counter 1 */ +#define TCC1_CTRLA _SFR_MEM8(0x0840) +#define TCC1_CTRLB _SFR_MEM8(0x0841) +#define TCC1_CTRLC _SFR_MEM8(0x0842) +#define TCC1_CTRLD _SFR_MEM8(0x0843) +#define TCC1_CTRLE _SFR_MEM8(0x0844) +#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +#define TCC1_TEMP _SFR_MEM8(0x084F) +#define TCC1_CNT _SFR_MEM16(0x0860) +#define TCC1_PER _SFR_MEM16(0x0866) +#define TCC1_CCA _SFR_MEM16(0x0868) +#define TCC1_CCB _SFR_MEM16(0x086A) +#define TCC1_PERBUF _SFR_MEM16(0x0876) +#define TCC1_CCABUF _SFR_MEM16(0x0878) +#define TCC1_CCBBUF _SFR_MEM16(0x087A) + +/* AWEX - Advanced Waveform Extension */ +#define AWEXC_CTRL _SFR_MEM8(0x0880) +#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +#define AWEXC_STATUS _SFR_MEM8(0x0884) +#define AWEXC_STATUSSET _SFR_MEM8(0x0885) +#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +#define AWEXC_DTLS _SFR_MEM8(0x0888) +#define AWEXC_DTHS _SFR_MEM8(0x0889) +#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x0890) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08A0) +#define USARTC0_STATUS _SFR_MEM8(0x08A1) +#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) + +/* SPI - Serial Peripheral Interface */ +#define SPIC_CTRL _SFR_MEM8(0x08C0) +#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +#define SPIC_STATUS _SFR_MEM8(0x08C2) +#define SPIC_DATA _SFR_MEM8(0x08C3) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCD0_CTRLA _SFR_MEM8(0x0900) +#define TCD0_CTRLB _SFR_MEM8(0x0901) +#define TCD0_CTRLC _SFR_MEM8(0x0902) +#define TCD0_CTRLD _SFR_MEM8(0x0903) +#define TCD0_CTRLE _SFR_MEM8(0x0904) +#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +#define TCD0_TEMP _SFR_MEM8(0x090F) +#define TCD0_CNT _SFR_MEM16(0x0920) +#define TCD0_PER _SFR_MEM16(0x0926) +#define TCD0_CCA _SFR_MEM16(0x0928) +#define TCD0_CCB _SFR_MEM16(0x092A) +#define TCD0_CCC _SFR_MEM16(0x092C) +#define TCD0_CCD _SFR_MEM16(0x092E) +#define TCD0_PERBUF _SFR_MEM16(0x0936) +#define TCD0_CCABUF _SFR_MEM16(0x0938) +#define TCD0_CCBBUF _SFR_MEM16(0x093A) +#define TCD0_CCCBUF _SFR_MEM16(0x093C) +#define TCD0_CCDBUF _SFR_MEM16(0x093E) + +/* TC2 - 16-bit Timer/Counter type 2 */ +#define TCD2_CTRLA _SFR_MEM8(0x0900) +#define TCD2_CTRLB _SFR_MEM8(0x0901) +#define TCD2_CTRLC _SFR_MEM8(0x0902) +#define TCD2_CTRLE _SFR_MEM8(0x0904) +#define TCD2_INTCTRLA _SFR_MEM8(0x0906) +#define TCD2_INTCTRLB _SFR_MEM8(0x0907) +#define TCD2_CTRLF _SFR_MEM8(0x0909) +#define TCD2_INTFLAGS _SFR_MEM8(0x090C) +#define TCD2_LCNT _SFR_MEM8(0x0920) +#define TCD2_HCNT _SFR_MEM8(0x0921) +#define TCD2_LPER _SFR_MEM8(0x0926) +#define TCD2_HPER _SFR_MEM8(0x0927) +#define TCD2_LCMPA _SFR_MEM8(0x0928) +#define TCD2_HCMPA _SFR_MEM8(0x0929) +#define TCD2_LCMPB _SFR_MEM8(0x092A) +#define TCD2_HCMPB _SFR_MEM8(0x092B) +#define TCD2_LCMPC _SFR_MEM8(0x092C) +#define TCD2_HCMPC _SFR_MEM8(0x092D) +#define TCD2_LCMPD _SFR_MEM8(0x092E) +#define TCD2_HCMPD _SFR_MEM8(0x092F) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09A0) +#define USARTD0_STATUS _SFR_MEM8(0x09A1) +#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) + +/* SPI - Serial Peripheral Interface */ +#define SPID_CTRL _SFR_MEM8(0x09C0) +#define SPID_INTCTRL _SFR_MEM8(0x09C1) +#define SPID_STATUS _SFR_MEM8(0x09C2) +#define SPID_DATA _SFR_MEM8(0x09C3) + +/* TC0 - 16-bit Timer/Counter 0 */ +#define TCE0_CTRLA _SFR_MEM8(0x0A00) +#define TCE0_CTRLB _SFR_MEM8(0x0A01) +#define TCE0_CTRLC _SFR_MEM8(0x0A02) +#define TCE0_CTRLD _SFR_MEM8(0x0A03) +#define TCE0_CTRLE _SFR_MEM8(0x0A04) +#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +#define TCE0_TEMP _SFR_MEM8(0x0A0F) +#define TCE0_CNT _SFR_MEM16(0x0A20) +#define TCE0_PER _SFR_MEM16(0x0A26) +#define TCE0_CCA _SFR_MEM16(0x0A28) +#define TCE0_CCB _SFR_MEM16(0x0A2A) +#define TCE0_CCC _SFR_MEM16(0x0A2C) +#define TCE0_CCD _SFR_MEM16(0x0A2E) +#define TCE0_PERBUF _SFR_MEM16(0x0A36) +#define TCE0_CCABUF _SFR_MEM16(0x0A38) +#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ +#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ + +#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ + +#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_SPI Predefined. */ +/* PR_SPI Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPE bit masks and bit positions */ +/* PR_TWI Predefined. */ +/* PR_TWI Predefined. */ + +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* PR.PRPF bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC0 Predefined. */ +/* PR_TC0 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ +#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.AWEXLOCK bit masks and bit positions */ +#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.VPCTRLA bit masks and bit positions */ +#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ + +#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ + +/* PORTCFG.VPCTRLB bit masks and bit positions */ +#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ + +#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ + +/* PORTCFG.CLKEVOUT bit masks and bit positions */ +#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ + +#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ + +#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ + +/* PORTCFG.EVOUTSEL bit masks and bit positions */ +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ + +#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ + +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ +#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ +#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ +#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ +#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ +#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ +#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ +#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ +#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ +#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ + +#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ +#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ +#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ +#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ +#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ +#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ +#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ +#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ +#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ +#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* RTC - Real-Time Counter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TWI - Two-Wire Interface */ +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI.CTRL bit masks and bit positions */ +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* PORT - I/O Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ + +#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_SPI_bm 0x20 /* SPI bit mask. */ +#define PORT_SPI_bp 5 /* SPI bit position. */ + +#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ +#define PORT_USART0_bp 4 /* USART0 bit position. */ + +#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ +#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ + +#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ +#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ + +#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ +#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ + +#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ +#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ + +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_SRLEN Predefined. */ +/* PORT_SRLEN Predefined. */ + +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC0.CTRLA bit masks and bit positions */ +#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC0.CTRLB bit masks and bit positions */ +#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ + +#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ + +#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC0.CTRLC bit masks and bit positions */ +#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ + +#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ + +#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC0.CTRLD bit masks and bit positions */ +#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC0_EVACT_gp 5 /* Event Action group position. */ +#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC0.CTRLE bit masks and bit positions */ +#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC0.INTCTRLA bit masks and bit positions */ +#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC0.INTCTRLB bit masks and bit positions */ +#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ + +#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ + +#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC0.CTRLFCLR bit masks and bit positions */ +#define TC0_CMD_gm 0x0C /* Command group mask. */ +#define TC0_CMD_gp 2 /* Command group position. */ +#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC0_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC0_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +#define TC0_DIR_bp 0 /* Direction bit position. */ + +/* TC0.CTRLFSET bit masks and bit positions */ +/* TC0_CMD Predefined. */ +/* TC0_CMD Predefined. */ + +/* TC0_LUPD Predefined. */ +/* TC0_LUPD Predefined. */ + +/* TC0_DIR Predefined. */ +/* TC0_DIR Predefined. */ + +/* TC0.CTRLGCLR bit masks and bit positions */ +#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ + +#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ + +#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC0.CTRLGSET bit masks and bit positions */ +/* TC0_CCDBV Predefined. */ +/* TC0_CCDBV Predefined. */ + +/* TC0_CCCBV Predefined. */ +/* TC0_CCCBV Predefined. */ + +/* TC0_CCBBV Predefined. */ +/* TC0_CCBBV Predefined. */ + +/* TC0_CCABV Predefined. */ +/* TC0_CCABV Predefined. */ + +/* TC0_PERBV Predefined. */ +/* TC0_PERBV Predefined. */ + +/* TC0.INTFLAGS bit masks and bit positions */ +#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ + +#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ + +#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC1.CTRLA bit masks and bit positions */ +#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC1.CTRLB bit masks and bit positions */ +#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ + +#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ + +#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ + +/* TC1.CTRLC bit masks and bit positions */ +#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ + +#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ + +/* TC1.CTRLD bit masks and bit positions */ +#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC1_EVACT_gp 5 /* Event Action group position. */ +#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC1.CTRLE bit masks and bit positions */ +#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ + +/* TC1.INTCTRLA bit masks and bit positions */ +#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ + +#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ + +/* TC1.INTCTRLB bit masks and bit positions */ +#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ + +#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ + +/* TC1.CTRLFCLR bit masks and bit positions */ +#define TC1_CMD_gm 0x0C /* Command group mask. */ +#define TC1_CMD_gp 2 /* Command group position. */ +#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC1_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC1_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +#define TC1_DIR_bp 0 /* Direction bit position. */ + +/* TC1.CTRLFSET bit masks and bit positions */ +/* TC1_CMD Predefined. */ +/* TC1_CMD Predefined. */ + +/* TC1_LUPD Predefined. */ +/* TC1_LUPD Predefined. */ + +/* TC1_DIR Predefined. */ +/* TC1_DIR Predefined. */ + +/* TC1.CTRLGCLR bit masks and bit positions */ +#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ + +#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ + +#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +/* TC1.CTRLGSET bit masks and bit positions */ +/* TC1_CCBBV Predefined. */ +/* TC1_CCBBV Predefined. */ + +/* TC1_CCABV Predefined. */ +/* TC1_CCABV Predefined. */ + +/* TC1_PERBV Predefined. */ +/* TC1_PERBV Predefined. */ + +/* TC1.INTFLAGS bit masks and bit positions */ +#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ + +#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ + +#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* TC2 - 16-bit Timer/Counter type 2 */ +/* TC2.CTRLA bit masks and bit positions */ +#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ +#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* TC2.CTRLB bit masks and bit positions */ +#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ +#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ + +#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ +#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ + +#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ +#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ + +#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ +#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ + +#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ +#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ + +#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ +#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ + +#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ +#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ + +#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ +#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ + +/* TC2.CTRLC bit masks and bit positions */ +#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ +#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ + +#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ +#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ + +#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ +#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ + +#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ +#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ + +#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ +#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ + +#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ +#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ + +#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ +#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ + +#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ +#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ + +/* TC2.CTRLE bit masks and bit positions */ +#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ +#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ +#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ +#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ +#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ +#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ + +/* TC2.INTCTRLA bit masks and bit positions */ +#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ +#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ +#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ +#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ +#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ +#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ + +#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ +#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ +#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ +#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ +#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ +#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ + +/* TC2.INTCTRLB bit masks and bit positions */ +#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ +#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ +#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ +#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ +#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ +#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ + +#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ +#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ +#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ +#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ +#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ +#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ + +#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ +#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ +#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ +#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ +#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ +#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ + +#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ +#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ +#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ +#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ +#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ +#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ + +/* TC2.CTRLF bit masks and bit positions */ +#define TC2_CMD_gm 0x0C /* Command group mask. */ +#define TC2_CMD_gp 2 /* Command group position. */ +#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC2_CMD0_bp 2 /* Command bit 0 position. */ +#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC2_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ +#define TC2_CMDEN_gp 0 /* Command Enable group position. */ +#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ +#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ +#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ +#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ + +/* TC2.INTFLAGS bit masks and bit positions */ +#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ +#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ + +#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ +#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ + +#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ +#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ + +#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ +#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ + +#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ +#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ + +#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ +#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ + +/* AWEX - Timer/Counter Advanced Waveform Extension */ +/* AWEX.CTRL bit masks and bit positions */ +#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ + +#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ + +#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ + +#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ + +#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ + +#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ + +/* AWEX.FDCTRL bit masks and bit positions */ +#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ + +#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ + +#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ + +/* AWEX.STATUS bit masks and bit positions */ +#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ + +#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ + +#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ + +/* AWEX.STATUSSET bit masks and bit positions */ +/* AWEX_FDF Predefined. */ +/* AWEX_FDF Predefined. */ + +/* AWEX_DTHSBUFV Predefined. */ +/* AWEX_DTHSBUFV Predefined. */ + +/* AWEX_DTLSBUFV Predefined. */ +/* AWEX_DTLSBUFV Predefined. */ + +/* HIRES - Timer/Counter High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ +#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* LOCKBIT - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTC interrupt vectors */ +#define PORTC_INT0_vect_num 2 +#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +#define PORTC_INT1_vect_num 3 +#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ + +/* PORTR interrupt vectors */ +#define PORTR_INT0_vect_num 4 +#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +#define PORTR_INT1_vect_num 5 +#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 10 +#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 11 +#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 12 +#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 13 +#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_OVF_vect_num 14 +#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LUNF_vect_num 14 +#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_ERR_vect_num 15 +#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_HUNF_vect_num 15 +#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCA_vect_num 16 +#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPA_vect_num 16 +#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCB_vect_num 17 +#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPB_vect_num 17 +#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCC_vect_num 18 +#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPC_vect_num 18 +#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ + +/* TCC0 interrupt vectors */ +#define TCC0_CCD_vect_num 19 +#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ + +/* TCC2 interrupt vectors */ +#define TCC2_LCMPD_vect_num 19 +#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ + +/* TCC1 interrupt vectors */ +#define TCC1_OVF_vect_num 20 +#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +#define TCC1_ERR_vect_num 21 +#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +#define TCC1_CCA_vect_num 22 +#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +#define TCC1_CCB_vect_num 23 +#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 24 +#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 25 +#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 26 +#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 27 +#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 32 +#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +#define NVM_SPM_vect_num 33 +#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ + +/* PORTB interrupt vectors */ +#define PORTB_INT0_vect_num 34 +#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +#define PORTB_INT1_vect_num 35 +#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ + +/* PORTE interrupt vectors */ +#define PORTE_INT0_vect_num 43 +#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +#define PORTE_INT1_vect_num 44 +#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ + +/* TWIE interrupt vectors */ +#define TWIE_TWIS_vect_num 45 +#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +#define TWIE_TWIM_vect_num 46 +#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ + +/* TCE0 interrupt vectors */ +#define TCE0_OVF_vect_num 47 +#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +#define TCE0_ERR_vect_num 48 +#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +#define TCE0_CCA_vect_num 49 +#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +#define TCE0_CCB_vect_num 50 +#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +#define TCE0_CCC_vect_num 51 +#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +#define TCE0_CCD_vect_num 52 +#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ + +/* USARTE0 interrupt vectors */ +#define USARTE0_RXC_vect_num 58 +#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +#define USARTE0_DRE_vect_num 59 +#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +#define USARTE0_TXC_vect_num 60 +#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT0_vect_num 64 +#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +#define PORTD_INT1_vect_num 65 +#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ + +/* PORTA interrupt vectors */ +#define PORTA_INT0_vect_num 66 +#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +#define PORTA_INT1_vect_num 67 +#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 68 +#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 69 +#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 70 +#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 71 +#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ + +/* TCD0 interrupt vectors */ +#define TCD0_OVF_vect_num 77 +#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LUNF_vect_num 77 +#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_ERR_vect_num 78 +#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_HUNF_vect_num 78 +#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCA_vect_num 79 +#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPA_vect_num 79 +#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCB_vect_num 80 +#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPB_vect_num 80 +#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCC_vect_num 81 +#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPC_vect_num 81 +#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ + +/* TCD0 interrupt vectors */ +#define TCD0_CCD_vect_num 82 +#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ + +/* TCD2 interrupt vectors */ +#define TCD2_LCMPD_vect_num 82 +#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ + +/* SPID interrupt vectors */ +#define SPID_INT_vect_num 87 +#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 88 +#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 89 +#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 90 +#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (91 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (69632) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (65536) +#define APP_SECTION_PAGE_SIZE (256) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0xF000) +#define APPTABLE_SECTION_SIZE (4096) +#define APPTABLE_SECTION_PAGE_SIZE (256) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x10000) +#define BOOT_SECTION_SIZE (4096) +#define BOOT_SECTION_PAGE_SIZE (256) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (12288) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (2048) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (4096) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (2048) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (6) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (256) +#define USER_SIGNATURES_PAGE_SIZE (256) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (64) +#define PROD_SIGNATURES_PAGE_SIZE (256) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 256 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 6 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x96 +#define SIGNATURE_2 0x47 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC1 +#define __AVR_HAVE_PRPC_TC0 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_SPI +#define __AVR_HAVE_PRPD_TC0 + +/* PR.PRPE */ +#define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPE_TWI +#define __AVR_HAVE_PRPE_USART0 +#define __AVR_HAVE_PRPE_TC0 + +/* PR.PRPF */ +#define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) +#define __AVR_HAVE_PRPF_USART0 +#define __AVR_HAVE_PRPF_TC0 + + +#endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/iox8e5.h b/hardware/tools/avr/avr/include/avr/iox8e5.h new file mode 100644 index 0000000000000000000000000000000000000000..cfab85d9f880f4fbc86d93c9f8c8b8fef9fccd22 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/iox8e5.h @@ -0,0 +1,7699 @@ +/***************************************************************************** + * + * Copyright (C) 2015 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +#ifndef _AVR_IOXXX_H_ +# define _AVR_IOXXX_H_ "iox8e5.h" +#else +# error "Attempt to include more than one file." +#endif + +#ifndef _AVR_ATXMEGA8E5_H_INCLUDED +#define _AVR_ATXMEGA8E5_H_INCLUDED + +/* Ungrouped common registers */ +#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +/* Deprecated */ +#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ + +#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +#define SREG _SFR_MEM8(0x003F) /* Status Register */ + +/* C Language Only */ +#if !defined (__ASSEMBLER__) + +#include + +typedef volatile uint8_t register8_t; +typedef volatile uint16_t register16_t; +typedef volatile uint32_t register32_t; + + +#ifdef _WORDREGISTER +#undef _WORDREGISTER +#endif +#define _WORDREGISTER(regname) \ + __extension__ union \ + { \ + register16_t regname; \ + struct \ + { \ + register8_t regname ## L; \ + register8_t regname ## H; \ + }; \ + } + +#ifdef _DWORDREGISTER +#undef _DWORDREGISTER +#endif +#define _DWORDREGISTER(regname) \ + __extension__ union \ + { \ + register32_t regname; \ + struct \ + { \ + register8_t regname ## 0; \ + register8_t regname ## 1; \ + register8_t regname ## 2; \ + register8_t regname ## 3; \ + }; \ + } + + +/* +========================================================================== +IO Module Structures +========================================================================== +*/ + + +/* +-------------------------------------------------------------------------- +VPORT - Virtual Ports +-------------------------------------------------------------------------- +*/ + +/* Virtual Port */ +typedef struct VPORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t OUT; /* I/O Port Output */ + register8_t IN; /* I/O Port Input */ + register8_t INTFLAGS; /* Interrupt Flag Register */ +} VPORT_t; + + +/* +-------------------------------------------------------------------------- +XOCD - On-Chip Debug System +-------------------------------------------------------------------------- +*/ + +/* On-Chip Debug System */ +typedef struct OCD_struct +{ + register8_t OCDR0; /* OCD Register 0 */ + register8_t OCDR1; /* OCD Register 1 */ +} OCD_t; + + +/* +-------------------------------------------------------------------------- +CPU - CPU +-------------------------------------------------------------------------- +*/ + +/* CCP signatures */ +typedef enum CCP_enum +{ + CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ + CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +} CCP_t; + + +/* +-------------------------------------------------------------------------- +CLK - Clock System +-------------------------------------------------------------------------- +*/ + +/* Clock System */ +typedef struct CLK_struct +{ + register8_t CTRL; /* Control Register */ + register8_t PSCTRL; /* Prescaler Control Register */ + register8_t LOCK; /* Lock register */ + register8_t RTCCTRL; /* RTC Control Register */ + register8_t reserved_0x04; +} CLK_t; + + +/* Power Reduction */ +typedef struct PR_struct +{ + register8_t PRGEN; /* General Power Reduction */ + register8_t PRPA; /* Power Reduction Port A */ + register8_t reserved_0x02; + register8_t PRPC; /* Power Reduction Port C */ + register8_t PRPD; /* Power Reduction Port D */ + register8_t reserved_0x05; + register8_t reserved_0x06; +} PR_t; + +/* System Clock Selection */ +typedef enum CLK_SCLKSEL_enum +{ + CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ + CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ + CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ + CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ + CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ + CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ +} CLK_SCLKSEL_t; + +/* Prescaler A Division Factor */ +typedef enum CLK_PSADIV_enum +{ + CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ + CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ + CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ + CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ + CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ + CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ + CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ + CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ + CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ + CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ + CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ + CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ + CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ + CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ + CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ +} CLK_PSADIV_t; + +/* Prescaler B and C Division Factor */ +typedef enum CLK_PSBCDIV_enum +{ + CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ + CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ + CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ + CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +} CLK_PSBCDIV_t; + +/* RTC Clock Source */ +typedef enum CLK_RTCSRC_enum +{ + CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ + CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ + CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ + CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +} CLK_RTCSRC_t; + + +/* +-------------------------------------------------------------------------- +SLEEP - Sleep Controller +-------------------------------------------------------------------------- +*/ + +/* Sleep Controller */ +typedef struct SLEEP_struct +{ + register8_t CTRL; /* Control Register */ +} SLEEP_t; + +/* Sleep Mode */ +typedef enum SLEEP_SMODE_enum +{ + SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ + SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ + SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ + SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ + SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +} SLEEP_SMODE_t; + + + +#define SLEEP_MODE_IDLE (0x00<<1) +#define SLEEP_MODE_PWR_DOWN (0x02<<1) +#define SLEEP_MODE_PWR_SAVE (0x03<<1) +#define SLEEP_MODE_STANDBY (0x06<<1) +#define SLEEP_MODE_EXT_STANDBY (0x07<<1) +/* +-------------------------------------------------------------------------- +OSC - Oscillator +-------------------------------------------------------------------------- +*/ + +/* Oscillator */ +typedef struct OSC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t XOSCCTRL; /* External Oscillator Control Register */ + register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ + register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ + register8_t PLLCTRL; /* PLL Control Register */ + register8_t DFLLCTRL; /* DFLL Control Register */ + register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ +} OSC_t; + +/* Oscillator Frequency Range */ +typedef enum OSC_FRQRANGE_enum +{ + OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ + OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ + OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ + OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +} OSC_FRQRANGE_t; + +/* External Oscillator Selection and Startup Time */ +typedef enum OSC_XOSCSEL_enum +{ + OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ + OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ + OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ + OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ + OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ + OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ +} OSC_XOSCSEL_t; + +/* PLL Clock Source */ +typedef enum OSC_PLLSRC_enum +{ + OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ + OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ + OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ + OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +} OSC_PLLSRC_t; + +/* 32 MHz DFLL Calibration Reference */ +typedef enum OSC_RC32MCREF_enum +{ + OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ + OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ +} OSC_RC32MCREF_t; + + +/* +-------------------------------------------------------------------------- +DFLL - DFLL +-------------------------------------------------------------------------- +*/ + +/* DFLL */ +typedef struct DFLL_struct +{ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x01; + register8_t CALA; /* Calibration Register A */ + register8_t CALB; /* Calibration Register B */ + register8_t COMP0; /* Oscillator Compare Register 0 */ + register8_t COMP1; /* Oscillator Compare Register 1 */ + register8_t COMP2; /* Oscillator Compare Register 2 */ + register8_t reserved_0x07; +} DFLL_t; + + +/* +-------------------------------------------------------------------------- +RST - Reset +-------------------------------------------------------------------------- +*/ + +/* Reset */ +typedef struct RST_struct +{ + register8_t STATUS; /* Status Register */ + register8_t CTRL; /* Control Register */ +} RST_t; + + +/* +-------------------------------------------------------------------------- +WDT - Watch-Dog Timer +-------------------------------------------------------------------------- +*/ + +/* Watch-Dog Timer */ +typedef struct WDT_struct +{ + register8_t CTRL; /* Control */ + register8_t WINCTRL; /* Windowed Mode Control */ + register8_t STATUS; /* Status */ +} WDT_t; + +/* Period setting */ +typedef enum WDT_PER_enum +{ + WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_PER_t; + +/* Closed window period */ +typedef enum WDT_WPER_enum +{ + WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ + WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ + WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ + WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ + WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ + WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ + WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ + WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ + WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ + WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ + WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +} WDT_WPER_t; + + +/* +-------------------------------------------------------------------------- +MCU - MCU Control +-------------------------------------------------------------------------- +*/ + +/* MCU Control */ +typedef struct MCU_struct +{ + register8_t DEVID0; /* Device ID byte 0 */ + register8_t DEVID1; /* Device ID byte 1 */ + register8_t DEVID2; /* Device ID byte 2 */ + register8_t REVID; /* Revision ID */ + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t ANAINIT; /* Analog Startup Delay */ + register8_t EVSYSLOCK; /* Event System Lock */ + register8_t WEXLOCK; /* WEX Lock */ + register8_t FAULTLOCK; /* FAULT Lock */ + register8_t reserved_0x0B; +} MCU_t; + + +/* +-------------------------------------------------------------------------- +PMIC - Programmable Multi-level Interrupt Controller +-------------------------------------------------------------------------- +*/ + +/* Programmable Multi-level Interrupt Controller */ +typedef struct PMIC_struct +{ + register8_t STATUS; /* Status Register */ + register8_t INTPRI; /* Interrupt Priority */ + register8_t CTRL; /* Control Register */ + register8_t reserved_0x03; + register8_t reserved_0x04; + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} PMIC_t; + + +/* +-------------------------------------------------------------------------- +PORTCFG - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O port Configuration */ +typedef struct PORTCFG_struct +{ + register8_t MPCMASK; /* Multi-pin Configuration Mask */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t reserved_0x03; + register8_t CLKOUT; /* Clock Out Register */ + register8_t reserved_0x05; + register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ + register8_t SRLCTRL; /* Slew Rate Limit Control Register */ +} PORTCFG_t; + +/* Clock and Event Output Port */ +typedef enum PORTCFG_CLKEVPIN_enum +{ + PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ + PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ +} PORTCFG_CLKEVPIN_t; + +/* RTC Clock Output Port */ +typedef enum PORTCFG_RTCCLKOUT_enum +{ + PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ + PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ + PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ + PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ +} PORTCFG_RTCCLKOUT_t; + +/* Peripheral Clock Output Select */ +typedef enum PORTCFG_CLKOUTSEL_enum +{ + PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ + PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +} PORTCFG_CLKOUTSEL_t; + +/* System Clock Output Port */ +typedef enum PORTCFG_CLKOUT_enum +{ + PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ + PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ + PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ + PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ +} PORTCFG_CLKOUT_t; + +/* Analog Comparator Output Port */ +typedef enum PORTCFG_ACOUT_enum +{ + PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ + PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ + PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ + PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ +} PORTCFG_ACOUT_t; + +/* Event Output Port */ +typedef enum PORTCFG_EVOUT_enum +{ + PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ + PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ + PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ + PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ +} PORTCFG_EVOUT_t; + +/* Event Output Select */ +typedef enum PORTCFG_EVOUTSEL_enum +{ + PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ + PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ + PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ + PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ + PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ + PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ + PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ + PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ +} PORTCFG_EVOUTSEL_t; + + +/* +-------------------------------------------------------------------------- +CRC - Cyclic Redundancy Checker +-------------------------------------------------------------------------- +*/ + +/* Cyclic Redundancy Checker */ +typedef struct CRC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t reserved_0x02; + register8_t DATAIN; /* Data Input */ + register8_t CHECKSUM0; /* Checksum byte 0 */ + register8_t CHECKSUM1; /* Checksum byte 1 */ + register8_t CHECKSUM2; /* Checksum byte 2 */ + register8_t CHECKSUM3; /* Checksum byte 3 */ +} CRC_t; + +/* Reset */ +typedef enum CRC_RESET_enum +{ + CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ + CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ + CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +} CRC_RESET_t; + +/* Input Source */ +typedef enum CRC_SOURCE_enum +{ + CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ + CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ + CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ + CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ + CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ + CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ + CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +} CRC_SOURCE_t; + + +/* +-------------------------------------------------------------------------- +EDMA - Enhanced DMA Controller +-------------------------------------------------------------------------- +*/ + +/* EDMA Channel */ +typedef struct EDMA_CH_struct +{ + register8_t CTRLA; /* Channel Control A */ + register8_t CTRLB; /* Channel Control */ + register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ + register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ + register8_t TRIGSRC; /* Channel Trigger Source */ + register8_t reserved_0x05; + _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ + _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} EDMA_CH_t; + + +/* Enhanced DMA Controller */ +typedef struct EDMA_struct +{ + register8_t CTRL; /* Control */ + register8_t reserved_0x01; + register8_t reserved_0x02; + register8_t INTFLAGS; /* Transfer Interrupt Status */ + register8_t STATUS; /* Status */ + register8_t reserved_0x05; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + EDMA_CH_t CH0; /* EDMA Channel 0 */ + EDMA_CH_t CH1; /* EDMA Channel 1 */ + EDMA_CH_t CH2; /* EDMA Channel 2 */ + EDMA_CH_t CH3; /* EDMA Channel 3 */ +} EDMA_t; + +/* Channel mode */ +typedef enum EDMA_CHMODE_enum +{ + EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ + EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ + EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ + EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ +} EDMA_CHMODE_t; + +/* Double buffer mode */ +typedef enum EDMA_DBUFMODE_enum +{ + EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ + EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ + EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ + EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ +} EDMA_DBUFMODE_t; + +/* Priority mode */ +typedef enum EDMA_PRIMODE_enum +{ + EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ + EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ + EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ + EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ +} EDMA_PRIMODE_t; + +/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ +typedef enum EDMA_CH_RELOAD_enum +{ + EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ + EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ + EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ + EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ +} EDMA_CH_RELOAD_t; + +/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ +typedef enum EDMA_CH_DIR_enum +{ + EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ + EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ +} EDMA_CH_DIR_t; + +/* Destination addressing mode */ +typedef enum EDMA_CH_DESTDIR_enum +{ + EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ + EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ + EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ + EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ + EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ +} EDMA_CH_DESTDIR_t; + +/* Transfer trigger source */ +typedef enum EDMA_CH_TRIGSRC_enum +{ + EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ + EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ + EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ + EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ + EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ + EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ + EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ + EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ + EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ +} EDMA_CH_TRIGSRC_t; + +/* Interrupt level */ +typedef enum EDMA_CH_INTLVL_enum +{ + EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ + EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ + EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ +} EDMA_CH_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +EVSYS - Event System +-------------------------------------------------------------------------- +*/ + +/* Event System */ +typedef struct EVSYS_struct +{ + register8_t CH0MUX; /* Event Channel 0 Multiplexer */ + register8_t CH1MUX; /* Event Channel 1 Multiplexer */ + register8_t CH2MUX; /* Event Channel 2 Multiplexer */ + register8_t CH3MUX; /* Event Channel 3 Multiplexer */ + register8_t CH4MUX; /* Event Channel 4 Multiplexer */ + register8_t CH5MUX; /* Event Channel 5 Multiplexer */ + register8_t CH6MUX; /* Event Channel 6 Multiplexer */ + register8_t CH7MUX; /* Event Channel 7 Multiplexer */ + register8_t CH0CTRL; /* Channel 0 Control Register */ + register8_t CH1CTRL; /* Channel 1 Control Register */ + register8_t CH2CTRL; /* Channel 2 Control Register */ + register8_t CH3CTRL; /* Channel 3 Control Register */ + register8_t CH4CTRL; /* Channel 4 Control Register */ + register8_t CH5CTRL; /* Channel 5 Control Register */ + register8_t CH6CTRL; /* Channel 6 Control Register */ + register8_t CH7CTRL; /* Channel 7 Control Register */ + register8_t STROBE; /* Event Strobe */ + register8_t DATA; /* Event Data */ + register8_t DFCTRL; /* Digital Filter Control Register */ +} EVSYS_t; + +/* Event Channel multiplexer input selection */ +typedef enum EVSYS_CHMUX_enum +{ + EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ + EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ + EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ + EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ + EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ + EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ + EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ + EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ + EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ + EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ + EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ + EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ + EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ + EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ + EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ + EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ + EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ + EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ + EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ + EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ + EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ + EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ + EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ + EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ + EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ + EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ + EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ + EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ + EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ + EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ + EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ + EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ + EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ + EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ + EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ + EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ + EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ + EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ + EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ + EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ + EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ + EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ + EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ + EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ + EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ + EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ + EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ + EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ + EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ + EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ + EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ + EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ + EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ + EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ + EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ + EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ + EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ + EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ + EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ + EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ + EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ + EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ + EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ + EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ + EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ + EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ + EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ + EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ +} EVSYS_CHMUX_t; + +/* Quadrature Decoder Index Recognition Mode */ +typedef enum EVSYS_QDIRM_enum +{ + EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ + EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ + EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ + EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +} EVSYS_QDIRM_t; + +/* Digital filter coefficient */ +typedef enum EVSYS_DIGFILT_enum +{ + EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ + EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ + EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ + EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ + EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ + EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ + EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ + EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +} EVSYS_DIGFILT_t; + +/* Prescaler Filter */ +typedef enum EVSYS_PRESCFILT_enum +{ + EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ + EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ + EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ + EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ +} EVSYS_PRESCFILT_t; + +/* Prescaler */ +typedef enum EVSYS_PRESCALER_enum +{ + EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ + EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ + EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ + EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ + EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ +} EVSYS_PRESCALER_t; + + +/* +-------------------------------------------------------------------------- +NVM - Non Volatile Memory Controller +-------------------------------------------------------------------------- +*/ + +/* Non-volatile Memory Controller */ +typedef struct NVM_struct +{ + register8_t ADDR0; /* Address Register 0 */ + register8_t ADDR1; /* Address Register 1 */ + register8_t ADDR2; /* Address Register 2 */ + register8_t reserved_0x03; + register8_t DATA0; /* Data Register 0 */ + register8_t DATA1; /* Data Register 1 */ + register8_t DATA2; /* Data Register 2 */ + register8_t reserved_0x07; + register8_t reserved_0x08; + register8_t reserved_0x09; + register8_t CMD; /* Command */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t INTCTRL; /* Interrupt Control */ + register8_t reserved_0x0E; + register8_t STATUS; /* Status */ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_t; + +/* NVM Command */ +typedef enum NVM_CMD_enum +{ + NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ + NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ + NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ + NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ + NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ + NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ + NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ + NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ + NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ + NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ + NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ + NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ + NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ + NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ + NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ + NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ + NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ + NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ + NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ + NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ + NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ + NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ + NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ + NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ + NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ + NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ + NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ + NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ + NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ + NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ + NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ + NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ +} NVM_CMD_t; + +/* SPM ready interrupt level */ +typedef enum NVM_SPMLVL_enum +{ + NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ + NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ + NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ + NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +} NVM_SPMLVL_t; + +/* EEPROM ready interrupt level */ +typedef enum NVM_EELVL_enum +{ + NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ + NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ + NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +} NVM_EELVL_t; + +/* Boot lock bits - boot setcion */ +typedef enum NVM_BLBB_enum +{ + NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} NVM_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum NVM_BLBA_enum +{ + NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} NVM_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum NVM_BLBAT_enum +{ + NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} NVM_BLBAT_t; + +/* Lock bits */ +typedef enum NVM_LB_enum +{ + NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} NVM_LB_t; + + +/* +-------------------------------------------------------------------------- +ADC - Analog/Digital Converter +-------------------------------------------------------------------------- +*/ + +/* ADC Channel */ +typedef struct ADC_CH_struct +{ + register8_t CTRL; /* Control Register */ + register8_t MUXCTRL; /* MUX Control */ + register8_t INTCTRL; /* Channel Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + _WORDREGISTER(RES); /* Channel Result */ + register8_t SCAN; /* Input Channel Scan */ + register8_t CORRCTRL; /* Correction Control Register */ + register8_t OFFSETCORR0; /* Offset Correction Register 0 */ + register8_t OFFSETCORR1; /* Offset Correction Register 1 */ + register8_t GAINCORR0; /* Gain Correction Register 0 */ + register8_t GAINCORR1; /* Gain Correction Register 1 */ + register8_t AVGCTRL; /* Average Control Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; +} ADC_CH_t; + + +/* Analog-to-Digital Converter */ +typedef struct ADC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t REFCTRL; /* Reference Control */ + register8_t EVCTRL; /* Event Control */ + register8_t PRESCALER; /* Clock Prescaler */ + register8_t reserved_0x05; + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary Register */ + register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ + register8_t reserved_0x09; + register8_t reserved_0x0A; + register8_t reserved_0x0B; + _WORDREGISTER(CAL); /* Calibration Value */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + _WORDREGISTER(CH0RES); /* Channel 0 Result */ + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CMP); /* Compare Value */ + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + ADC_CH_t CH0; /* ADC Channel 0 */ +} ADC_t; + +/* Current Limitation */ +typedef enum ADC_CURRLIMIT_enum +{ + ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ + ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ + ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ + ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ +} ADC_CURRLIMIT_t; + +/* Conversion result resolution */ +typedef enum ADC_RESOLUTION_enum +{ + ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ + ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ + ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ + ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +} ADC_RESOLUTION_t; + +/* Voltage reference selection */ +typedef enum ADC_REFSEL_enum +{ + ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ + ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ + ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ + ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ + ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ +} ADC_REFSEL_t; + +/* Event channel input selection */ +typedef enum ADC_EVSEL_enum +{ + ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ + ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ + ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ + ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ + ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ + ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ + ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ + ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +} ADC_EVSEL_t; + +/* Event action selection */ +typedef enum ADC_EVACT_enum +{ + ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ + ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ + ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ +} ADC_EVACT_t; + +/* Clock prescaler */ +typedef enum ADC_PRESCALER_enum +{ + ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ + ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ + ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ + ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ + ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ + ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ + ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ + ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +} ADC_PRESCALER_t; + +/* Gain factor */ +typedef enum ADC_CH_GAIN_enum +{ + ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ + ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ + ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ + ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ + ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ + ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ + ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ + ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ +} ADC_CH_GAIN_t; + +/* Input mode */ +typedef enum ADC_CH_INPUTMODE_enum +{ + ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ + ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ + ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ + ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ +} ADC_CH_INPUTMODE_t; + +/* Positive input multiplexer selection */ +typedef enum ADC_CH_MUXPOS_enum +{ + ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ + ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ + ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ + ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ + ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ + ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ + ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ + ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ + ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ + ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ + ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ + ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ + ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ + ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ + ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ + ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +} ADC_CH_MUXPOS_t; + +/* Internal input multiplexer selections */ +typedef enum ADC_CH_MUXINT_enum +{ + ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ + ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ + ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ + ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ +} ADC_CH_MUXINT_t; + +/* Negative input multiplexer selection when gain on 4 LSB pins */ +typedef enum ADC_CH_MUXNEGL_enum +{ + ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ + ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ + ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ + ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ + ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ + ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ +} ADC_CH_MUXNEGL_t; + +/* Negative input multiplexer selection when gain on 4 MSB pins */ +typedef enum ADC_CH_MUXNEGH_enum +{ + ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ + ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ + ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ + ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ + ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ +} ADC_CH_MUXNEGH_t; + +/* Negative input multiplexer selection */ +typedef enum ADC_CH_MUXNEG_enum +{ + ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +} ADC_CH_MUXNEG_t; + +/* Interupt mode */ +typedef enum ADC_CH_INTMODE_enum +{ + ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ + ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ + ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +} ADC_CH_INTMODE_t; + +/* Interrupt level */ +typedef enum ADC_CH_INTLVL_enum +{ + ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ + ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ + ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +} ADC_CH_INTLVL_t; + +/* Averaged Number of Samples */ +typedef enum ADC_SAMPNUM_enum +{ + ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ + ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ + ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ + ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ + ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ + ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ + ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ + ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ + ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ + ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ + ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ +} ADC_SAMPNUM_t; + + +/* +-------------------------------------------------------------------------- +DAC - Digital/Analog Converter +-------------------------------------------------------------------------- +*/ + +/* Digital-to-Analog Converter */ +typedef struct DAC_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t EVCTRL; /* Event Input Control */ + register8_t reserved_0x04; + register8_t STATUS; /* Status */ + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t CH0GAINCAL; /* Gain Calibration */ + register8_t CH0OFFSETCAL; /* Offset Calibration */ + register8_t CH1GAINCAL; /* Gain Calibration */ + register8_t CH1OFFSETCAL; /* Offset Calibration */ + register8_t reserved_0x0C; + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + _WORDREGISTER(CH0DATA); /* Channel 0 Data */ + _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +} DAC_t; + +/* Output channel selection */ +typedef enum DAC_CHSEL_enum +{ + DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ + DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ + DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +} DAC_CHSEL_t; + +/* Reference voltage selection */ +typedef enum DAC_REFSEL_enum +{ + DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ + DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ + DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ + DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +} DAC_REFSEL_t; + +/* Event channel selection */ +typedef enum DAC_EVSEL_enum +{ + DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ + DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ + DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ + DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ + DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ + DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ + DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ + DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +} DAC_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +AC - Analog Comparator +-------------------------------------------------------------------------- +*/ + +/* Analog Comparator */ +typedef struct AC_struct +{ + register8_t AC0CTRL; /* Analog Comparator 0 Control */ + register8_t AC1CTRL; /* Analog Comparator 1 Control */ + register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ + register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t WINCTRL; /* Window Mode Control */ + register8_t STATUS; /* Status */ + register8_t CURRCTRL; /* Current Source Control Register */ + register8_t CURRCALIB; /* Current Source Calibration Register */ +} AC_t; + +/* Interrupt mode */ +typedef enum AC_INTMODE_enum +{ + AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ + AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ + AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +} AC_INTMODE_t; + +/* Interrupt level */ +typedef enum AC_INTLVL_enum +{ + AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ + AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ + AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ + AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +} AC_INTLVL_t; + +/* Hysteresis mode selection */ +typedef enum AC_HYSMODE_enum +{ + AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ + AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ + AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +} AC_HYSMODE_t; + +/* Positive input multiplexer selection */ +typedef enum AC_MUXPOS_enum +{ + AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ + AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ + AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ + AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ + AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ + AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ + AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ + AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +} AC_MUXPOS_t; + +/* Negative input multiplexer selection */ +typedef enum AC_MUXNEG_enum +{ + AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ + AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ + AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ + AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ + AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ + AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ + AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ + AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +} AC_MUXNEG_t; + +/* Windows interrupt mode */ +typedef enum AC_WINTMODE_enum +{ + AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ + AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ + AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ + AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +} AC_WINTMODE_t; + +/* Window interrupt level */ +typedef enum AC_WINTLVL_enum +{ + AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ + AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ + AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ + AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +} AC_WINTLVL_t; + +/* Window mode state */ +typedef enum AC_WSTATE_enum +{ + AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ + AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ + AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +} AC_WSTATE_t; + + +/* +-------------------------------------------------------------------------- +RTC - Real-Time Clounter +-------------------------------------------------------------------------- +*/ + +/* Real-Time Counter */ +typedef struct RTC_struct +{ + register8_t CTRL; /* Control Register */ + register8_t STATUS; /* Status Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flags */ + register8_t TEMP; /* Temporary register */ + register8_t reserved_0x05; + register8_t CALIB; /* Calibration Register */ + register8_t reserved_0x07; + _WORDREGISTER(CNT); /* Count Register */ + _WORDREGISTER(PER); /* Period Register */ + _WORDREGISTER(COMP); /* Compare Register */ +} RTC_t; + +/* Prescaler Factor */ +typedef enum RTC_PRESCALER_enum +{ + RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ + RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ + RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ + RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ + RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ + RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ + RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ + RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +} RTC_PRESCALER_t; + +/* Compare Interrupt level */ +typedef enum RTC_COMPINTLVL_enum +{ + RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ + RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +} RTC_COMPINTLVL_t; + +/* Overflow Interrupt level */ +typedef enum RTC_OVFINTLVL_enum +{ + RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} RTC_OVFINTLVL_t; + + +/* +-------------------------------------------------------------------------- +XCL - XMEGA Custom Logic +-------------------------------------------------------------------------- +*/ + +/* XMEGA Custom Logic */ +typedef struct XCL_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t CTRLG; /* Control Register G */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t PLC; /* Peripheral Lenght Control Register */ + register8_t CNTL; /* Counter Register Low */ + register8_t CNTH; /* Counter Register High */ + register8_t CMPL; /* Compare Register Low */ + register8_t CMPH; /* Compare Register High */ + register8_t PERCAPTL; /* Period or Capture Register Low */ + register8_t PERCAPTH; /* Period or Capture Register High */ +} XCL_t; + +/* LUT0 Output Enable */ +typedef enum XCL_LUTOUTEN_enum +{ + XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ + XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ + XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ +} XCL_LUTOUTEN_t; + +/* Port Selection */ +typedef enum XCL_PORTSEL_enum +{ + XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ + XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ +} XCL_PORTSEL_t; + +/* LUT Configuration */ +typedef enum XCL_LUTCONF_enum +{ + XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ + XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ + XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ + XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ + XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ + XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ + XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ + XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ +} XCL_LUTCONF_t; + +/* Input Selection */ +typedef enum XCL_INSEL_enum +{ + XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ + XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ + XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ + XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ +} XCL_INSEL_t; + +/* Delay Configuration on LUT */ +typedef enum XCL_DLYCONF_enum +{ + XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ + XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ + XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ +} XCL_DLYCONF_t; + +/* Delay Selection */ +typedef enum XCL_DLYSEL_enum +{ + XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ + XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ + XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ + XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ +} XCL_DLYSEL_t; + +/* Clock Selection */ +typedef enum XCL_CLKSEL_enum +{ + XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ + XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ + XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ + XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ + XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ + XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ + XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ + XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ + XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ + XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ + XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ + XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ + XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ + XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ + XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ + XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ +} XCL_CLKSEL_t; + +/* Timer/Counter Command Selection */ +typedef enum XCL_CMDSEL_enum +{ + XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ + XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ +} XCL_CMDSEL_t; + +/* Timer/Counter Selection */ +typedef enum XCL_TCSEL_enum +{ + XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ + XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ + XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ + XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ + XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ + XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ +} XCL_TCSEL_t; + +/* Timer/Counter Mode */ +typedef enum XCL_TCMODE_enum +{ + XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ + XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ + XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ +} XCL_TCMODE_t; + +/* Compare Output Value Timer */ +typedef enum XCL_CMPEN_enum +{ + XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ + XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ +} XCL_CMPEN_t; + +/* Command Enable */ +typedef enum XCL_CMDEN_enum +{ + XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ + XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ + XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ + XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ +} XCL_CMDEN_t; + +/* Timer/Counter Event Source Selection */ +typedef enum XCL_EVSRC_enum +{ + XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ + XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ + XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ + XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ + XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ + XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ + XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ + XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ +} XCL_EVSRC_t; + +/* Timer/Counter Event Action Selection */ +typedef enum XCL_EVACT_enum +{ + XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ + XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ + XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ + XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ +} XCL_EVACT_t; + +/* Underflow Interrupt level */ +typedef enum XCL_UNF_INTLVL_enum +{ + XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ + XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ + XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ +} XCL_UNF_INTLVL_t; + +/* Compare/Capture Interrupt level */ +typedef enum XCL_CC_INTLVL_enum +{ + XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} XCL_CC_INTLVL_t; + + +/* +-------------------------------------------------------------------------- +TWI - Two-Wire Interface +-------------------------------------------------------------------------- +*/ + +/* */ +typedef struct TWI_MASTER_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t STATUS; /* Status Register */ + register8_t BAUD; /* Baurd Rate Control Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ +} TWI_MASTER_t; + + +/* */ +typedef struct TWI_SLAVE_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t STATUS; /* Status Register */ + register8_t ADDR; /* Address Register */ + register8_t DATA; /* Data Register */ + register8_t ADDRMASK; /* Address Mask Register */ +} TWI_SLAVE_t; + + +/* */ +typedef struct TWI_TIMEOUT_struct +{ + register8_t TOS; /* Timeout Status Register */ + register8_t TOCONF; /* Timeout Configuration Register */ +} TWI_TIMEOUT_t; + + +/* Two-Wire Interface */ +typedef struct TWI_struct +{ + register8_t CTRL; /* TWI Common Control Register */ + TWI_MASTER_t MASTER; /* TWI master module */ + TWI_SLAVE_t SLAVE; /* TWI slave module */ + TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ +} TWI_t; + +/* SDA Hold Time */ +typedef enum TWI_SDAHOLD_enum +{ + TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ + TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ + TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ + TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ +} TWI_SDAHOLD_t; + +/* Master Interrupt Level */ +typedef enum TWI_MASTER_INTLVL_enum +{ + TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_MASTER_INTLVL_t; + +/* Inactive Timeout */ +typedef enum TWI_MASTER_TIMEOUT_enum +{ + TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ + TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ + TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ + TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +} TWI_MASTER_TIMEOUT_t; + +/* Master Command */ +typedef enum TWI_MASTER_CMD_enum +{ + TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ + TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ + TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +} TWI_MASTER_CMD_t; + +/* Master Bus State */ +typedef enum TWI_MASTER_BUSSTATE_enum +{ + TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ + TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ + TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ + TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +} TWI_MASTER_BUSSTATE_t; + +/* Slave Interrupt Level */ +typedef enum TWI_SLAVE_INTLVL_enum +{ + TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ + TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +} TWI_SLAVE_INTLVL_t; + +/* Slave Command */ +typedef enum TWI_SLAVE_CMD_enum +{ + TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ + TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ + TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +} TWI_SLAVE_CMD_t; + +/* Master Timeout */ +typedef enum TWI_MASTER_TTIMEOUT_enum +{ + TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ + TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ + TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ + TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ + TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ + TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ + TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ + TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ +} TWI_MASTER_TTIMEOUT_t; + +/* Slave Ttimeout */ +typedef enum TWI_SLAVE_TTIMEOUT_enum +{ + TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ + TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ + TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ + TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ + TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ + TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ + TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ + TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ +} TWI_SLAVE_TTIMEOUT_t; + +/* Master/Slave Extend Timeout */ +typedef enum TWI_MASTER_TMSEXT_enum +{ + TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ + TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ + TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ + TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ +} TWI_MASTER_TMSEXT_t; + + +/* +-------------------------------------------------------------------------- +PORT - Port Configuration +-------------------------------------------------------------------------- +*/ + +/* I/O Ports */ +typedef struct PORT_struct +{ + register8_t DIR; /* I/O Port Data Direction */ + register8_t DIRSET; /* I/O Port Data Direction Set */ + register8_t DIRCLR; /* I/O Port Data Direction Clear */ + register8_t DIRTGL; /* I/O Port Data Direction Toggle */ + register8_t OUT; /* I/O Port Output */ + register8_t OUTSET; /* I/O Port Output Set */ + register8_t OUTCLR; /* I/O Port Output Clear */ + register8_t OUTTGL; /* I/O Port Output Toggle */ + register8_t IN; /* I/O port Input */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t INTMASK; /* Port Interrupt Mask */ + register8_t reserved_0x0B; + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t REMAP; /* Pin Remap Register */ + register8_t reserved_0x0F; + register8_t PIN0CTRL; /* Pin 0 Control Register */ + register8_t PIN1CTRL; /* Pin 1 Control Register */ + register8_t PIN2CTRL; /* Pin 2 Control Register */ + register8_t PIN3CTRL; /* Pin 3 Control Register */ + register8_t PIN4CTRL; /* Pin 4 Control Register */ + register8_t PIN5CTRL; /* Pin 5 Control Register */ + register8_t PIN6CTRL; /* Pin 6 Control Register */ + register8_t PIN7CTRL; /* Pin 7 Control Register */ +} PORT_t; + +/* Port Interrupt Level */ +typedef enum PORT_INTLVL_enum +{ + PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} PORT_INTLVL_t; + +/* Output/Pull Configuration */ +typedef enum PORT_OPC_enum +{ + PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ + PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ + PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ + PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ + PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ + PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ + PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ + PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +} PORT_OPC_t; + +/* Input/Sense Configuration */ +typedef enum PORT_ISC_enum +{ + PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ + PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ + PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ + PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ + PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ + PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +} PORT_ISC_t; + + +/* +-------------------------------------------------------------------------- +TC - 16-bit Timer/Counter With PWM +-------------------------------------------------------------------------- +*/ + +/* 16-bit Timer/Counter 4 */ +typedef struct TC4_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + _WORDREGISTER(CCC); /* Compare or Capture C */ + _WORDREGISTER(CCD); /* Compare or Capture D */ + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ + _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +} TC4_t; + + +/* 16-bit Timer/Counter 5 */ +typedef struct TC5_struct +{ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control register C */ + register8_t CTRLD; /* Control Register D */ + register8_t CTRLE; /* Control Register E */ + register8_t CTRLF; /* Control Register F */ + register8_t INTCTRLA; /* Interrupt Control Register A */ + register8_t INTCTRLB; /* Interrupt Control Register B */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G Set */ + register8_t CTRLHCLR; /* Control Register H Clear */ + register8_t CTRLHSET; /* Control Register H Set */ + register8_t INTFLAGS; /* Interrupt Flag Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t TEMP; /* Temporary Register For 16-bit Access */ + register8_t reserved_0x10; + register8_t reserved_0x11; + register8_t reserved_0x12; + register8_t reserved_0x13; + register8_t reserved_0x14; + register8_t reserved_0x15; + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t reserved_0x1E; + register8_t reserved_0x1F; + _WORDREGISTER(CNT); /* Count */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + _WORDREGISTER(PER); /* Period */ + _WORDREGISTER(CCA); /* Compare or Capture A */ + _WORDREGISTER(CCB); /* Compare or Capture B */ + register8_t reserved_0x2C; + register8_t reserved_0x2D; + register8_t reserved_0x2E; + register8_t reserved_0x2F; + register8_t reserved_0x30; + register8_t reserved_0x31; + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t reserved_0x34; + register8_t reserved_0x35; + _WORDREGISTER(PERBUF); /* Period Buffer */ + _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ + _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} TC5_t; + +/* Clock Selection */ +typedef enum TC45_CLKSEL_enum +{ + TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ + TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ + TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ + TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ + TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ + TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ + TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ + TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ + TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_CLKSEL_t; + +/* Byte Mode */ +typedef enum TC45_BYTEM_enum +{ + TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ + TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ +} TC45_BYTEM_t; + +/* Circular Enable Mode */ +typedef enum TC45_CIRCEN_enum +{ + TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ + TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ + TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ + TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ +} TC45_CIRCEN_t; + +/* Waveform Generation Mode */ +typedef enum TC45_WGMODE_enum +{ + TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ + TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ + TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ + TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ + TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ + TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +} TC45_WGMODE_t; + +/* Event Action */ +typedef enum TC45_EVACT_enum +{ + TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ + TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ + TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ + TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ + TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ + TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ + TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ +} TC45_EVACT_t; + +/* Event Selection */ +typedef enum TC45_EVSEL_enum +{ + TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ + TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ + TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ + TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ + TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ + TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ + TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ + TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +} TC45_EVSEL_t; + +/* Compare or Capture Channel A Mode */ +typedef enum TC45_CCAMODE_enum +{ + TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_CCAMODE_t; + +/* Compare or Capture Channel B Mode */ +typedef enum TC45_CCBMODE_enum +{ + TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_CCBMODE_t; + +/* Compare or Capture Channel C Mode */ +typedef enum TC45_CCCMODE_enum +{ + TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_CCCMODE_t; + +/* Compare or Capture Channel D Mode */ +typedef enum TC45_CCDMODE_enum +{ + TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_CCDMODE_t; + +/* Compare or Capture Low Channel A Mode */ +typedef enum TC45_LCCAMODE_enum +{ + TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_LCCAMODE_t; + +/* Compare or Capture Low Channel B Mode */ +typedef enum TC45_LCCBMODE_enum +{ + TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_LCCBMODE_t; + +/* Compare or Capture Low Channel C Mode */ +typedef enum TC45_LCCCMODE_enum +{ + TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_LCCCMODE_t; + +/* Compare or Capture Low Channel D Mode */ +typedef enum TC45_LCCDMODE_enum +{ + TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_LCCDMODE_t; + +/* Compare or Capture High Channel A Mode */ +typedef enum TC45_HCCAMODE_enum +{ + TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ + TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ + TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ + TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ +} TC45_HCCAMODE_t; + +/* Compare or Capture High Channel B Mode */ +typedef enum TC45_HCCBMODE_enum +{ + TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ + TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ + TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ + TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ +} TC45_HCCBMODE_t; + +/* Compare or Capture High Channel C Mode */ +typedef enum TC45_HCCCMODE_enum +{ + TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ + TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ + TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ + TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ +} TC45_HCCCMODE_t; + +/* Compare or Capture High Channel D Mode */ +typedef enum TC45_HCCDMODE_enum +{ + TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ + TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ + TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ + TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ +} TC45_HCCDMODE_t; + +/* Timer Trigger Restart Interrupt Level */ +typedef enum TC45_TRGINTLVL_enum +{ + TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_TRGINTLVL_t; + +/* Error Interrupt Level */ +typedef enum TC45_ERRINTLVL_enum +{ + TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_ERRINTLVL_t; + +/* Overflow Interrupt Level */ +typedef enum TC45_OVFINTLVL_enum +{ + TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_OVFINTLVL_t; + +/* Compare or Capture Channel A Interrupt Level */ +typedef enum TC45_CCAINTLVL_enum +{ + TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_CCAINTLVL_t; + +/* Compare or Capture Channel B Interrupt Level */ +typedef enum TC45_CCBINTLVL_enum +{ + TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_CCBINTLVL_t; + +/* Compare or Capture Channel C Interrupt Level */ +typedef enum TC45_CCCINTLVL_enum +{ + TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_CCCINTLVL_t; + +/* Compare or Capture Channel D Interrupt Level */ +typedef enum TC45_CCDINTLVL_enum +{ + TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_CCDINTLVL_t; + +/* Compare or Capture Low Channel A Interrupt Level */ +typedef enum TC45_LCCAINTLVL_enum +{ + TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ + TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +} TC45_LCCAINTLVL_t; + +/* Compare or Capture Low Channel B Interrupt Level */ +typedef enum TC45_LCCBINTLVL_enum +{ + TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ + TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +} TC45_LCCBINTLVL_t; + +/* Compare or Capture Low Channel C Interrupt Level */ +typedef enum TC45_LCCCINTLVL_enum +{ + TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} TC45_LCCCINTLVL_t; + +/* Compare or Capture Low Channel D Interrupt Level */ +typedef enum TC45_LCCDINTLVL_enum +{ + TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ + TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ + TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ + TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +} TC45_LCCDINTLVL_t; + +/* Timer/Counter Command */ +typedef enum TC45_CMD_enum +{ + TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ + TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ + TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ + TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +} TC45_CMD_t; + + +/* +-------------------------------------------------------------------------- +FAULT - Fault Extension +-------------------------------------------------------------------------- +*/ + +/* Fault Extension */ +typedef struct FAULT_struct +{ + register8_t CTRLA; /* Control A Register */ + register8_t CTRLB; /* Control B Register */ + register8_t CTRLC; /* Control C Register */ + register8_t CTRLD; /* Control D Register */ + register8_t CTRLE; /* Control E Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLGCLR; /* Control Register G Clear */ + register8_t CTRLGSET; /* Control Register G set */ +} FAULT_t; + +/* Ramp Mode Selection */ +typedef enum FAULT_RAMP_enum +{ + FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ + FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ +} FAULT_RAMP_t; + +/* Fault E Input Source Selection */ +typedef enum FAULT_SRCE_enum +{ + FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ + FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ +} FAULT_SRCE_t; + +/* Fault A Halt Action Selection */ +typedef enum FAULT_HALTA_enum +{ + FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTA_t; + +/* Fault A Source Selection */ +typedef enum FAULT_SRCA_enum +{ + FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ + FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ +} FAULT_SRCA_t; + +/* Fault B Halt Action Selection */ +typedef enum FAULT_HALTB_enum +{ + FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ + FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ + FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ +} FAULT_HALTB_t; + +/* Fault B Source Selection */ +typedef enum FAULT_SRCB_enum +{ + FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ + FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ + FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ + FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ +} FAULT_SRCB_t; + +/* Channel index Command */ +typedef enum FAULT_IDXCMD_enum +{ + FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ + FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ + FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ + FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ +} FAULT_IDXCMD_t; + + +/* +-------------------------------------------------------------------------- +WEX - Waveform Extension +-------------------------------------------------------------------------- +*/ + +/* Waveform Extension */ +typedef struct WEX_struct +{ + register8_t CTRL; /* Control Register */ + register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ + register8_t DTLS; /* Dead-time Low Side Register */ + register8_t DTHS; /* Dead-time High Side Register */ + register8_t STATUSCLR; /* Status Clear Register */ + register8_t STATUSSET; /* Status Set Register */ + register8_t SWAP; /* Swap Register */ + register8_t PGO; /* Pattern Generation Override Register */ + register8_t PGV; /* Pattern Generation Value Register */ + register8_t reserved_0x09; + register8_t SWAPBUF; /* Dead Time Low Side Buffer */ + register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ + register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ + register8_t reserved_0x0D; + register8_t reserved_0x0E; + register8_t OUTOVDIS; /* Output Override Disable Register */ +} WEX_t; + +/* Output Matrix Mode */ +typedef enum WEX_OTMX_enum +{ + WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ + WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ + WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ + WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ + WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ +} WEX_OTMX_t; + + +/* +-------------------------------------------------------------------------- +HIRES - High-Resolution Extension +-------------------------------------------------------------------------- +*/ + +/* High-Resolution Extension */ +typedef struct HIRES_struct +{ + register8_t CTRLA; /* Control Register A */ +} HIRES_t; + +/* High Resolution Plus Mode */ +typedef enum HIRES_HRPLUS_enum +{ + HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ + HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ + HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ + HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ +} HIRES_HRPLUS_t; + +/* High Resolution Mode */ +typedef enum HIRES_HREN_enum +{ + HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ + HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ + HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ + HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ +} HIRES_HREN_t; + + +/* +-------------------------------------------------------------------------- +USART - Universal Asynchronous Receiver-Transmitter +-------------------------------------------------------------------------- +*/ + +/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +typedef struct USART_struct +{ + register8_t DATA; /* Data Register */ + register8_t STATUS; /* Status Register */ + register8_t CTRLA; /* Control Register A */ + register8_t CTRLB; /* Control Register B */ + register8_t CTRLC; /* Control Register C */ + register8_t CTRLD; /* Control Register D */ + register8_t BAUDCTRLA; /* Baud Rate Control Register A */ + register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +} USART_t; + +/* Receive Start Interrupt level */ +typedef enum USART_RXSINTLVL_enum +{ + USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_RXSINTLVL_t; + +/* Receive Complete Interrupt level */ +typedef enum USART_RXCINTLVL_enum +{ + USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ + USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ + USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ + USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +} USART_RXCINTLVL_t; + +/* Transmit Complete Interrupt level */ +typedef enum USART_TXCINTLVL_enum +{ + USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ + USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ + USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ + USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +} USART_TXCINTLVL_t; + +/* Data Register Empty Interrupt level */ +typedef enum USART_DREINTLVL_enum +{ + USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ + USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ + USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +} USART_DREINTLVL_t; + +/* Character Size */ +typedef enum USART_CHSIZE_enum +{ + USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ + USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ + USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ + USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ + USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +} USART_CHSIZE_t; + +/* Communication Mode */ +typedef enum USART_CMODE_enum +{ + USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ + USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ + USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ + USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +} USART_CMODE_t; + +/* Parity Mode */ +typedef enum USART_PMODE_enum +{ + USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ + USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ + USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +} USART_PMODE_t; + +/* Encoding and Decoding Type */ +typedef enum USART_DECTYPE_enum +{ + USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ + USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ + USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ +} USART_DECTYPE_t; + +/* XCL LUT Action */ +typedef enum USART_LUTACT_enum +{ + USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ + USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ + USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ + USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ +} USART_LUTACT_t; + +/* XCL Peripheral Counter Action */ +typedef enum USART_PECACT_enum +{ + USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ + USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ + USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ + USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ +} USART_PECACT_t; + + +/* +-------------------------------------------------------------------------- +SPI - Serial Peripheral Interface +-------------------------------------------------------------------------- +*/ + +/* Serial Peripheral Interface with Buffer Modes */ +typedef struct SPI_struct +{ + register8_t CTRL; /* Control Register */ + register8_t INTCTRL; /* Interrupt Control Register */ + register8_t STATUS; /* Status Register */ + register8_t DATA; /* Data Register */ + register8_t CTRLB; /* Control Register B */ +} SPI_t; + +/* SPI Mode */ +typedef enum SPI_MODE_enum +{ + SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ + SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ + SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ + SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ +} SPI_MODE_t; + +/* Prescaler setting */ +typedef enum SPI_PRESCALER_enum +{ + SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ + SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ + SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ + SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ +} SPI_PRESCALER_t; + +/* Interrupt level */ +typedef enum SPI_INTLVL_enum +{ + SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ + SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ + SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ + SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +} SPI_INTLVL_t; + +/* Buffer Modes */ +typedef enum SPI_BUFMODE_enum +{ + SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ + SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ + SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ +} SPI_BUFMODE_t; + + +/* +-------------------------------------------------------------------------- +IRCOM - IR Communication Module +-------------------------------------------------------------------------- +*/ + +/* IR Communication Module */ +typedef struct IRCOM_struct +{ + register8_t CTRL; /* Control Register */ + register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ + register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +} IRCOM_t; + +/* Event channel selection */ +typedef enum IRDA_EVSEL_enum +{ + IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ + IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ + IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ + IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ + IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ + IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ + IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ + IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ + IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +} IRDA_EVSEL_t; + + +/* +-------------------------------------------------------------------------- +FUSE - Fuses and Lockbits +-------------------------------------------------------------------------- +*/ + +/* Lock Bits */ +typedef struct NVM_LOCKBITS_struct +{ + register8_t LOCK_BITS; /* Lock Bits (Changed from LOCKBITS to avoid avr-libc collision) */ +} NVM_LOCKBITS_t; + + +/* Fuses */ +typedef struct NVM_FUSES_struct +{ + register8_t reserved_0x00; + register8_t FUSEBYTE1; /* Watchdog Configuration */ + register8_t FUSEBYTE2; /* Reset Configuration */ + register8_t reserved_0x03; + register8_t FUSEBYTE4; /* Start-up Configuration */ + register8_t FUSEBYTE5; /* EESAVE and BOD Level */ + register8_t FUSEBYTE6; /* Fault State */ +} NVM_FUSES_t; + +/* Boot lock bits - boot setcion */ +typedef enum FUSE_BLBB_enum +{ + FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ + FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ + FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ + FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +} FUSE_BLBB_t; + +/* Boot lock bits - application section */ +typedef enum FUSE_BLBA_enum +{ + FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ + FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ + FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ + FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +} FUSE_BLBA_t; + +/* Boot lock bits - application table section */ +typedef enum FUSE_BLBAT_enum +{ + FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ + FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ + FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ + FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +} FUSE_BLBAT_t; + +/* Lock bits */ +typedef enum FUSE_LB_enum +{ + FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ + FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ + FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +} FUSE_LB_t; + +/* Boot Loader Section Reset Vector */ +typedef enum BOOTRST_enum +{ + BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ + BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +} BOOTRST_t; + +/* BOD operation */ +typedef enum BOD_enum +{ + BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ + BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ + BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ +} BOD_t; + +/* Watchdog (Window) Timeout Period */ +typedef enum WD_enum +{ + WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ + WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ + WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ + WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ + WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ + WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ + WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ + WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ + WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ + WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ + WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +} WD_t; + +/* Start-up Time */ +typedef enum SUT_enum +{ + SUT_0MS_gc = (0x03<<2), /* 0 ms */ + SUT_4MS_gc = (0x01<<2), /* 4 ms */ + SUT_64MS_gc = (0x00<<2), /* 64 ms */ +} SUT_t; + +/* Brownout Detection Voltage Level */ +typedef enum BODLVL_enum +{ + BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ + BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ + BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ + BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ + BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ + BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ + BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ + BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ +} BODLVL_t; + + +/* +-------------------------------------------------------------------------- +SIGROW - Signature Row +-------------------------------------------------------------------------- +*/ + +/* Production Signatures */ +typedef struct NVM_PROD_SIGNATURES_struct +{ + register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ + register8_t reserved_0x01; + register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ + register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ + register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ + register8_t reserved_0x05; + register8_t reserved_0x06; + register8_t reserved_0x07; + register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ + register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ + register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ + register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ + register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ + register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ + register8_t reserved_0x0E; + register8_t reserved_0x0F; + register8_t WAFNUM; /* Wafer Number */ + register8_t reserved_0x11; + register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ + register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ + register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ + register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ + register8_t reserved_0x16; + register8_t reserved_0x17; + register8_t reserved_0x18; + register8_t reserved_0x19; + register8_t reserved_0x1A; + register8_t reserved_0x1B; + register8_t reserved_0x1C; + register8_t reserved_0x1D; + register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ + register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ + register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ + register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ + register8_t reserved_0x22; + register8_t reserved_0x23; + register8_t reserved_0x24; + register8_t reserved_0x25; + register8_t reserved_0x26; + register8_t reserved_0x27; + register8_t ACACURRCAL; /* ACA Current Calibration Byte */ + register8_t reserved_0x29; + register8_t reserved_0x2A; + register8_t reserved_0x2B; + register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ + register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ + register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ + register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ + register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ + register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ + register8_t reserved_0x32; + register8_t reserved_0x33; + register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ + register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ + register8_t reserved_0x36; + register8_t reserved_0x37; + register8_t reserved_0x38; + register8_t reserved_0x39; + register8_t reserved_0x3A; + register8_t reserved_0x3B; + register8_t reserved_0x3C; + register8_t reserved_0x3D; + register8_t reserved_0x3E; + register8_t reserved_0x3F; +} NVM_PROD_SIGNATURES_t; + +/* +========================================================================== +IO Module Instances. Mapped to memory. +========================================================================== +*/ + +#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ +#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ +#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ +#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ +#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ +#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ +#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +#define RST (*(RST_t *) 0x0078) /* Reset */ +#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ +#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ +#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ +#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ +#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ +#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ +#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ +#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ +#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ +#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ +#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ +#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ +#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ +#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ +#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ +#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ +#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ +#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ +#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ +#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ +#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ +#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ +#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ + + +#endif /* !defined (__ASSEMBLER__) */ + + +/* ========== Flattened fully qualified IO register names ========== */ + +/* GPIO - General Purpose IO Registers */ +#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +#define GPIO_GPIOR3 _SFR_MEM8(0x0003) + +/* Deprecated */ +#define GPIO_GPIO0 _SFR_MEM8(0x0000) +#define GPIO_GPIO1 _SFR_MEM8(0x0001) +#define GPIO_GPIO2 _SFR_MEM8(0x0002) +#define GPIO_GPIO3 _SFR_MEM8(0x0003) + +/* NVM_FUSES - Fuses */ +#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) +#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) +#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) +#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) +#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) + +/* NVM_LOCKBITS - Lock Bits */ +#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) + +/* NVM_PROD_SIGNATURES - Production Signatures */ +#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) +#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) +#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) +#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) +#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) +#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) +#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) +#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) +#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) +#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) +#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) +#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) +#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) +#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) +#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) +#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) +#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) +#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) +#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) +#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) +#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) +#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) +#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) +#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) +#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) +#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) +#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) +#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) + +/* VPORT - Virtual Port */ +#define VPORT0_DIR _SFR_MEM8(0x0010) +#define VPORT0_OUT _SFR_MEM8(0x0011) +#define VPORT0_IN _SFR_MEM8(0x0012) +#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) + +/* VPORT - Virtual Port */ +#define VPORT1_DIR _SFR_MEM8(0x0014) +#define VPORT1_OUT _SFR_MEM8(0x0015) +#define VPORT1_IN _SFR_MEM8(0x0016) +#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) + +/* VPORT - Virtual Port */ +#define VPORT2_DIR _SFR_MEM8(0x0018) +#define VPORT2_OUT _SFR_MEM8(0x0019) +#define VPORT2_IN _SFR_MEM8(0x001A) +#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) + +/* VPORT - Virtual Port */ +#define VPORT3_DIR _SFR_MEM8(0x001C) +#define VPORT3_OUT _SFR_MEM8(0x001D) +#define VPORT3_IN _SFR_MEM8(0x001E) +#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) + +/* OCD - On-Chip Debug System */ +#define OCD_OCDR0 _SFR_MEM8(0x002E) +#define OCD_OCDR1 _SFR_MEM8(0x002F) + +/* CPU - CPU registers */ +#define CPU_CCP _SFR_MEM8(0x0034) +#define CPU_RAMPD _SFR_MEM8(0x0038) +#define CPU_RAMPX _SFR_MEM8(0x0039) +#define CPU_RAMPY _SFR_MEM8(0x003A) +#define CPU_RAMPZ _SFR_MEM8(0x003B) +#define CPU_EIND _SFR_MEM8(0x003C) +#define CPU_SPL _SFR_MEM8(0x003D) +#define CPU_SPH _SFR_MEM8(0x003E) +#define CPU_SREG _SFR_MEM8(0x003F) + +/* CLK - Clock System */ +#define CLK_CTRL _SFR_MEM8(0x0040) +#define CLK_PSCTRL _SFR_MEM8(0x0041) +#define CLK_LOCK _SFR_MEM8(0x0042) +#define CLK_RTCCTRL _SFR_MEM8(0x0043) + +/* SLEEP - Sleep Controller */ +#define SLEEP_CTRL _SFR_MEM8(0x0048) + +/* OSC - Oscillator */ +#define OSC_CTRL _SFR_MEM8(0x0050) +#define OSC_STATUS _SFR_MEM8(0x0051) +#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +#define OSC_RC32KCAL _SFR_MEM8(0x0054) +#define OSC_PLLCTRL _SFR_MEM8(0x0055) +#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +#define OSC_RC8MCAL _SFR_MEM8(0x0057) + +/* DFLL - DFLL */ +#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) + +/* PR - Power Reduction */ +#define PR_PRGEN _SFR_MEM8(0x0070) +#define PR_PRPA _SFR_MEM8(0x0071) +#define PR_PRPC _SFR_MEM8(0x0073) +#define PR_PRPD _SFR_MEM8(0x0074) + +/* RST - Reset */ +#define RST_STATUS _SFR_MEM8(0x0078) +#define RST_CTRL _SFR_MEM8(0x0079) + +/* WDT - Watch-Dog Timer */ +#define WDT_CTRL _SFR_MEM8(0x0080) +#define WDT_WINCTRL _SFR_MEM8(0x0081) +#define WDT_STATUS _SFR_MEM8(0x0082) + +/* MCU - MCU Control */ +#define MCU_DEVID0 _SFR_MEM8(0x0090) +#define MCU_DEVID1 _SFR_MEM8(0x0091) +#define MCU_DEVID2 _SFR_MEM8(0x0092) +#define MCU_REVID _SFR_MEM8(0x0093) +#define MCU_ANAINIT _SFR_MEM8(0x0097) +#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +#define MCU_WEXLOCK _SFR_MEM8(0x0099) +#define MCU_FAULTLOCK _SFR_MEM8(0x009A) + +/* PMIC - Programmable Multi-level Interrupt Controller */ +#define PMIC_STATUS _SFR_MEM8(0x00A0) +#define PMIC_INTPRI _SFR_MEM8(0x00A1) +#define PMIC_CTRL _SFR_MEM8(0x00A2) + +/* PORTCFG - I/O port Configuration */ +#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) +#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) +#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) + +/* CRC - Cyclic Redundancy Checker */ +#define CRC_CTRL _SFR_MEM8(0x00D0) +#define CRC_STATUS _SFR_MEM8(0x00D1) +#define CRC_DATAIN _SFR_MEM8(0x00D3) +#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) + +/* EDMA - Enhanced DMA Controller */ +#define EDMA_CTRL _SFR_MEM8(0x0100) +#define EDMA_INTFLAGS _SFR_MEM8(0x0103) +#define EDMA_STATUS _SFR_MEM8(0x0104) +#define EDMA_TEMP _SFR_MEM8(0x0106) +#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) +#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) +#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) +#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) +#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) +#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) +#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) +#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) +#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) +#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) +#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) +#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) +#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) +#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) +#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) +#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) +#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) +#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) +#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) +#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) +#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) +#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) +#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) +#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) +#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) +#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) +#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) +#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) + +/* EVSYS - Event System */ +#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +#define EVSYS_STROBE _SFR_MEM8(0x0190) +#define EVSYS_DATA _SFR_MEM8(0x0191) +#define EVSYS_DFCTRL _SFR_MEM8(0x0192) + +/* NVM - Non-volatile Memory Controller */ +#define NVM_ADDR0 _SFR_MEM8(0x01C0) +#define NVM_ADDR1 _SFR_MEM8(0x01C1) +#define NVM_ADDR2 _SFR_MEM8(0x01C2) +#define NVM_DATA0 _SFR_MEM8(0x01C4) +#define NVM_DATA1 _SFR_MEM8(0x01C5) +#define NVM_DATA2 _SFR_MEM8(0x01C6) +#define NVM_CMD _SFR_MEM8(0x01CA) +#define NVM_CTRLA _SFR_MEM8(0x01CB) +#define NVM_CTRLB _SFR_MEM8(0x01CC) +#define NVM_INTCTRL _SFR_MEM8(0x01CD) +#define NVM_STATUS _SFR_MEM8(0x01CF) +#define NVM_LOCKBITS _SFR_MEM8(0x01D0) + +/* ADC - Analog-to-Digital Converter */ +#define ADCA_CTRLA _SFR_MEM8(0x0200) +#define ADCA_CTRLB _SFR_MEM8(0x0201) +#define ADCA_REFCTRL _SFR_MEM8(0x0202) +#define ADCA_EVCTRL _SFR_MEM8(0x0203) +#define ADCA_PRESCALER _SFR_MEM8(0x0204) +#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +#define ADCA_TEMP _SFR_MEM8(0x0207) +#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) +#define ADCA_CAL _SFR_MEM16(0x020C) +#define ADCA_CH0RES _SFR_MEM16(0x0210) +#define ADCA_CMP _SFR_MEM16(0x0218) +#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +#define ADCA_CH0_RES _SFR_MEM16(0x0224) +#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) +#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) +#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) +#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) +#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) +#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) +#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) + +/* DAC - Digital-to-Analog Converter */ +#define DACA_CTRLA _SFR_MEM8(0x0300) +#define DACA_CTRLB _SFR_MEM8(0x0301) +#define DACA_CTRLC _SFR_MEM8(0x0302) +#define DACA_EVCTRL _SFR_MEM8(0x0303) +#define DACA_STATUS _SFR_MEM8(0x0305) +#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +#define DACA_CH0DATA _SFR_MEM16(0x0318) +#define DACA_CH1DATA _SFR_MEM16(0x031A) + +/* AC - Analog Comparator */ +#define ACA_AC0CTRL _SFR_MEM8(0x0380) +#define ACA_AC1CTRL _SFR_MEM8(0x0381) +#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +#define ACA_CTRLA _SFR_MEM8(0x0384) +#define ACA_CTRLB _SFR_MEM8(0x0385) +#define ACA_WINCTRL _SFR_MEM8(0x0386) +#define ACA_STATUS _SFR_MEM8(0x0387) +#define ACA_CURRCTRL _SFR_MEM8(0x0388) +#define ACA_CURRCALIB _SFR_MEM8(0x0389) + +/* RTC - Real-Time Counter */ +#define RTC_CTRL _SFR_MEM8(0x0400) +#define RTC_STATUS _SFR_MEM8(0x0401) +#define RTC_INTCTRL _SFR_MEM8(0x0402) +#define RTC_INTFLAGS _SFR_MEM8(0x0403) +#define RTC_TEMP _SFR_MEM8(0x0404) +#define RTC_CALIB _SFR_MEM8(0x0406) +#define RTC_CNT _SFR_MEM16(0x0408) +#define RTC_PER _SFR_MEM16(0x040A) +#define RTC_COMP _SFR_MEM16(0x040C) + +/* XCL - XMEGA Custom Logic */ +#define XCL_CTRLA _SFR_MEM8(0x0460) +#define XCL_CTRLB _SFR_MEM8(0x0461) +#define XCL_CTRLC _SFR_MEM8(0x0462) +#define XCL_CTRLD _SFR_MEM8(0x0463) +#define XCL_CTRLE _SFR_MEM8(0x0464) +#define XCL_CTRLF _SFR_MEM8(0x0465) +#define XCL_CTRLG _SFR_MEM8(0x0466) +#define XCL_INTCTRL _SFR_MEM8(0x0467) +#define XCL_INTFLAGS _SFR_MEM8(0x0468) +#define XCL_PLC _SFR_MEM8(0x0469) +#define XCL_CNTL _SFR_MEM8(0x046A) +#define XCL_CNTH _SFR_MEM8(0x046B) +#define XCL_CMPL _SFR_MEM8(0x046C) +#define XCL_CMPH _SFR_MEM8(0x046D) +#define XCL_PERCAPTL _SFR_MEM8(0x046E) +#define XCL_PERCAPTH _SFR_MEM8(0x046F) + +/* TWI - Two-Wire Interface */ +#define TWIC_CTRL _SFR_MEM8(0x0480) +#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) +#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) + +/* PORT - I/O Ports */ +#define PORTA_DIR _SFR_MEM8(0x0600) +#define PORTA_DIRSET _SFR_MEM8(0x0601) +#define PORTA_DIRCLR _SFR_MEM8(0x0602) +#define PORTA_DIRTGL _SFR_MEM8(0x0603) +#define PORTA_OUT _SFR_MEM8(0x0604) +#define PORTA_OUTSET _SFR_MEM8(0x0605) +#define PORTA_OUTCLR _SFR_MEM8(0x0606) +#define PORTA_OUTTGL _SFR_MEM8(0x0607) +#define PORTA_IN _SFR_MEM8(0x0608) +#define PORTA_INTCTRL _SFR_MEM8(0x0609) +#define PORTA_INTMASK _SFR_MEM8(0x060A) +#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +#define PORTA_REMAP _SFR_MEM8(0x060E) +#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) + +/* PORT - I/O Ports */ +#define PORTC_DIR _SFR_MEM8(0x0640) +#define PORTC_DIRSET _SFR_MEM8(0x0641) +#define PORTC_DIRCLR _SFR_MEM8(0x0642) +#define PORTC_DIRTGL _SFR_MEM8(0x0643) +#define PORTC_OUT _SFR_MEM8(0x0644) +#define PORTC_OUTSET _SFR_MEM8(0x0645) +#define PORTC_OUTCLR _SFR_MEM8(0x0646) +#define PORTC_OUTTGL _SFR_MEM8(0x0647) +#define PORTC_IN _SFR_MEM8(0x0648) +#define PORTC_INTCTRL _SFR_MEM8(0x0649) +#define PORTC_INTMASK _SFR_MEM8(0x064A) +#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +#define PORTC_REMAP _SFR_MEM8(0x064E) +#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) + +/* PORT - I/O Ports */ +#define PORTD_DIR _SFR_MEM8(0x0660) +#define PORTD_DIRSET _SFR_MEM8(0x0661) +#define PORTD_DIRCLR _SFR_MEM8(0x0662) +#define PORTD_DIRTGL _SFR_MEM8(0x0663) +#define PORTD_OUT _SFR_MEM8(0x0664) +#define PORTD_OUTSET _SFR_MEM8(0x0665) +#define PORTD_OUTCLR _SFR_MEM8(0x0666) +#define PORTD_OUTTGL _SFR_MEM8(0x0667) +#define PORTD_IN _SFR_MEM8(0x0668) +#define PORTD_INTCTRL _SFR_MEM8(0x0669) +#define PORTD_INTMASK _SFR_MEM8(0x066A) +#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +#define PORTD_REMAP _SFR_MEM8(0x066E) +#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) + +/* PORT - I/O Ports */ +#define PORTR_DIR _SFR_MEM8(0x07E0) +#define PORTR_DIRSET _SFR_MEM8(0x07E1) +#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +#define PORTR_OUT _SFR_MEM8(0x07E4) +#define PORTR_OUTSET _SFR_MEM8(0x07E5) +#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +#define PORTR_IN _SFR_MEM8(0x07E8) +#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +#define PORTR_INTMASK _SFR_MEM8(0x07EA) +#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +#define PORTR_REMAP _SFR_MEM8(0x07EE) +#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) + +/* TC4 - 16-bit Timer/Counter 4 */ +#define TCC4_CTRLA _SFR_MEM8(0x0800) +#define TCC4_CTRLB _SFR_MEM8(0x0801) +#define TCC4_CTRLC _SFR_MEM8(0x0802) +#define TCC4_CTRLD _SFR_MEM8(0x0803) +#define TCC4_CTRLE _SFR_MEM8(0x0804) +#define TCC4_CTRLF _SFR_MEM8(0x0805) +#define TCC4_INTCTRLA _SFR_MEM8(0x0806) +#define TCC4_INTCTRLB _SFR_MEM8(0x0807) +#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) +#define TCC4_CTRLGSET _SFR_MEM8(0x0809) +#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) +#define TCC4_CTRLHSET _SFR_MEM8(0x080B) +#define TCC4_INTFLAGS _SFR_MEM8(0x080C) +#define TCC4_TEMP _SFR_MEM8(0x080F) +#define TCC4_CNT _SFR_MEM16(0x0820) +#define TCC4_PER _SFR_MEM16(0x0826) +#define TCC4_CCA _SFR_MEM16(0x0828) +#define TCC4_CCB _SFR_MEM16(0x082A) +#define TCC4_CCC _SFR_MEM16(0x082C) +#define TCC4_CCD _SFR_MEM16(0x082E) +#define TCC4_PERBUF _SFR_MEM16(0x0836) +#define TCC4_CCABUF _SFR_MEM16(0x0838) +#define TCC4_CCBBUF _SFR_MEM16(0x083A) +#define TCC4_CCCBUF _SFR_MEM16(0x083C) +#define TCC4_CCDBUF _SFR_MEM16(0x083E) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCC5_CTRLA _SFR_MEM8(0x0840) +#define TCC5_CTRLB _SFR_MEM8(0x0841) +#define TCC5_CTRLC _SFR_MEM8(0x0842) +#define TCC5_CTRLD _SFR_MEM8(0x0843) +#define TCC5_CTRLE _SFR_MEM8(0x0844) +#define TCC5_CTRLF _SFR_MEM8(0x0845) +#define TCC5_INTCTRLA _SFR_MEM8(0x0846) +#define TCC5_INTCTRLB _SFR_MEM8(0x0847) +#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) +#define TCC5_CTRLGSET _SFR_MEM8(0x0849) +#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) +#define TCC5_CTRLHSET _SFR_MEM8(0x084B) +#define TCC5_INTFLAGS _SFR_MEM8(0x084C) +#define TCC5_TEMP _SFR_MEM8(0x084F) +#define TCC5_CNT _SFR_MEM16(0x0860) +#define TCC5_PER _SFR_MEM16(0x0866) +#define TCC5_CCA _SFR_MEM16(0x0868) +#define TCC5_CCB _SFR_MEM16(0x086A) +#define TCC5_PERBUF _SFR_MEM16(0x0876) +#define TCC5_CCABUF _SFR_MEM16(0x0878) +#define TCC5_CCBBUF _SFR_MEM16(0x087A) + +/* FAULT - Fault Extension */ +#define FAULTC4_CTRLA _SFR_MEM8(0x0880) +#define FAULTC4_CTRLB _SFR_MEM8(0x0881) +#define FAULTC4_CTRLC _SFR_MEM8(0x0882) +#define FAULTC4_CTRLD _SFR_MEM8(0x0883) +#define FAULTC4_CTRLE _SFR_MEM8(0x0884) +#define FAULTC4_STATUS _SFR_MEM8(0x0885) +#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) +#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) + +/* FAULT - Fault Extension */ +#define FAULTC5_CTRLA _SFR_MEM8(0x0890) +#define FAULTC5_CTRLB _SFR_MEM8(0x0891) +#define FAULTC5_CTRLC _SFR_MEM8(0x0892) +#define FAULTC5_CTRLD _SFR_MEM8(0x0893) +#define FAULTC5_CTRLE _SFR_MEM8(0x0894) +#define FAULTC5_STATUS _SFR_MEM8(0x0895) +#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) +#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) + +/* WEX - Waveform Extension */ +#define WEXC_CTRL _SFR_MEM8(0x08A0) +#define WEXC_DTBOTH _SFR_MEM8(0x08A1) +#define WEXC_DTLS _SFR_MEM8(0x08A2) +#define WEXC_DTHS _SFR_MEM8(0x08A3) +#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) +#define WEXC_STATUSSET _SFR_MEM8(0x08A5) +#define WEXC_SWAP _SFR_MEM8(0x08A6) +#define WEXC_PGO _SFR_MEM8(0x08A7) +#define WEXC_PGV _SFR_MEM8(0x08A8) +#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) +#define WEXC_PGOBUF _SFR_MEM8(0x08AB) +#define WEXC_PGVBUF _SFR_MEM8(0x08AC) +#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) + +/* HIRES - High-Resolution Extension */ +#define HIRESC_CTRLA _SFR_MEM8(0x08B0) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTC0_DATA _SFR_MEM8(0x08C0) +#define USARTC0_STATUS _SFR_MEM8(0x08C1) +#define USARTC0_CTRLA _SFR_MEM8(0x08C2) +#define USARTC0_CTRLB _SFR_MEM8(0x08C3) +#define USARTC0_CTRLC _SFR_MEM8(0x08C4) +#define USARTC0_CTRLD _SFR_MEM8(0x08C5) +#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) +#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) + +/* SPI - Serial Peripheral Interface with Buffer Modes */ +#define SPIC_CTRL _SFR_MEM8(0x08E0) +#define SPIC_INTCTRL _SFR_MEM8(0x08E1) +#define SPIC_STATUS _SFR_MEM8(0x08E2) +#define SPIC_DATA _SFR_MEM8(0x08E3) +#define SPIC_CTRLB _SFR_MEM8(0x08E4) + +/* IRCOM - IR Communication Module */ +#define IRCOM_CTRL _SFR_MEM8(0x08F8) +#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) + +/* TC5 - 16-bit Timer/Counter 5 */ +#define TCD5_CTRLA _SFR_MEM8(0x0940) +#define TCD5_CTRLB _SFR_MEM8(0x0941) +#define TCD5_CTRLC _SFR_MEM8(0x0942) +#define TCD5_CTRLD _SFR_MEM8(0x0943) +#define TCD5_CTRLE _SFR_MEM8(0x0944) +#define TCD5_CTRLF _SFR_MEM8(0x0945) +#define TCD5_INTCTRLA _SFR_MEM8(0x0946) +#define TCD5_INTCTRLB _SFR_MEM8(0x0947) +#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) +#define TCD5_CTRLGSET _SFR_MEM8(0x0949) +#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) +#define TCD5_CTRLHSET _SFR_MEM8(0x094B) +#define TCD5_INTFLAGS _SFR_MEM8(0x094C) +#define TCD5_TEMP _SFR_MEM8(0x094F) +#define TCD5_CNT _SFR_MEM16(0x0960) +#define TCD5_PER _SFR_MEM16(0x0966) +#define TCD5_CCA _SFR_MEM16(0x0968) +#define TCD5_CCB _SFR_MEM16(0x096A) +#define TCD5_PERBUF _SFR_MEM16(0x0976) +#define TCD5_CCABUF _SFR_MEM16(0x0978) +#define TCD5_CCBBUF _SFR_MEM16(0x097A) + +/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ +#define USARTD0_DATA _SFR_MEM8(0x09C0) +#define USARTD0_STATUS _SFR_MEM8(0x09C1) +#define USARTD0_CTRLA _SFR_MEM8(0x09C2) +#define USARTD0_CTRLB _SFR_MEM8(0x09C3) +#define USARTD0_CTRLC _SFR_MEM8(0x09C4) +#define USARTD0_CTRLD _SFR_MEM8(0x09C5) +#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) +#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) + + + +/*================== Bitfield Definitions ================== */ + +/* VPORT - Virtual Ports */ +/* VPORT.INTFLAGS bit masks and bit positions */ +#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ +#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ + +#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ +#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ + +#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ +#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ + +#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ +#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ + +#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ +#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ + +#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ +#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ + +#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ +#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ + +#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ +#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ + +/* XOCD - On-Chip Debug System */ +/* OCD.OCDR0 bit masks and bit positions */ +#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ +#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ +#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ +#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ +#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ +#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ +#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ +#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ +#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ +#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ +#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ +#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ +#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ +#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ +#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ +#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ +#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ +#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ + +/* OCD.OCDR1 bit masks and bit positions */ +/* OCD_OCDRD Predefined. */ +/* OCD_OCDRD Predefined. */ + +/* CPU - CPU */ +/* CPU.CCP bit masks and bit positions */ +#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +#define CPU_CCP_gp 0 /* CCP signature group position. */ +#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ + +/* CPU.SREG bit masks and bit positions */ +#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ + +#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +#define CPU_T_bp 6 /* Transfer Bit bit position. */ + +#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +#define CPU_H_bp 5 /* Half Carry Flag bit position. */ + +#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ + +#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ + +#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +#define CPU_N_bp 2 /* Negative Flag bit position. */ + +#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +#define CPU_Z_bp 1 /* Zero Flag bit position. */ + +#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +#define CPU_C_bp 0 /* Carry Flag bit position. */ + +/* CLK - Clock System */ +/* CLK.CTRL bit masks and bit positions */ +#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ + +/* CLK.PSCTRL bit masks and bit positions */ +#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ + +#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ + +/* CLK.LOCK bit masks and bit positions */ +#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ + +/* CLK.RTCCTRL bit masks and bit positions */ +#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ + +#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ + +/* PR.PRGEN bit masks and bit positions */ +#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ +#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ + +#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +#define PR_RTC_bp 2 /* Real-time Counter bit position. */ + +#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +#define PR_EVSYS_bp 1 /* Event System bit position. */ + +#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ +#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ + +/* PR.PRPA bit masks and bit positions */ +#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +#define PR_DAC_bp 2 /* Port A DAC bit position. */ + +#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +#define PR_ADC_bp 1 /* Port A ADC bit position. */ + +#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ + +/* PR.PRPC bit masks and bit positions */ +#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ + +#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +#define PR_USART0_bp 4 /* Port C USART0 bit position. */ + +#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +#define PR_SPI_bp 3 /* Port C SPI bit position. */ + +#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ +#define PR_HIRES_bp 2 /* Port C WEX bit position. */ + +#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ +#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ + +#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ +#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ + +/* PR.PRPD bit masks and bit positions */ +/* PR_USART0 Predefined. */ +/* PR_USART0 Predefined. */ + +/* PR_TC5 Predefined. */ +/* PR_TC5 Predefined. */ + +/* SLEEP - Sleep Controller */ +/* SLEEP.CTRL bit masks and bit positions */ +#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ + +#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ + +/* OSC - Oscillator */ +/* OSC.CTRL bit masks and bit positions */ +#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ +#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ + +#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ + +#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ + +#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ + +#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ + +#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ + +#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ + +/* OSC.STATUS bit masks and bit positions */ +#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ + +#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ + +#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ + +#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ + +#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ + +#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ + +/* OSC.XOSCCTRL bit masks and bit positions */ +#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ + +#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ + +#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ +#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ + +#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ +#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ +#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ + +/* OSC.XOSCFAIL bit masks and bit positions */ +#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ + +#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ + +#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ + +#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ + +/* OSC.PLLCTRL bit masks and bit positions */ +#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ + +#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ +#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ + +#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ + +/* OSC.DFLLCTRL bit masks and bit positions */ +#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ +#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ +#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ +#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ +#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ +#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ + +/* OSC.RC8MCAL bit masks and bit positions */ +#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ +#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ +#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ +#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ +#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ +#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ +#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ +#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ +#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ +#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ +#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ +#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ +#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ +#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ +#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ +#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ +#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ +#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ + +/* DFLL - DFLL */ +/* DFLL.CTRL bit masks and bit positions */ +#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ + +/* DFLL.CALA bit masks and bit positions */ +#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ + +/* DFLL.CALB bit masks and bit positions */ +#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ + +/* RST - Reset */ +/* RST.STATUS bit masks and bit positions */ +#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ + +#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ + +#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ + +#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ + +#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ + +#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ + +#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ + +/* RST.CTRL bit masks and bit positions */ +#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +#define RST_SWRST_bp 0 /* Software Reset bit position. */ + +/* WDT - Watch-Dog Timer */ +/* WDT.CTRL bit masks and bit positions */ +#define WDT_PER_gm 0x3C /* Period group mask. */ +#define WDT_PER_gp 2 /* Period group position. */ +#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +#define WDT_PER0_bp 2 /* Period bit 0 position. */ +#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +#define WDT_PER1_bp 3 /* Period bit 1 position. */ +#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +#define WDT_PER2_bp 4 /* Period bit 2 position. */ +#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +#define WDT_PER3_bp 5 /* Period bit 3 position. */ + +#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +#define WDT_ENABLE_bp 1 /* Enable bit position. */ + +#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +#define WDT_CEN_bp 0 /* Change Enable bit position. */ + +/* WDT.WINCTRL bit masks and bit positions */ +#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ + +#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ + +#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ + +/* WDT.STATUS bit masks and bit positions */ +#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ + +/* MCU - MCU Control */ +/* MCU.ANAINIT bit masks and bit positions */ +#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ +#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ +#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ +#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ +#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ +#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ + +/* MCU.EVSYSLOCK bit masks and bit positions */ +#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ + +#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ + +/* MCU.WEXLOCK bit masks and bit positions */ +#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ +#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ + +/* MCU.FAULTLOCK bit masks and bit positions */ +#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ +#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ + +#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ +#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ + +/* PMIC - Programmable Multi-level Interrupt Controller */ +/* PMIC.STATUS bit masks and bit positions */ +#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ + +#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ + +#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ + +#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ + +/* PMIC.INTPRI bit masks and bit positions */ +#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ +#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ +#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ +#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ +#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ +#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ +#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ +#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ +#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ +#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ +#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ +#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ +#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ +#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ +#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ +#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ +#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ +#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ + +/* PMIC.CTRL bit masks and bit positions */ +#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ + +#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ + +#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ + +#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ + +#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ + +/* PORTCFG - Port Configuration */ +/* PORTCFG.CLKOUT bit masks and bit positions */ +#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ +#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ + +#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ +#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ +#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ +#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ +#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ +#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ + +#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ +#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ +#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ +#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ +#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ +#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ + +#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ + +/* PORTCFG.ACEVOUT bit masks and bit positions */ +#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ +#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ +#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ +#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ +#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ +#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ + +#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ +#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ +#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ +#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ +#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ +#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ + +#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ +#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ + +#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ +#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ +#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ +#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ +#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ +#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ +#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ +#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ + +/* PORTCFG.SRLCTRL bit masks and bit positions */ +#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ +#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ + +#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ +#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ + +#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ +#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ + +#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ +#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ + +/* CRC - Cyclic Redundancy Checker */ +/* CRC.CTRL bit masks and bit positions */ +#define CRC_RESET_gm 0xC0 /* Reset group mask. */ +#define CRC_RESET_gp 6 /* Reset group position. */ +#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ +#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ +#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ +#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ + +#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ + +#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ +#define CRC_SOURCE_gp 0 /* Input Source group position. */ +#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ +#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ +#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ +#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ +#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ +#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ +#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ +#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ + +/* CRC.STATUS bit masks and bit positions */ +#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ +#define CRC_ZERO_bp 1 /* Zero detection bit position. */ + +#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ +#define CRC_BUSY_bp 0 /* Busy bit position. */ + +/* EDMA - Enhanced DMA Controller */ +/* EDMA.CTRL bit masks and bit positions */ +#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ +#define EDMA_ENABLE_bp 7 /* Enable bit position. */ + +#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ +#define EDMA_RESET_bp 6 /* Software Reset bit position. */ + +#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ +#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ +#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ +#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ +#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ +#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ + +#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ +#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ +#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ +#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ +#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ +#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ + +#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ +#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ +#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ +#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ +#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ +#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ + +/* EDMA.INTFLAGS bit masks and bit positions */ +#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ + +#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ + +/* EDMA.STATUS bit masks and bit positions */ +#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ +#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ + +#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ +#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ + +#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ +#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ + +#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ +#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ + +#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ +#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ + +#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ +#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ + +#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ +#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ + +#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ +#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ + +/* EDMA_CH.CTRLA bit masks and bit positions */ +#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ + +#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ + +#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ + +#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ + +#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ + +#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ +#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ + +/* EDMA_CH.CTRLB bit masks and bit positions */ +#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ +#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ + +#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ +#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ + +#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ +#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ + +#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ +#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ + +#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ +#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ +#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ +#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ +#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ +#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ + +#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ +#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ +#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ +#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ +#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ +#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ + +/* EDMA_CH.ADDRCTRL bit masks and bit positions */ +#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ +#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ +#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ +#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ +#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ +#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ + +#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ +#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ +#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ +#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ +#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ +#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ +#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ +#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ + +/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ +#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ +#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ + +#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ +#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ +#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ +#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ +#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ +#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ +#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ +#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ + +/* EDMA_CH.TRIGSRC bit masks and bit positions */ +#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ + +/* EVSYS - Event System */ +/* EVSYS.CH0MUX bit masks and bit positions */ +#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ + +/* EVSYS.CH1MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH2MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH3MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH4MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH5MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH6MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH7MUX bit masks and bit positions */ +/* EVSYS_CHMUX Predefined. */ +/* EVSYS_CHMUX Predefined. */ + +/* EVSYS.CH0CTRL bit masks and bit positions */ +#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ +#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ + +#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ + +#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ + +#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ + +#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ + +/* EVSYS.CH1CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH2CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH3CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH4CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH5CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH6CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.CH7CTRL bit masks and bit positions */ +/* EVSYS_DIGFILT Predefined. */ +/* EVSYS_DIGFILT Predefined. */ + +/* EVSYS.DFCTRL bit masks and bit positions */ +#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ +#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ +#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ +#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ +#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ +#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ +#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ +#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ +#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ +#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ + +#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ +#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ + +#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ +#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ +#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ +#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ +#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ +#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ + +/* NVM - Non Volatile Memory Controller */ +/* NVM.CMD bit masks and bit positions */ +#define NVM_CMD_gm 0x7F /* Command group mask. */ +#define NVM_CMD_gp 0 /* Command group position. */ +#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +#define NVM_CMD6_bp 6 /* Command bit 6 position. */ + +/* NVM.CTRLA bit masks and bit positions */ +#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ + +/* NVM.CTRLB bit masks and bit positions */ +#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ + +#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ + +/* NVM.INTCTRL bit masks and bit positions */ +#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ + +#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ + +/* NVM.STATUS bit masks and bit positions */ +#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ + +#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ + +#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ + +#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ + +/* NVM.LOCKBITS bit masks and bit positions */ +#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* ADC - Analog/Digital Converter */ +/* ADC_CH.CTRL bit masks and bit positions */ +#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ + +#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ + +#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ + +/* ADC_CH.MUXCTRL bit masks and bit positions */ +#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ +#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ +#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ +#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ +#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ +#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ +#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ +#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ +#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ +#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ + +#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ +#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ +#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ +#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ +#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ +#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ +#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ +#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ +#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ +#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ + +#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ +#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ +#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ +#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ +#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ +#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ + +#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ +#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ +#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ +#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ + +#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ +#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ +#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ +#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ +#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ +#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ + +/* ADC_CH.INTCTRL bit masks and bit positions */ +#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ + +#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ + +/* ADC_CH.INTFLAGS bit masks and bit positions */ +#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ + +/* ADC_CH.SCAN bit masks and bit positions */ +#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ +#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ +#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ +#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ +#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ +#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ +#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ +#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ +#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ +#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ + +#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ +#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ +#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ +#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ +#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ +#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ +#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ +#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ +#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ +#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ + +/* ADC_CH.CORRCTRL bit masks and bit positions */ +#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ +#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ + +/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ +#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ +#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ +#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ +#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ +#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ +#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ +#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ +#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ +#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ +#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ + +/* ADC_CH.GAINCORR1 bit masks and bit positions */ +#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ +#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ +#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ +#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ +#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ +#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ +#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ +#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ +#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ +#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ + +/* ADC_CH.AVGCTRL bit masks and bit positions */ +#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ +#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ +#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ +#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ +#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ +#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ +#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ +#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ + +#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ +#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ +#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ +#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ +#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ +#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ +#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ +#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ +#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ +#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ + +/* ADC.CTRLA bit masks and bit positions */ +#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ +#define ADC_START_bp 2 /* Start Conversion bit position. */ + +#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ + +#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ + +/* ADC.CTRLB bit masks and bit positions */ +#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ +#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ +#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ +#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ +#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ +#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ + +#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ + +#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ + +#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ + +/* ADC.REFCTRL bit masks and bit positions */ +#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ + +#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ + +#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ + +/* ADC.EVCTRL bit masks and bit positions */ +#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ + +#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ + +/* ADC.PRESCALER bit masks and bit positions */ +#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ + +/* ADC.INTFLAGS bit masks and bit positions */ +#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ + +/* ADC.SAMPCTRL bit masks and bit positions */ +#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ +#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ +#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ +#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ +#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ +#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ +#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ +#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ +#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ +#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ +#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ +#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ +#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ +#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ + +/* DAC - Digital/Analog Converter */ +/* DAC.CTRLA bit masks and bit positions */ +#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ + +#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ + +#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ + +#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ + +#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define DAC_ENABLE_bp 0 /* Enable bit position. */ + +/* DAC.CTRLB bit masks and bit positions */ +#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ + +#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ + +#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ + +/* DAC.CTRLC bit masks and bit positions */ +#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ + +#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ + +/* DAC.EVCTRL bit masks and bit positions */ +#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ + +#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ + +/* DAC.STATUS bit masks and bit positions */ +#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ + +#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ + +/* DAC.CH0GAINCAL bit masks and bit positions */ +#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH0OFFSETCAL bit masks and bit positions */ +#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* DAC.CH1GAINCAL bit masks and bit positions */ +#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ + +/* DAC.CH1OFFSETCAL bit masks and bit positions */ +#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ + +/* AC - Analog Comparator */ +/* AC.AC0CTRL bit masks and bit positions */ +#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ + +#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ + +#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ + +#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +#define AC_ENABLE_bp 0 /* Enable bit position. */ + +/* AC.AC1CTRL bit masks and bit positions */ +/* AC_INTMODE Predefined. */ +/* AC_INTMODE Predefined. */ + +/* AC_INTLVL Predefined. */ +/* AC_INTLVL Predefined. */ + +/* AC_HYSMODE Predefined. */ +/* AC_HYSMODE Predefined. */ + +/* AC_ENABLE Predefined. */ +/* AC_ENABLE Predefined. */ + +/* AC.AC0MUXCTRL bit masks and bit positions */ +#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ + +#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ + +/* AC.AC1MUXCTRL bit masks and bit positions */ +/* AC_MUXPOS Predefined. */ +/* AC_MUXPOS Predefined. */ + +/* AC_MUXNEG Predefined. */ +/* AC_MUXNEG Predefined. */ + +/* AC.CTRLA bit masks and bit positions */ +#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ +#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ + +#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ +#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ + +#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ +#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ + +#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ + +/* AC.CTRLB bit masks and bit positions */ +#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ + +/* AC.WINCTRL bit masks and bit positions */ +#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ + +#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ + +#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ + +/* AC.STATUS bit masks and bit positions */ +#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ + +#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ + +#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ + +#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ + +#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ + +#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ + +/* AC.CURRCTRL bit masks and bit positions */ +#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ +#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ + +#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ +#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ + +#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ +#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ + +#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ +#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ + +/* AC.CURRCALIB bit masks and bit positions */ +#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ +#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ +#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ +#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ +#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ +#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ +#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ +#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ +#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ +#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ + +/* RTC - Real-Time Clounter */ +/* RTC.CTRL bit masks and bit positions */ +#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ +#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ + +#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ + +/* RTC.STATUS bit masks and bit positions */ +#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ + +/* RTC.INTCTRL bit masks and bit positions */ +#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ + +#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ + +/* RTC.INTFLAGS bit masks and bit positions */ +#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ + +#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ + +/* RTC.CALIB bit masks and bit positions */ +#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ +#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ + +#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ +#define RTC_ERROR_gp 0 /* Error Value group position. */ +#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ +#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ +#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ +#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ +#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ +#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ +#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ +#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ +#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ +#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ +#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ +#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ +#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ +#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ + +/* XCL - XMEGA Custom Logic */ +/* XCL.CTRLA bit masks and bit positions */ +#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ +#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ +#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ +#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ +#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ +#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ + +#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ +#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ +#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ +#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ +#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ +#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ + +#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ +#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ +#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ +#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ +#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ +#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ +#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ +#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ + +/* XCL.CTRLB bit masks and bit positions */ +#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ +#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ +#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ +#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ +#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ +#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ + +#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ +#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ +#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ +#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ +#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ +#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ + +#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ +#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ +#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ +#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ +#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ +#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ + +#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ +#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ +#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ +#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ +#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ +#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ + +/* XCL.CTRLC bit masks and bit positions */ +#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ +#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ + +#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ +#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ + +#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ +#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ +#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ +#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ +#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ +#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ + +#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ +#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ +#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ +#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ +#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ +#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ + +#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ +#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ +#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ +#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ +#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ +#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ + +/* XCL.CTRLD bit masks and bit positions */ +#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ +#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ +#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ +#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ +#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ +#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ +#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ +#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ +#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ +#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ + +#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ +#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ +#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ +#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ +#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ +#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ +#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ +#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ +#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ +#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ + +/* XCL.CTRLE bit masks and bit positions */ +#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ +#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ + +#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ +#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ +#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ +#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ +#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ +#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ +#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ +#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ + +#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ +#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ + +/* XCL.CTRLF bit masks and bit positions */ +#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ +#define XCL_CMDEN_gp 6 /* Command Enable group position. */ +#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ +#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ +#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ +#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ + +#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ +#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ + +#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ +#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ + +#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ +#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ + +#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ +#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ + +#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ +#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ +#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ +#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ +#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ +#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ + +/* XCL.CTRLG bit masks and bit positions */ +#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ +#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ + +#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ +#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ +#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ +#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ +#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ +#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ + +#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ +#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ +#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ +#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ +#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ +#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ + +#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ +#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ +#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ +#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ +#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ +#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ +#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ +#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ + +/* XCL.INTCTRL bit masks and bit positions */ +#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ +#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ + +#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ +#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ + +#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ + +#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ +#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ + +#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ +#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ + +#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ +#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ + +#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ +#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ + +#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ +#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ + +#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ +#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ +#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ +#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ +#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ +#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ + +#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ +#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ +#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ +#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ +#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ +#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ + +/* XCL.INTFLAGS bit masks and bit positions */ +#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ +#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ + +#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ + +#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ +#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ + +#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ +#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ + +#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ +#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ + +#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ +#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ + +#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ +#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ + +/* XCL.PLC bit masks and bit positions */ +#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ +#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ +#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ +#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ +#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ +#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ +#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ +#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ +#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ +#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ +#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ +#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ +#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ +#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ +#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ +#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ +#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ +#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ + +/* XCL.CNTL bit masks and bit positions */ +#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ +#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ +#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ +#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ +#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ +#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ +#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ +#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ +#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ +#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ +#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ +#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ +#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ +#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ +#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ +#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ +#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ +#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ + +#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ +#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ +#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ +#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ +#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ +#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ +#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ +#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ +#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ +#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ +#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ +#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ +#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ +#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ +#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ +#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ +#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ +#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ + +#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ +#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ +#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ +#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ +#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ +#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ +#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ +#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ +#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ +#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ +#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ +#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ +#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ +#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ +#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ +#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ +#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ +#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ + +/* XCL.CNTH bit masks and bit positions */ +#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ +#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ +#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ +#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ +#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ +#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ +#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ +#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ +#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ +#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ +#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ +#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ +#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ +#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ +#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ +#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ +#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ +#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ + +#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ +#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ +#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ +#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ +#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ +#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ +#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ +#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ +#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ +#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ +#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ +#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ +#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ +#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ +#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ +#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ +#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ +#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ + +#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ +#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ +#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ +#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ +#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ +#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ +#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ +#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ +#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ +#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ +#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ +#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ +#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ +#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ +#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ +#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ +#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ +#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ + +#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ +#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ +#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ +#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ +#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ +#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ + +#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ +#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ +#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ +#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ +#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ +#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ +#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ +#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ +#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ +#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ + +/* XCL.CMPL bit masks and bit positions */ +#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ +#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ +#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ +#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ +#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ +#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ +#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ +#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ +#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ +#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ +#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ +#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ +#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ +#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ +#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ +#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ +#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ +#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ + +#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ +#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ +#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ +#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ +#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ +#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ +#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ +#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ +#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ +#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ +#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ +#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ +#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ +#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ +#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ +#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ +#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ +#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ + +/* XCL.CMPH bit masks and bit positions */ +#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ +#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ +#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ +#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ +#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ +#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ +#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ +#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ +#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ +#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ +#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ +#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ +#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ +#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ +#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ +#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ +#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ +#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ + +#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ +#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ +#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ +#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ +#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ +#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ +#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ +#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ +#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ +#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ +#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ +#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ +#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ +#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ +#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ +#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ +#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ +#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ + +/* XCL.PERCAPTL bit masks and bit positions */ +#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ +#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ +#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ +#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ +#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ +#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ +#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ +#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ +#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ +#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ +#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ +#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ +#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ +#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ +#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ +#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ +#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ +#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ + +#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ +#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ +#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ +#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ +#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ +#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ +#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ +#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ +#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ +#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ +#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ +#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ +#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ +#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ +#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ +#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ +#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ +#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ + +#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ +#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ +#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ +#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ +#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ +#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ +#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ +#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ +#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ +#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ +#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ +#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ +#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ +#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ +#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ +#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ +#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ +#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ + +#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ +#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ +#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ + +/* XCL.PERCAPTH bit masks and bit positions */ +#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ +#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ +#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ +#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ +#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ +#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ +#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ +#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ +#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ +#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ +#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ +#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ +#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ +#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ +#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ +#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ +#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ +#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ + +#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ +#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ +#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ +#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ +#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ +#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ +#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ +#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ +#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ +#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ +#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ +#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ +#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ +#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ +#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ +#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ +#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ +#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ + +#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ +#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ +#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ +#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ +#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ +#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ +#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ +#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ +#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ +#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ +#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ +#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ +#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ +#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ +#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ +#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ +#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ +#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ + +#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ +#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ +#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ +#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ +#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ +#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ +#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ +#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ +#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ +#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ +#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ +#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ +#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ +#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ +#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ +#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ +#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ +#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ + +/* TWI - Two-Wire Interface */ +/* TWI.CTRL bit masks and bit positions */ +#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ +#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ + +#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ +#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ + +#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ +#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ +#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ +#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ +#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ +#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ + +#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ +#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ + +#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ +#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ +#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ +#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ +#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ +#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ + +#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ + +/* TWI_MASTER.CTRLA bit masks and bit positions */ +#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ + +#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ + +#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ + +/* TWI_MASTER.CTRLB bit masks and bit positions */ +#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ + +#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ + +#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ +#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ + +#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_MASTER.CTRLC bit masks and bit positions */ +#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ + +/* TWI_MASTER.STATUS bit masks and bit positions */ +#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ + +#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ + +#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ + +#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ + +/* TWI_SLAVE.CTRLA bit masks and bit positions */ +#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ + +#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ + +#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ + +#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ + +#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ + +#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ + +/* TWI_SLAVE.CTRLB bit masks and bit positions */ +#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ + +#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ + +#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ +#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ + +#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ +#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ + +/* TWI_SLAVE.STATUS bit masks and bit positions */ +#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ + +#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ + +#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ + +#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ + +#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ + +#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ + +#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ + +#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ + +/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ + +#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ + +/* TWI_TIMEOUT.TOS bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ + +#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ +#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ + +/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ +#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ + +#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ +#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ + +#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ +#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ +#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ + +/* PORT - Port Configuration */ +/* PORT.INTCTRL bit masks and bit positions */ +#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ +#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ +#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ +#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ +#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ +#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ + +/* PORT.INTFLAGS bit masks and bit positions */ +#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ +#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ + +#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ +#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ + +#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ +#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ + +#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ +#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ + +#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ +#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ + +#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ +#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ + +#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ +#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ + +#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ +#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ + +/* PORT.REMAP bit masks and bit positions */ +#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ +#define PORT_USART0_bp 4 /* Usart0 bit position. */ + +#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ +#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ + +#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ +#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ + +#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ +#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ + +#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ +#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ + +/* PORT.PIN0CTRL bit masks and bit positions */ +#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ + +#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ + +#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ + +/* PORT.PIN1CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN2CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN3CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN4CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN5CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN6CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* PORT.PIN7CTRL bit masks and bit positions */ +/* PORT_INVEN Predefined. */ +/* PORT_INVEN Predefined. */ + +/* PORT_OPC Predefined. */ +/* PORT_OPC Predefined. */ + +/* PORT_ISC Predefined. */ +/* PORT_ISC Predefined. */ + +/* TC - 16-bit Timer/Counter With PWM */ +/* TC4.CTRLA bit masks and bit positions */ +#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC4.CTRLB bit masks and bit positions */ +#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC4.CTRLC bit masks and bit positions */ +#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ +#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ + +#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ +#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ + +#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ +#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ + +#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ +#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ + +#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ +#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ + +#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ +#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ + +#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ +#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ + +#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ +#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ + +#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC4.CTRLD bit masks and bit positions */ +#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC4_EVACT_gp 5 /* Event Action group position. */ +#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC4.CTRLE bit masks and bit positions */ +#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ +#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ +#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ +#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ +#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ +#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ + +#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ +#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ +#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ +#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ +#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ +#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ + +#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ +#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ +#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ +#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ +#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ +#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ +#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC4.CTRLF bit masks and bit positions */ +#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ +#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ +#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ +#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ +#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ +#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ +#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC4.INTCTRLA bit masks and bit positions */ +#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC4.INTCTRLB bit masks and bit positions */ +#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ +#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ +#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ +#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ +#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ +#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ +#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC4.CTRLGCLR bit masks and bit positions */ +#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC4_CMD_gm 0x0C /* Command group mask. */ +#define TC4_CMD_gp 2 /* Command group position. */ +#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC4_CMD0_bp 2 /* Command bit 0 position. */ +#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC4_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC4_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC4_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC4.CTRLGSET bit masks and bit positions */ +/* TC4_STOP Predefined. */ +/* TC4_STOP Predefined. */ + +/* TC4_CMD Predefined. */ +/* TC4_CMD Predefined. */ + +/* TC4_LUPD Predefined. */ +/* TC4_LUPD Predefined. */ + +/* TC4_DIR Predefined. */ +/* TC4_DIR Predefined. */ + +/* TC4.CTRLHCLR bit masks and bit positions */ +#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC4.CTRLHSET bit masks and bit positions */ +/* TC4_CCDBV Predefined. */ +/* TC4_CCDBV Predefined. */ + +/* TC4_CCCBV Predefined. */ +/* TC4_CCCBV Predefined. */ + +/* TC4_CCBBV Predefined. */ +/* TC4_CCBBV Predefined. */ + +/* TC4_CCABV Predefined. */ +/* TC4_CCABV Predefined. */ + +/* TC4_PERBV Predefined. */ +/* TC4_PERBV Predefined. */ + +/* TC4_LCCDBV Predefined. */ +/* TC4_LCCDBV Predefined. */ + +/* TC4_LCCCBV Predefined. */ +/* TC4_LCCCBV Predefined. */ + +/* TC4_LCCBBV Predefined. */ +/* TC4_LCCBBV Predefined. */ + +/* TC4_LCCABV Predefined. */ +/* TC4_LCCABV Predefined. */ + +/* TC4_LPERBV Predefined. */ +/* TC4_LPERBV Predefined. */ + +/* TC4.INTFLAGS bit masks and bit positions */ +#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* TC5.CTRLA bit masks and bit positions */ +#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ +#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ + +#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ +#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ + +#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ +#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ + +#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ +#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ +#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ +#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ +#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ +#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ +#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ +#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ +#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ +#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ + +/* TC5.CTRLB bit masks and bit positions */ +#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ +#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ +#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ +#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ +#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ +#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ + +#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ +#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ +#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ +#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ +#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ +#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ + +#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ +#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ +#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ +#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ +#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ +#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ +#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ +#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ + +/* TC5.CTRLC bit masks and bit positions */ +#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ +#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ + +#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ +#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ + +#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ +#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ + +#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ +#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ + +#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ +#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ + +#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ +#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ + +#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ +#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ + +#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ +#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ + +/* TC5.CTRLD bit masks and bit positions */ +#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ +#define TC5_EVACT_gp 5 /* Event Action group position. */ +#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ +#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ +#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ + +#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ +#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ + +#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ +#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ +#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ + +/* TC5.CTRLE bit masks and bit positions */ +#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ +#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ +#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ +#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ +#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ +#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ + +#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ +#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ +#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ +#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ +#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ +#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ +#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ +#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ +#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ + +#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ +#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ +#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ +#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ +#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ +#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ + +/* TC5.CTRLF bit masks and bit positions */ +#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ +#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ +#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ +#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ + +#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ +#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ +#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ +#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ +#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ +#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ + +/* TC5.INTCTRLA bit masks and bit positions */ +#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ +#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ +#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ +#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ +#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ +#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ + +#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ +#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ +#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ +#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ +#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ +#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ + +#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ +#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ +#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ +#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ +#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ +#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ + +/* TC5.INTCTRLB bit masks and bit positions */ +#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ +#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ +#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ +#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ +#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ +#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ + +#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ +#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ +#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ +#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ +#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ +#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ + +/* TC5.CTRLGCLR bit masks and bit positions */ +#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ +#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ + +#define TC5_CMD_gm 0x0C /* Command group mask. */ +#define TC5_CMD_gp 2 /* Command group position. */ +#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ +#define TC5_CMD0_bp 2 /* Command bit 0 position. */ +#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ +#define TC5_CMD1_bp 3 /* Command bit 1 position. */ + +#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ +#define TC5_LUPD_bp 1 /* Lock Update bit position. */ + +#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ +#define TC5_DIR_bp 0 /* Counter Direction bit position. */ + +/* TC5.CTRLGSET bit masks and bit positions */ +/* TC5_STOP Predefined. */ +/* TC5_STOP Predefined. */ + +/* TC5_CMD Predefined. */ +/* TC5_CMD Predefined. */ + +/* TC5_LUPD Predefined. */ +/* TC5_LUPD Predefined. */ + +/* TC5_DIR Predefined. */ +/* TC5_DIR Predefined. */ + +/* TC5.CTRLHCLR bit masks and bit positions */ +#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ + +#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ +#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ + +#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ + +#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ + +#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ +#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ + +#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ +#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ + +/* TC5.CTRLHSET bit masks and bit positions */ +/* TC5_CCBBV Predefined. */ +/* TC5_CCBBV Predefined. */ + +/* TC5_CCABV Predefined. */ +/* TC5_CCABV Predefined. */ + +/* TC5_PERBV Predefined. */ +/* TC5_PERBV Predefined. */ + +/* TC5_LCCBBV Predefined. */ +/* TC5_LCCBBV Predefined. */ + +/* TC5_LCCABV Predefined. */ +/* TC5_LCCABV Predefined. */ + +/* TC5_LPERBV Predefined. */ +/* TC5_LPERBV Predefined. */ + +/* TC5.INTFLAGS bit masks and bit positions */ +#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ + +#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ +#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ + +#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ + +#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ +#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ + +#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ + +#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ +#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ + +/* FAULT - Fault Extension */ +/* FAULT.CTRLA bit masks and bit positions */ +#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ +#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ +#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ +#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ +#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ +#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ + +#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ +#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ + +#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ +#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ + +#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ +#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ + +#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ +#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ + +#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ +#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ +#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ +#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ +#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ +#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ + +/* FAULT.CTRLB bit masks and bit positions */ +#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ +#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ + +#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ +#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ +#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ +#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ +#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ +#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ + +#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ +#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ + +#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ +#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ + +#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ +#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ +#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ +#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ +#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ +#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ + +/* FAULT.CTRLC bit masks and bit positions */ +#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ +#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ + +#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ +#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ + +#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ +#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ + +#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ +#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ + +/* FAULT.CTRLD bit masks and bit positions */ +#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ +#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ + +#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ +#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ +#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ +#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ +#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ +#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ + +#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ +#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ + +#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ +#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ + +#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ +#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ +#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ +#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ +#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ +#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ + +/* FAULT.CTRLE bit masks and bit positions */ +#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ +#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ + +#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ +#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ + +#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ +#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ + +#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ +#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ + +/* FAULT.STATUS bit masks and bit positions */ +#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ +#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ + +#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ +#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ + +#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ +#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ + +#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ +#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ + +#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGCLR bit masks and bit positions */ +#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ +#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ + +#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ +#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ + +#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ +#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ + +#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ +#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ + +#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ +#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ + +#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ +#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ + +/* FAULT.CTRLGSET bit masks and bit positions */ +#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ +#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ + +#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ +#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ + +#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ +#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ + +#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ +#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ +#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ +#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ +#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ +#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ + +/* WEX - Waveform Extension */ +/* WEX.CTRL bit masks and bit positions */ +#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ +#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ + +#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ +#define WEX_OTMX_gp 4 /* Output Matrix group position. */ +#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ +#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ +#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ +#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ +#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ +#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ + +#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ +#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ + +#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ +#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ + +#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ +#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ + +#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ +#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ + +/* WEX.STATUSCLR bit masks and bit positions */ +#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ +#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ + +#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ +#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ + +#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ +#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ + +/* WEX.STATUSSET bit masks and bit positions */ +/* WEX_SWAPBUF Predefined. */ +/* WEX_SWAPBUF Predefined. */ + +/* WEX_PGVBUFV Predefined. */ +/* WEX_PGVBUFV Predefined. */ + +/* WEX_PGOBUFV Predefined. */ +/* WEX_PGOBUFV Predefined. */ + +/* WEX.SWAP bit masks and bit positions */ +#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* WEX.SWAPBUF bit masks and bit positions */ +#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ +#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ + +#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ +#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ + +#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ +#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ + +#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ +#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ + +/* HIRES - High-Resolution Extension */ +/* HIRES.CTRLA bit masks and bit positions */ +#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ +#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ +#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ +#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ +#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ +#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ + +#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ +#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ +#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ +#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ +#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ +#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ + +/* USART - Universal Asynchronous Receiver-Transmitter */ +/* USART.STATUS bit masks and bit positions */ +#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ + +#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ + +#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ + +#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +#define USART_FERR_bp 4 /* Frame Error bit position. */ + +#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ + +#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +#define USART_PERR_bp 2 /* Parity Error bit position. */ + +#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ +#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ + +#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ + +#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ +#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ + +/* USART.CTRLA bit masks and bit positions */ +#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ +#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ + +#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ +#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ + +#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.CTRLB bit masks and bit positions */ +#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ +#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ + +#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ +#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ + +#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ + +#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ + +#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ + +#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ + +#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ + +/* USART.CTRLC bit masks and bit positions */ +#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +#define USART_CMODE_gp 6 /* Communication Mode group position. */ +#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ + +#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +#define USART_PMODE_gp 4 /* Parity Mode group position. */ +#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ + +#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ + +#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +#define USART_CHSIZE_gp 0 /* Character Size group position. */ +#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ + +/* USART.CTRLD bit masks and bit positions */ +#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ +#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ +#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ +#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ + +#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ +#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ +#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ + +#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ +#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ + +/* USART.BAUDCTRLA bit masks and bit positions */ +#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ + +/* USART.BAUDCTRLB bit masks and bit positions */ +#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ + +/* USART_BSEL Predefined. */ +/* USART_BSEL Predefined. */ + +/* SPI - Serial Peripheral Interface */ +/* SPI.CTRL bit masks and bit positions */ +#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ + +#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ +#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ + +#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ + +#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ + +#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +#define SPI_MODE_gp 2 /* SPI Mode group position. */ +#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ + +#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ + +/* SPI.INTCTRL bit masks and bit positions */ +#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ +#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ + +#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ + +/* SPI.STATUS bit masks and bit positions */ +#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ +#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ + +#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ +#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ + +#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ +#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ + +#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ +#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ + +/* SPI.CTRLB bit masks and bit positions */ +#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ +#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ +#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ +#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ +#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ +#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ + +#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ +#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ + +/* IRCOM - IR Communication Module */ +/* IRCOM.CTRL bit masks and bit positions */ +#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ + +/* FUSE - Fuses and Lockbits */ +/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ + +#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ + +#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ + +#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ + +/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ + +#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ + +/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ + +#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ + +#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ + +/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ + +#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ + +#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ +#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ +#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ +#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ +#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ +#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ +#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ +#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ + +/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ +#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ +#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ + +#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ +#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ + +#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ +#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ +#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ +#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ +#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ +#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ +#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ +#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ +#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ +#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ +#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ +#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ +#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ +#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ + + + +// Generic Port Pins + +#define PIN0_bm 0x01 +#define PIN0_bp 0 +#define PIN1_bm 0x02 +#define PIN1_bp 1 +#define PIN2_bm 0x04 +#define PIN2_bp 2 +#define PIN3_bm 0x08 +#define PIN3_bp 3 +#define PIN4_bm 0x10 +#define PIN4_bp 4 +#define PIN5_bm 0x20 +#define PIN5_bp 5 +#define PIN6_bm 0x40 +#define PIN6_bp 6 +#define PIN7_bm 0x80 +#define PIN7_bp 7 + +/* ========== Interrupt Vector Definitions ========== */ +/* Vector 0 is the reset vector */ + +/* OSC interrupt vectors */ +#define OSC_OSCF_vect_num 1 +#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ + +/* PORTR interrupt vectors */ +#define PORTR_INT_vect_num 2 +#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ + +/* EDMA interrupt vectors */ +#define EDMA_CH0_vect_num 3 +#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ +#define EDMA_CH1_vect_num 4 +#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ +#define EDMA_CH2_vect_num 5 +#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ +#define EDMA_CH3_vect_num 6 +#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ + +/* RTC interrupt vectors */ +#define RTC_OVF_vect_num 7 +#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ +#define RTC_COMP_vect_num 8 +#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ + +/* PORTC interrupt vectors */ +#define PORTC_INT_vect_num 9 +#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ + +/* TWIC interrupt vectors */ +#define TWIC_TWIS_vect_num 10 +#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ +#define TWIC_TWIM_vect_num 11 +#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ + +/* TCC4 interrupt vectors */ +#define TCC4_OVF_vect_num 12 +#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ +#define TCC4_ERR_vect_num 13 +#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ +#define TCC4_CCA_vect_num 14 +#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ +#define TCC4_CCB_vect_num 15 +#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ +#define TCC4_CCC_vect_num 16 +#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ +#define TCC4_CCD_vect_num 17 +#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ + +/* TCC5 interrupt vectors */ +#define TCC5_OVF_vect_num 18 +#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ +#define TCC5_ERR_vect_num 19 +#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ +#define TCC5_CCA_vect_num 20 +#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ +#define TCC5_CCB_vect_num 21 +#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ + +/* SPIC interrupt vectors */ +#define SPIC_INT_vect_num 22 +#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ + +/* USARTC0 interrupt vectors */ +#define USARTC0_RXC_vect_num 23 +#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ +#define USARTC0_DRE_vect_num 24 +#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ +#define USARTC0_TXC_vect_num 25 +#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ + +/* NVM interrupt vectors */ +#define NVM_EE_vect_num 26 +#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ +#define NVM_SPM_vect_num 27 +#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ + +/* XCL interrupt vectors */ +#define XCL_UNF_vect_num 28 +#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ +#define XCL_CC_vect_num 29 +#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ + +/* PORTA interrupt vectors */ +#define PORTA_INT_vect_num 30 +#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ + +/* ACA interrupt vectors */ +#define ACA_AC0_vect_num 31 +#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ +#define ACA_AC1_vect_num 32 +#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ +#define ACA_ACW_vect_num 33 +#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ + +/* ADCA interrupt vectors */ +#define ADCA_CH0_vect_num 34 +#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ + +/* PORTD interrupt vectors */ +#define PORTD_INT_vect_num 35 +#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ + +/* TCD5 interrupt vectors */ +#define TCD5_OVF_vect_num 36 +#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ +#define TCD5_ERR_vect_num 37 +#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ +#define TCD5_CCA_vect_num 38 +#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ +#define TCD5_CCB_vect_num 39 +#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ + +/* USARTD0 interrupt vectors */ +#define USARTD0_RXC_vect_num 40 +#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ +#define USARTD0_DRE_vect_num 41 +#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ +#define USARTD0_TXC_vect_num 42 +#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ + +#define _VECTOR_SIZE 4 /* Size of individual vector. */ +#define _VECTORS_SIZE (43 * _VECTOR_SIZE) + + +/* ========== Constants ========== */ + +#define PROGMEM_START (0x0000) +#define PROGMEM_SIZE (10240) +#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) + +#define APP_SECTION_START (0x0000) +#define APP_SECTION_SIZE (8192) +#define APP_SECTION_PAGE_SIZE (128) +#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) + +#define APPTABLE_SECTION_START (0x1800) +#define APPTABLE_SECTION_SIZE (2048) +#define APPTABLE_SECTION_PAGE_SIZE (128) +#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) + +#define BOOT_SECTION_START (0x2000) +#define BOOT_SECTION_SIZE (2048) +#define BOOT_SECTION_PAGE_SIZE (128) +#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) + +#define DATAMEM_START (0x0000) +#define DATAMEM_SIZE (9216) +#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) + +#define IO_START (0x0000) +#define IO_SIZE (4096) +#define IO_PAGE_SIZE (0) +#define IO_END (IO_START + IO_SIZE - 1) + +#define MAPPED_EEPROM_START (0x1000) +#define MAPPED_EEPROM_SIZE (512) +#define MAPPED_EEPROM_PAGE_SIZE (0) +#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) + +#define INTERNAL_SRAM_START (0x2000) +#define INTERNAL_SRAM_SIZE (1024) +#define INTERNAL_SRAM_PAGE_SIZE (0) +#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) + +#define EEPROM_START (0x0000) +#define EEPROM_SIZE (512) +#define EEPROM_PAGE_SIZE (32) +#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) + +#define SIGNATURES_START (0x0000) +#define SIGNATURES_SIZE (3) +#define SIGNATURES_PAGE_SIZE (0) +#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) + +#define FUSES_START (0x0000) +#define FUSES_SIZE (7) +#define FUSES_PAGE_SIZE (0) +#define FUSES_END (FUSES_START + FUSES_SIZE - 1) + +#define LOCKBITS_START (0x0000) +#define LOCKBITS_SIZE (1) +#define LOCKBITS_PAGE_SIZE (0) +#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) + +#define USER_SIGNATURES_START (0x0000) +#define USER_SIGNATURES_SIZE (128) +#define USER_SIGNATURES_PAGE_SIZE (128) +#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) + +#define PROD_SIGNATURES_START (0x0000) +#define PROD_SIGNATURES_SIZE (54) +#define PROD_SIGNATURES_PAGE_SIZE (128) +#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) + +#define FLASHSTART PROGMEM_START +#define FLASHEND PROGMEM_END +#define SPM_PAGESIZE 128 +#define RAMSTART INTERNAL_SRAM_START +#define RAMSIZE INTERNAL_SRAM_SIZE +#define RAMEND INTERNAL_SRAM_END +#define E2END EEPROM_END +#define E2PAGESIZE EEPROM_PAGE_SIZE + + +/* ========== Fuses ========== */ +#define FUSE_MEMORY_SIZE 7 + +/* Fuse Byte 0 Reserved */ + +/* Fuse Byte 1 */ +#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +#define FUSE1_DEFAULT (0xFF) + +/* Fuse Byte 2 */ +#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +#define FUSE2_DEFAULT (0xFF) + +/* Fuse Byte 3 Reserved */ + +/* Fuse Byte 4 */ +#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +#define FUSE4_DEFAULT (0xFF) + +/* Fuse Byte 5 */ +#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ +#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ +#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ +#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +#define FUSE5_DEFAULT (0xFF) + +/* Fuse Byte 6 */ +#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ +#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ +#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ +#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ +#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ +#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ +#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ +#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ +#define FUSE6_DEFAULT (0xFF) + +/* ========== Lock Bits ========== */ +#define __LOCK_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +#define __BOOT_LOCK_APPLICATION_BITS_EXIST +#define __BOOT_LOCK_BOOT_BITS_EXIST + +/* ========== Signature ========== */ +#define SIGNATURE_0 0x1E +#define SIGNATURE_1 0x93 +#define SIGNATURE_2 0x41 + +/* ========== Power Reduction Condition Definitions ========== */ + +/* PR.PRGEN */ +#define __AVR_HAVE_PRGEN (PR_XCL_bm|PR_RTC_bm|PR_EVSYS_bm|PR_EDMA_bm) +#define __AVR_HAVE_PRGEN_XCL +#define __AVR_HAVE_PRGEN_RTC +#define __AVR_HAVE_PRGEN_EVSYS +#define __AVR_HAVE_PRGEN_EDMA + +/* PR.PRPA */ +#define __AVR_HAVE_PRPA (PR_DAC_bm|PR_ADC_bm|PR_AC_bm) +#define __AVR_HAVE_PRPA_DAC +#define __AVR_HAVE_PRPA_ADC +#define __AVR_HAVE_PRPA_AC + +/* PR.PRPC */ +#define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC5_bm|PR_TC4_bm) +#define __AVR_HAVE_PRPC_TWI +#define __AVR_HAVE_PRPC_USART0 +#define __AVR_HAVE_PRPC_SPI +#define __AVR_HAVE_PRPC_HIRES +#define __AVR_HAVE_PRPC_TC5 +#define __AVR_HAVE_PRPC_TC4 + +/* PR.PRPD */ +#define __AVR_HAVE_PRPD (PR_USART0_bm|PR_TC5_bm) +#define __AVR_HAVE_PRPD_USART0 +#define __AVR_HAVE_PRPD_TC5 + + +#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ + diff --git a/hardware/tools/avr/avr/include/avr/lock.h b/hardware/tools/avr/avr/include/avr/lock.h new file mode 100644 index 0000000000000000000000000000000000000000..fa87655542a67e72549158822d671fd9ef9bd296 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/lock.h @@ -0,0 +1,239 @@ +/* Copyright (c) 2007, Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* avr/lock.h - Lock Bits API */ + +#ifndef _AVR_LOCK_H_ +#define _AVR_LOCK_H_ 1 + + +/** \file */ +/** \defgroup avr_lock : Lockbit Support + + \par Introduction + + The Lockbit API allows a user to specify the lockbit settings for the + specific AVR device they are compiling for. These lockbit settings will be + placed in a special section in the ELF output file, after linking. + + Programming tools can take advantage of the lockbit information embedded in + the ELF file, by extracting this information and determining if the lockbits + need to be programmed after programming the Flash and EEPROM memories. + This also allows a single ELF file to contain all the + information needed to program an AVR. + + To use the Lockbit API, include the header file, which in turn + automatically includes the individual I/O header file and the + file. These other two files provides everything necessary to set the AVR + lockbits. + + \par Lockbit API + + Each I/O header file may define up to 3 macros that controls what kinds + of lockbits are available to the user. + + If __LOCK_BITS_EXIST is defined, then two lock bits are available to the + user and 3 mode settings are defined for these two bits. + + If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are + available to the user and 4 mode settings are defined for these two bits. + + If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are + available to the user and 4 mode settings are defined for these two bits. + + If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits + are available to set the locking mode for the Application Table Section + (which is used in the XMEGA family). + + If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are + available to set the locking mode for the Application Section (which is used + in the XMEGA family). + + If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available + to set the locking mode for the Boot Loader Section (which is used in the + XMEGA family). + + The AVR lockbit modes have inverted values, logical 1 for an unprogrammed + (disabled) bit and logical 0 for a programmed (enabled) bit. The defined + macros for each individual lock bit represent this in their definition by a + bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined + as: + \code + #define LB_MODE_3 (0xFC) +` \endcode + + To combine the lockbit mode macros together to represent a whole byte, + use the bitwise AND operator, like so: + \code + (LB_MODE_3 & BLB0_MODE_2) + \endcode + + also defines a macro that provides a default lockbit value: + LOCKBITS_DEFAULT which is defined to be 0xFF. + + See the AVR device specific datasheet for more details about these + lock bits and the available mode settings. + + A convenience macro, LOCKMEM, is defined as a GCC attribute for a + custom-named section of ".lock". + + A convenience macro, LOCKBITS, is defined that declares a variable, __lock, + of type unsigned char with the attribute defined by LOCKMEM. This variable + allows the end user to easily set the lockbit data. + + \note If a device-specific I/O header file has previously defined LOCKMEM, + then LOCKMEM is not redefined. If a device-specific I/O header file has + previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is + currently known to be defined in the I/O header files for the XMEGA devices. + + \par API Usage Example + + Putting all of this together is easy: + + \code + #include + + LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); + + int main(void) + { + return 0; + } + \endcode + + Or: + + \code + #include + + unsigned char __lock __attribute__((section (".lock"))) = + (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4); + + int main(void) + { + return 0; + } + \endcode + + + + However there are a number of caveats that you need to be aware of to + use this API properly. + + Be sure to include to get all of the definitions for the API. + The LOCKBITS macro defines a global variable to store the lockbit data. This + variable is assigned to its own linker section. Assign the desired lockbit + values immediately in the variable initialization. + + The .lock section in the ELF file will get its values from the initial + variable assignment ONLY. This means that you can NOT assign values to + this variable in functions and the new values will not be put into the + ELF .lock section. + + The global variable is declared in the LOCKBITS macro has two leading + underscores, which means that it is reserved for the "implementation", + meaning the library, so it will not conflict with a user-named variable. + + You must initialize the lockbit variable to some meaningful value, even + if it is the default value. This is because the lockbits default to a + logical 1, meaning unprogrammed. Normal uninitialized data defaults to all + locgial zeros. So it is vital that all lockbits are initialized, even with + default data. If they are not, then the lockbits may not programmed to the + desired settings and can possibly put your device into an unrecoverable + state. + + Be sure to have the -mmcu=device flag in your compile command line and + your linker command line to have the correct device selected and to have + the correct I/O header file included when you include . + + You can print out the contents of the .lock section in the ELF file by + using this command line: + \code + avr-objdump -s -j .lock + \endcode + +*/ + + +#if !(defined(__ASSEMBLER__) || defined(__DOXYGEN__)) + +#ifndef LOCKMEM +#define LOCKMEM __attribute__((__used__, __section__ (".lock"))) +#endif + +#ifndef LOCKBITS +#define LOCKBITS unsigned char __lock LOCKMEM +#endif + +/* Lock Bit Modes */ +#if defined(__LOCK_BITS_EXIST) +#define LB_MODE_1 (0xFF) +#define LB_MODE_2 (0xFE) +#define LB_MODE_3 (0xFC) +#endif + +#if defined(__BOOT_LOCK_BITS_0_EXIST) +#define BLB0_MODE_1 (0xFF) +#define BLB0_MODE_2 (0xFB) +#define BLB0_MODE_3 (0xF3) +#define BLB0_MODE_4 (0xF7) +#endif + +#if defined(__BOOT_LOCK_BITS_1_EXIST) +#define BLB1_MODE_1 (0xFF) +#define BLB1_MODE_2 (0xEF) +#define BLB1_MODE_3 (0xCF) +#define BLB1_MODE_4 (0xDF) +#endif + +#if defined(__BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST) +#define BLBAT0 ~_BV(2) +#define BLBAT1 ~_BV(3) +#endif + +#if defined(__BOOT_LOCK_APPLICATION_BITS_EXIST) +#define BLBA0 ~_BV(4) +#define BLBA1 ~_BV(5) +#endif + +#if defined(__BOOT_LOCK_BOOT_BITS_EXIST) +#define BLBB0 ~_BV(6) +#define BLBB1 ~_BV(7) +#endif + + +#define LOCKBITS_DEFAULT (0xFF) + +#endif /* !(__ASSEMBLER || __DOXYGEN__) */ + + +#endif /* _AVR_LOCK_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/parity.h b/hardware/tools/avr/avr/include/avr/parity.h new file mode 100644 index 0000000000000000000000000000000000000000..d7afd34ddd4da5a89164bd96b0a54f1be0297a7c --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/parity.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2005 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_PARITY_H_ +#define _AVR_PARITY_H_ + +#warning "This file has been moved to ." +#include + +#endif /* _AVR_PARITY_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/pgmspace.h b/hardware/tools/avr/avr/include/avr/pgmspace.h new file mode 100644 index 0000000000000000000000000000000000000000..57407404b441a54d90013652f09ad5c939858ec4 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/pgmspace.h @@ -0,0 +1,1791 @@ +/* Copyright (c) 2002-2007 Marek Michalkiewicz + Copyright (c) 2006, Carlos Lamas + Copyright (c) 2009-2010, Jan Waclawek + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + pgmspace.h + + Contributors: + Created by Marek Michalkiewicz + Eric B. Weddington + Wolfgang Haidinger (pgm_read_dword()) + Ivanov Anton (pgm_read_float()) + */ + +/** \file */ +/** \defgroup avr_pgmspace : Program Space Utilities + \code + #include + #include + \endcode + + The functions in this module provide interfaces for a program to access + data stored in program space (flash memory) of the device. In order to + use these functions, the target device must support either the \c LPM or + \c ELPM instructions. + + \note These functions are an attempt to provide some compatibility with + header files that come with IAR C, to make porting applications between + different compilers easier. This is not 100% compatibility though (GCC + does not have full support for multiple address spaces yet). + + \note If you are working with strings which are completely based in ram, + use the standard string functions described in \ref avr_string. + + \note If possible, put your constant tables in the lower 64 KB and use + pgm_read_byte_near() or pgm_read_word_near() instead of + pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that + way, and you can still use the upper 64K for executable code. + All functions that are suffixed with a \c _P \e require their + arguments to be in the lower 64 KB of the flash ROM, as they do + not use ELPM instructions. This is normally not a big concern as + the linker setup arranges any program space constants declared + using the macros from this header file so they are placed right after + the interrupt vectors, and in front of any executable code. However, + it can become a problem if there are too many of these constants, or + for bootloaders on devices with more than 64 KB of ROM. + All these functions will not work in that situation. + + \note For Xmega devices, make sure the NVM controller + command register (\c NVM.CMD or \c NVM_CMD) is set to 0x00 (NOP) + before using any of these functions. +*/ + +#ifndef __PGMSPACE_H_ +#define __PGMSPACE_H_ 1 + +#ifndef __DOXYGEN__ +#define __need_size_t +#endif +#include +#include +#include + +#ifndef __DOXYGEN__ +#ifndef __ATTR_CONST__ +#define __ATTR_CONST__ __attribute__((__const__)) +#endif + +#ifndef __ATTR_PROGMEM__ +#define __ATTR_PROGMEM__ __attribute__((__progmem__)) +#endif + +#ifndef __ATTR_PURE__ +#define __ATTR_PURE__ __attribute__((__pure__)) +#endif +#endif /* !__DOXYGEN__ */ + +/** + \ingroup avr_pgmspace + \def PROGMEM + + Attribute to use in order to declare an object being located in + flash ROM. + */ +#define PROGMEM __ATTR_PROGMEM__ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__DOXYGEN__) +/* + * Doxygen doesn't grok the appended attribute syntax of + * GCC, and confuses the typedefs with function decls, so + * supply a doxygen-friendly view. + */ + +/** + \ingroup avr_pgmspace + \typedef prog_void + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of a "void" object located in flash ROM. Does not make much + sense by itself, but can be used to declare a "void *" object in + flash ROM. +*/ +typedef void PROGMEM prog_void; + +/** + \ingroup avr_pgmspace + \typedef prog_char + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of a "char" object located in flash ROM. +*/ +typedef char PROGMEM prog_char; + +/** + \ingroup avr_pgmspace + \typedef prog_uchar + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "unsigned char" object located in flash ROM. +*/ +typedef unsigned char PROGMEM prog_uchar; + +/** + \ingroup avr_pgmspace + \typedef prog_int8_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "int8_t" object located in flash ROM. +*/ +typedef int8_t PROGMEM prog_int8_t; + +/** + \ingroup avr_pgmspace + \typedef prog_uint8_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "uint8_t" object located in flash ROM. +*/ +typedef uint8_t PROGMEM prog_uint8_t; + +/** + \ingroup avr_pgmspace + \typedef prog_int16_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "int16_t" object located in flash ROM. +*/ +typedef int16_t PROGMEM prog_int16_t; + +/** + \ingroup avr_pgmspace + \typedef prog_uint16_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "uint16_t" object located in flash ROM. +*/ +typedef uint16_t PROGMEM prog_uint16_t; + +/** + \ingroup avr_pgmspace + \typedef prog_int32_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "int32_t" object located in flash ROM. +*/ +typedef int32_t PROGMEM prog_int32_t; + +/** + \ingroup avr_pgmspace + \typedef prog_uint32_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "uint32_t" object located in flash ROM. +*/ +typedef uint32_t PROGMEM prog_uint32_t; + +/** + \ingroup avr_pgmspace + \typedef prog_int64_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "int64_t" object located in flash ROM. + + \note This type is not available when the compiler + option -mint8 is in effect. +*/ +typedef int64_t PROGMEM prog_int64_t; + +/** + \ingroup avr_pgmspace + \typedef prog_uint64_t + \note DEPRECATED + + This typedef is now deprecated because the usage of the __progmem__ + attribute on a type is not supported in GCC. However, the use of the + __progmem__ attribute on a variable declaration is supported, and this is + now the recommended usage. + + The typedef is only visible if the macro __PROG_TYPES_COMPAT__ + has been defined before including (either by a + \c \#define directive, or by a -D compiler option.) + + Type of an "uint64_t" object located in flash ROM. + + \note This type is not available when the compiler + option -mint8 is in effect. +*/ +typedef uint64_t PROGMEM prog_uint64_t; + +/** \ingroup avr_pgmspace + \def PGM_P + + Used to declare a variable that is a pointer to a string in program + space. */ + +#ifndef PGM_P +#define PGM_P const char * +#endif + +/** \ingroup avr_pgmspace + \def PGM_VOID_P + + Used to declare a generic pointer to an object in program space. */ + +#ifndef PGM_VOID_P +#define PGM_VOID_P const void * +#endif + +#elif defined(__PROG_TYPES_COMPAT__) /* !DOXYGEN */ + +typedef void prog_void __attribute__((__progmem__,deprecated("prog_void type is deprecated."))); +typedef char prog_char __attribute__((__progmem__,deprecated("prog_char type is deprecated."))); +typedef unsigned char prog_uchar __attribute__((__progmem__,deprecated("prog_uchar type is deprecated."))); +typedef int8_t prog_int8_t __attribute__((__progmem__,deprecated("prog_int8_t type is deprecated."))); +typedef uint8_t prog_uint8_t __attribute__((__progmem__,deprecated("prog_uint8_t type is deprecated."))); +typedef int16_t prog_int16_t __attribute__((__progmem__,deprecated("prog_int16_t type is deprecated."))); +typedef uint16_t prog_uint16_t __attribute__((__progmem__,deprecated("prog_uint16_t type is deprecated."))); +typedef int32_t prog_int32_t __attribute__((__progmem__,deprecated("prog_int32_t type is deprecated."))); +typedef uint32_t prog_uint32_t __attribute__((__progmem__,deprecated("prog_uint32_t type is deprecated."))); +#if !__USING_MINT8 +typedef int64_t prog_int64_t __attribute__((__progmem__,deprecated("prog_int64_t type is deprecated."))); +typedef uint64_t prog_uint64_t __attribute__((__progmem__,deprecated("prog_uint64_t type is deprecated."))); +#endif + +#ifndef PGM_P +#define PGM_P const prog_char * +#endif + +#ifndef PGM_VOID_P +#define PGM_VOID_P const prog_void * +#endif + +#else /* !defined(__DOXYGEN__), !defined(__PROG_TYPES_COMPAT__) */ + +#ifndef PGM_P +#define PGM_P const char * +#endif + +#ifndef PGM_VOID_P +#define PGM_VOID_P const void * +#endif +#endif /* defined(__DOXYGEN__), defined(__PROG_TYPES_COMPAT__) */ + +/* Although in C, we can get away with just using __c, it does not work in + C++. We need to use &__c[0] to avoid the compiler puking. Dave Hylands + explaned it thusly, + + Let's suppose that we use PSTR("Test"). In this case, the type returned + by __c is a prog_char[5] and not a prog_char *. While these are + compatible, they aren't the same thing (especially in C++). The type + returned by &__c[0] is a prog_char *, which explains why it works + fine. */ + +#if defined(__DOXYGEN__) +/* + * The #define below is just a dummy that serves documentation + * purposes only. + */ +/** \ingroup avr_pgmspace + \def PSTR(s) + + Used to declare a static pointer to a string in program space. */ +# define PSTR(s) ((const PROGMEM char *)(s)) +#else /* !DOXYGEN */ +/* The real thing. */ +# define PSTR(s) (__extension__({static const char __c[] PROGMEM = (s); &__c[0];})) +#endif /* DOXYGEN */ + +#ifndef __DOXYGEN__ /* Internal macros, not documented. */ +#define __LPM_classic__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm" "\n\t" \ + "mov %0, r0" "\n\t" \ + : "=r" (__result) \ + : "z" (__addr16) \ + : "r0" \ + ); \ + __result; \ +})) + +#define __LPM_tiny__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ + uint8_t __result; \ + __asm__ \ + ( \ + "ld %0, z" "\n\t" \ + : "=r" (__result) \ + : "z" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_enhanced__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm %0, Z" "\n\t" \ + : "=r" (__result) \ + : "z" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_word_classic__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint16_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + : "r0" \ + ); \ + __result; \ +})) + +#define __LPM_word_tiny__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ + uint16_t __result; \ + __asm__ \ + ( \ + "ld %A0, z+" "\n\t" \ + "ld %B0, z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_word_enhanced__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint16_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm %A0, Z+" "\n\t" \ + "lpm %B0, Z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_dword_classic__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint32_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %C0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %D0, r0" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + : "r0" \ + ); \ + __result; \ +})) + +#define __LPM_dword_tiny__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ + uint32_t __result; \ + __asm__ \ + ( \ + "ld %A0, z+" "\n\t" \ + "ld %B0, z+" "\n\t" \ + "ld %C0, z+" "\n\t" \ + "ld %D0, z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_dword_enhanced__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + uint32_t __result; \ + __asm__ __volatile__ \ + ( \ + "lpm %A0, Z+" "\n\t" \ + "lpm %B0, Z+" "\n\t" \ + "lpm %C0, Z+" "\n\t" \ + "lpm %D0, Z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_float_classic__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + float __result; \ + __asm__ __volatile__ \ + ( \ + "lpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %C0, r0" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "lpm" "\n\t" \ + "mov %D0, r0" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + : "r0" \ + ); \ + __result; \ +})) + +#define __LPM_float_tiny__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr) + __AVR_TINY_PM_BASE_ADDRESS__; \ + float __result; \ + __asm__ \ + ( \ + "ld %A0, z+" "\n\t" \ + "ld %B0, z+" "\n\t" \ + "ld %C0, z+" "\n\t" \ + "ld %D0, z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#define __LPM_float_enhanced__(addr) \ +(__extension__({ \ + uint16_t __addr16 = (uint16_t)(addr); \ + float __result; \ + __asm__ __volatile__ \ + ( \ + "lpm %A0, Z+" "\n\t" \ + "lpm %B0, Z+" "\n\t" \ + "lpm %C0, Z+" "\n\t" \ + "lpm %D0, Z" "\n\t" \ + : "=r" (__result), "=z" (__addr16) \ + : "1" (__addr16) \ + ); \ + __result; \ +})) + +#if defined (__AVR_HAVE_LPMX__) +#define __LPM(addr) __LPM_enhanced__(addr) +#define __LPM_word(addr) __LPM_word_enhanced__(addr) +#define __LPM_dword(addr) __LPM_dword_enhanced__(addr) +#define __LPM_float(addr) __LPM_float_enhanced__(addr) +/* +Macro to read data from program memory for avr tiny parts(tiny 4/5/9/10/20/40). +why: +- LPM instruction is not available in AVR_TINY instruction set. +- Programs are executed starting from address 0x0000 in program memory. +But it must be addressed starting from 0x4000 when accessed via data memory. +Reference: TINY device (ATTiny 4,5,9,10,20 and 40) datasheets +Bug: avrtc-536 +*/ +#elif defined (__AVR_TINY__) +#define __LPM(addr) __LPM_tiny__(addr) +#define __LPM_word(addr) __LPM_word_tiny__(addr) +#define __LPM_dword(addr) __LPM_dword_tiny__(addr) +#define __LPM_float(addr) __LPM_float_tiny__(addr) +#else +#define __LPM(addr) __LPM_classic__(addr) +#define __LPM_word(addr) __LPM_word_classic__(addr) +#define __LPM_dword(addr) __LPM_dword_classic__(addr) +#define __LPM_float(addr) __LPM_float_classic__(addr) +#endif + +#endif /* !__DOXYGEN__ */ + +/** \ingroup avr_pgmspace + \def pgm_read_byte_near(address_short) + Read a byte from the program space with a 16-bit (near) address. + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_byte_near(address_short) __LPM((uint16_t)(address_short)) + +/** \ingroup avr_pgmspace + \def pgm_read_word_near(address_short) + Read a word from the program space with a 16-bit (near) address. + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short)) + +/** \ingroup avr_pgmspace + \def pgm_read_dword_near(address_short) + Read a double word from the program space with a 16-bit (near) address. + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_dword_near(address_short) \ + __LPM_dword((uint16_t)(address_short)) + +/** \ingroup avr_pgmspace + \def pgm_read_float_near(address_short) + Read a float from the program space with a 16-bit (near) address. + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_float_near(address_short) \ + __LPM_float((uint16_t)(address_short)) + +/** \ingroup avr_pgmspace + \def pgm_read_ptr_near(address_short) + Read a pointer from the program space with a 16-bit (near) address. + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_ptr_near(address_short) \ + (void*)__LPM_word((uint16_t)(address_short)) + +#if defined(RAMPZ) || defined(__DOXYGEN__) + +/* Only for devices with more than 64K of program memory. + RAMPZ must be defined (see iom103.h, iom128.h). +*/ + +/* The classic functions are needed for ATmega103. */ +#ifndef __DOXYGEN__ /* These are internal macros, avoid "is + not documented" warnings. */ +#define __ELPM_classic__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "mov r31, %B1" "\n\t" \ + "mov r30, %A1" "\n\t" \ + "elpm" "\n\t" \ + "mov %0, r0" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r0", "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_enhanced__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %0, Z+" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_xmega__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint8_t __result; \ + __asm__ __volatile__ \ + ( \ + "in __tmp_reg__, %2" "\n\t" \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %0, Z+" "\n\t" \ + "out %2, __tmp_reg__" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_word_classic__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint16_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "mov r31, %B1" "\n\t" \ + "mov r30, %A1" "\n\t" \ + "elpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r0", "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_word_enhanced__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint16_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_word_xmega__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint16_t __result; \ + __asm__ __volatile__ \ + ( \ + "in __tmp_reg__, %2" "\n\t" \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z" "\n\t" \ + "out %2, __tmp_reg__" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_dword_classic__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint32_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "mov r31, %B1" "\n\t" \ + "mov r30, %A1" "\n\t" \ + "elpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %C0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %D0, r0" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r0", "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_dword_enhanced__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint32_t __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z+" "\n\t" \ + "elpm %C0, Z+" "\n\t" \ + "elpm %D0, Z" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_dword_xmega__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + uint32_t __result; \ + __asm__ __volatile__ \ + ( \ + "in __tmp_reg__, %2" "\n\t" \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z+" "\n\t" \ + "elpm %C0, Z+" "\n\t" \ + "elpm %D0, Z" "\n\t" \ + "out %2, __tmp_reg__" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_float_classic__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + float __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "mov r31, %B1" "\n\t" \ + "mov r30, %A1" "\n\t" \ + "elpm" "\n\t" \ + "mov %A0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %B0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %C0, r0" "\n\t" \ + "in r0, %2" "\n\t" \ + "adiw r30, 1" "\n\t" \ + "adc r0, __zero_reg__" "\n\t" \ + "out %2, r0" "\n\t" \ + "elpm" "\n\t" \ + "mov %D0, r0" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r0", "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_float_enhanced__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + float __result; \ + __asm__ __volatile__ \ + ( \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z+" "\n\t" \ + "elpm %C0, Z+" "\n\t" \ + "elpm %D0, Z" "\n\t" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +#define __ELPM_float_xmega__(addr) \ +(__extension__({ \ + uint32_t __addr32 = (uint32_t)(addr); \ + float __result; \ + __asm__ __volatile__ \ + ( \ + "in __tmp_reg__, %2" "\n\t" \ + "out %2, %C1" "\n\t" \ + "movw r30, %1" "\n\t" \ + "elpm %A0, Z+" "\n\t" \ + "elpm %B0, Z+" "\n\t" \ + "elpm %C0, Z+" "\n\t" \ + "elpm %D0, Z" "\n\t" \ + "out %2, __tmp_reg__" \ + : "=r" (__result) \ + : "r" (__addr32), \ + "I" (_SFR_IO_ADDR(RAMPZ)) \ + : "r30", "r31" \ + ); \ + __result; \ +})) + +/* +Check for architectures that implement RAMPD (avrxmega5, avrxmega7) +as they need to save/restore RAMPZ for ELPM macros so it does +not interfere with data accesses. +*/ +#if defined (__AVR_HAVE_RAMPD__) + +#define __ELPM(addr) __ELPM_xmega__(addr) +#define __ELPM_word(addr) __ELPM_word_xmega__(addr) +#define __ELPM_dword(addr) __ELPM_dword_xmega__(addr) +#define __ELPM_float(addr) __ELPM_float_xmega__(addr) + +#else + +#if defined (__AVR_HAVE_LPMX__) + +#define __ELPM(addr) __ELPM_enhanced__(addr) +#define __ELPM_word(addr) __ELPM_word_enhanced__(addr) +#define __ELPM_dword(addr) __ELPM_dword_enhanced__(addr) +#define __ELPM_float(addr) __ELPM_float_enhanced__(addr) + +#else + +#define __ELPM(addr) __ELPM_classic__(addr) +#define __ELPM_word(addr) __ELPM_word_classic__(addr) +#define __ELPM_dword(addr) __ELPM_dword_classic__(addr) +#define __ELPM_float(addr) __ELPM_float_classic__(addr) + +#endif /* __AVR_HAVE_LPMX__ */ + +#endif /* __AVR_HAVE_RAMPD__ */ + +#endif /* !__DOXYGEN__ */ + +/** \ingroup avr_pgmspace + \def pgm_read_byte_far(address_long) + Read a byte from the program space with a 32-bit (far) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_byte_far(address_long) __ELPM((uint32_t)(address_long)) + +/** \ingroup avr_pgmspace + \def pgm_read_word_far(address_long) + Read a word from the program space with a 32-bit (far) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_word_far(address_long) __ELPM_word((uint32_t)(address_long)) + +/** \ingroup avr_pgmspace + \def pgm_read_dword_far(address_long) + Read a double word from the program space with a 32-bit (far) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_dword_far(address_long) __ELPM_dword((uint32_t)(address_long)) + +/** \ingroup avr_pgmspace + \def pgm_read_float_far(address_long) + Read a float from the program space with a 32-bit (far) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_float_far(address_long) __ELPM_float((uint32_t)(address_long)) + +/** \ingroup avr_pgmspace + \def pgm_read_ptr_far(address_long) + Read a pointer from the program space with a 32-bit (far) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_ptr_far(address_long) (void*)__ELPM_word((uint32_t)(address_long)) + +#endif /* RAMPZ or __DOXYGEN__ */ + +/** \ingroup avr_pgmspace + \def pgm_read_byte(address_short) + Read a byte from the program space with a 16-bit (near) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_byte(address_short) pgm_read_byte_near(address_short) + +/** \ingroup avr_pgmspace + \def pgm_read_word(address_short) + Read a word from the program space with a 16-bit (near) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_word(address_short) pgm_read_word_near(address_short) + +/** \ingroup avr_pgmspace + \def pgm_read_dword(address_short) + Read a double word from the program space with a 16-bit (near) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_dword(address_short) pgm_read_dword_near(address_short) + +/** \ingroup avr_pgmspace + \def pgm_read_float(address_short) + Read a float from the program space with a 16-bit (near) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_float(address_short) pgm_read_float_near(address_short) + +/** \ingroup avr_pgmspace + \def pgm_read_ptr(address_short) + Read a pointer from the program space with a 16-bit (near) address. + + \note The address is a byte address. + The address is in the program space. */ + +#define pgm_read_ptr(address_short) pgm_read_ptr_near(address_short) + +/** \ingroup avr_pgmspace + \def pgm_get_far_address(var) + + This macro facilitates the obtention of a 32 bit "far" pointer (only 24 bits + used) to data even passed the 64KB limit for the 16 bit ordinary pointer. It + is similar to the '&' operator, with some limitations. + + Comments: + + - The overhead is minimal and it's mainly due to the 32 bit size operation. + + - 24 bit sizes guarantees the code compatibility for use in future devices. + + - hh8() is an undocumented feature but seems to give the third significant byte + of a 32 bit data and accepts symbols, complementing the functionality of hi8() + and lo8(). There is not an equivalent assembler function to get the high + significant byte. + + - 'var' has to be resolved at linking time as an existing symbol, i.e, a simple + type variable name, an array name (not an indexed element of the array, if the + index is a constant the compiler does not complain but fails to get the address + if optimization is enabled), a struct name or a struct field name, a function + identifier, a linker defined identifier,... + + - The returned value is the identifier's VMA (virtual memory address) determined + by the linker and falls in the corresponding memory region. The AVR Harvard + architecture requires non overlapping VMA areas for the multiple address spaces + in the processor: Flash ROM, RAM, and EEPROM. Typical offset for this are + 0x00000000, 0x00800xx0, and 0x00810000 respectively, derived from the linker + script used and linker options. The value returned can be seen then as a + universal pointer. +*/ + +#define pgm_get_far_address(var) \ +({ \ + uint_farptr_t tmp; \ + \ + __asm__ __volatile__( \ + \ + "ldi %A0, lo8(%1)" "\n\t" \ + "ldi %B0, hi8(%1)" "\n\t" \ + "ldi %C0, hh8(%1)" "\n\t" \ + "clr %D0" "\n\t" \ + : \ + "=d" (tmp) \ + : \ + "p" (&(var)) \ + ); \ + tmp; \ +}) + + + +/** \ingroup avr_pgmspace + \fn const void * memchr_P(const void *s, int val, size_t len) + \brief Scan flash memory for a character. + + The memchr_P() function scans the first \p len bytes of the flash + memory area pointed to by \p s for the character \p val. The first + byte to match \p val (interpreted as an unsigned character) stops + the operation. + + \return The memchr_P() function returns a pointer to the matching + byte or \c NULL if the character does not occur in the given memory + area. */ +extern const void * memchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; + +/** \ingroup avr_pgmspace + \fn int memcmp_P(const void *s1, const void *s2, size_t len) + \brief Compare memory areas + + The memcmp_P() function compares the first \p len bytes of the memory + areas \p s1 and flash \p s2. The comparision is performed using unsigned + char operations. + + \returns The memcmp_P() function returns an integer less than, equal + to, or greater than zero if the first \p len bytes of \p s1 is found, + respectively, to be less than, to match, or be greater than the first + \p len bytes of \p s2. */ +extern int memcmp_P(const void *, const void *, size_t) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn void *memccpy_P (void *dest, const void *src, int val, size_t len) + + This function is similar to memccpy() except that \p src is pointer + to a string in program space. */ +extern void *memccpy_P(void *, const void *, int __val, size_t); + +/** \ingroup avr_pgmspace + \fn void *memcpy_P(void *dest, const void *src, size_t n) + + The memcpy_P() function is similar to memcpy(), except the src string + resides in program space. + + \returns The memcpy_P() function returns a pointer to dest. */ +extern void *memcpy_P(void *, const void *, size_t); + +/** \ingroup avr_pgmspace + \fn void *memmem_P(const void *s1, size_t len1, const void *s2, size_t len2) + + The memmem_P() function is similar to memmem() except that \p s2 is + pointer to a string in program space. */ +extern void *memmem_P(const void *, size_t, const void *, size_t) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn const void +memrchr_P(const void *src, int val, size_t len) + + The memrchr_P() function is like the memchr_P() function, except + that it searches backwards from the end of the \p len bytes pointed + to by \p src instead of forwards from the front. (Glibc, GNU extension.) + + \return The memrchr_P() function returns a pointer to the matching + byte or \c NULL if the character does not occur in the given memory + area. */ +extern const void * memrchr_P(const void *, int __val, size_t __len) __ATTR_CONST__; + +/** \ingroup avr_pgmspace + \fn char *strcat_P(char *dest, const char *src) + + The strcat_P() function is similar to strcat() except that the \e src + string must be located in program space (flash). + + \returns The strcat() function returns a pointer to the resulting string + \e dest. */ +extern char *strcat_P(char *, const char *); + +/** \ingroup avr_pgmspace + \fn const char *strchr_P(const char *s, int val) + \brief Locate character in program space string. + + The strchr_P() function locates the first occurrence of \p val + (converted to a char) in the string pointed to by \p s in program + space. The terminating null character is considered to be part of + the string. + + The strchr_P() function is similar to strchr() except that \p s is + pointer to a string in program space. + + \returns The strchr_P() function returns a pointer to the matched + character or \c NULL if the character is not found. */ +extern const char * strchr_P(const char *, int __val) __ATTR_CONST__; + +/** \ingroup avr_pgmspace + \fn const char *strchrnul_P(const char *s, int c) + + The strchrnul_P() function is like strchr_P() except that if \p c is + not found in \p s, then it returns a pointer to the null byte at the + end of \p s, rather than \c NULL. (Glibc, GNU extension.) + + \return The strchrnul_P() function returns a pointer to the matched + character, or a pointer to the null byte at the end of \p s (i.e., + \c s+strlen(s)) if the character is not found. */ +extern const char * strchrnul_P(const char *, int __val) __ATTR_CONST__; + +/** \ingroup avr_pgmspace + \fn int strcmp_P(const char *s1, const char *s2) + + The strcmp_P() function is similar to strcmp() except that \p s2 is + pointer to a string in program space. + + \returns The strcmp_P() function returns an integer less than, equal + to, or greater than zero if \p s1 is found, respectively, to be less + than, to match, or be greater than \p s2. A consequence of the + ordering used by strcmp_P() is that if \p s1 is an initial substring + of \p s2, then \p s1 is considered to be "less than" \p s2. */ +extern int strcmp_P(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strcpy_P(char *dest, const char *src) + + The strcpy_P() function is similar to strcpy() except that src is a + pointer to a string in program space. + + \returns The strcpy_P() function returns a pointer to the destination + string dest. */ +extern char *strcpy_P(char *, const char *); + +/** \ingroup avr_pgmspace + \fn int strcasecmp_P(const char *s1, const char *s2) + \brief Compare two strings ignoring case. + + The strcasecmp_P() function compares the two strings \p s1 and \p s2, + ignoring the case of the characters. + + \param s1 A pointer to a string in the devices SRAM. + \param s2 A pointer to a string in the devices Flash. + + \returns The strcasecmp_P() function returns an integer less than, + equal to, or greater than zero if \p s1 is found, respectively, to + be less than, to match, or be greater than \p s2. A consequence of + the ordering used by strcasecmp_P() is that if \p s1 is an initial + substring of \p s2, then \p s1 is considered to be "less than" \p s2. */ +extern int strcasecmp_P(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strcasestr_P(const char *s1, const char *s2) + + This funtion is similar to strcasestr() except that \p s2 is pointer + to a string in program space. */ +extern char *strcasestr_P(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn size_t strcspn_P(const char *s, const char *reject) + + The strcspn_P() function calculates the length of the initial segment + of \p s which consists entirely of characters not in \p reject. This + function is similar to strcspn() except that \p reject is a pointer + to a string in program space. + + \return The strcspn_P() function returns the number of characters in + the initial segment of \p s which are not in the string \p reject. + The terminating zero is not considered as a part of string. */ +extern size_t strcspn_P(const char *__s, const char * __reject) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn size_t strlcat_P(char *dst, const char *src, size_t siz) + \brief Concatenate two strings. + + The strlcat_P() function is similar to strlcat(), except that the \p src + string must be located in program space (flash). + + Appends \p src to string \p dst of size \p siz (unlike strncat(), + \p siz is the full size of \p dst, not space left). At most \p siz-1 + characters will be copied. Always NULL terminates (unless \p siz <= + \p strlen(dst)). + + \returns The strlcat_P() function returns strlen(src) + MIN(siz, + strlen(initial dst)). If retval >= siz, truncation occurred. */ +extern size_t strlcat_P (char *, const char *, size_t ); + +/** \ingroup avr_pgmspace + \fn size_t strlcpy_P(char *dst, const char *src, size_t siz) + \brief Copy a string from progmem to RAM. + + Copy \p src to string \p dst of size \p siz. At most \p siz-1 + characters will be copied. Always NULL terminates (unless \p siz == 0). + The strlcpy_P() function is similar to strlcpy() except that the + \p src is pointer to a string in memory space. + + \returns The strlcpy_P() function returns strlen(src). If + retval >= siz, truncation occurred. */ +extern size_t strlcpy_P (char *, const char *, size_t ); + +/** \ingroup avr_pgmspace + \fn size_t strnlen_P(const char *src, size_t len) + \brief Determine the length of a fixed-size string. + + The strnlen_P() function is similar to strnlen(), except that \c src is a + pointer to a string in program space. + + \returns The strnlen_P function returns strlen_P(src), if that is less than + \c len, or \c len if there is no '\\0' character among the first \c len + characters pointed to by \c src. */ +extern size_t strnlen_P(const char *, size_t) __ATTR_CONST__; /* program memory can't change */ + +/** \ingroup avr_pgmspace + \fn int strncmp_P(const char *s1, const char *s2, size_t n) + + The strncmp_P() function is similar to strcmp_P() except it only compares + the first (at most) n characters of s1 and s2. + + \returns The strncmp_P() function returns an integer less than, equal to, + or greater than zero if s1 (or the first n bytes thereof) is found, + respectively, to be less than, to match, or be greater than s2. */ +extern int strncmp_P(const char *, const char *, size_t) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn int strncasecmp_P(const char *s1, const char *s2, size_t n) + \brief Compare two strings ignoring case. + + The strncasecmp_P() function is similar to strcasecmp_P(), except it + only compares the first \p n characters of \p s1. + + \param s1 A pointer to a string in the devices SRAM. + \param s2 A pointer to a string in the devices Flash. + \param n The maximum number of bytes to compare. + + \returns The strncasecmp_P() function returns an integer less than, + equal to, or greater than zero if \p s1 (or the first \p n bytes + thereof) is found, respectively, to be less than, to match, or be + greater than \p s2. A consequence of the ordering used by + strncasecmp_P() is that if \p s1 is an initial substring of \p s2, + then \p s1 is considered to be "less than" \p s2. */ +extern int strncasecmp_P(const char *, const char *, size_t) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strncat_P(char *dest, const char *src, size_t len) + \brief Concatenate two strings. + + The strncat_P() function is similar to strncat(), except that the \e src + string must be located in program space (flash). + + \returns The strncat_P() function returns a pointer to the resulting string + dest. */ +extern char *strncat_P(char *, const char *, size_t); + +/** \ingroup avr_pgmspace + \fn char *strncpy_P(char *dest, const char *src, size_t n) + + The strncpy_P() function is similar to strcpy_P() except that not more + than n bytes of src are copied. Thus, if there is no null byte among the + first n bytes of src, the result will not be null-terminated. + + In the case where the length of src is less than that of n, the remainder + of dest will be padded with nulls. + + \returns The strncpy_P() function returns a pointer to the destination + string dest. */ +extern char *strncpy_P(char *, const char *, size_t); + +/** \ingroup avr_pgmspace + \fn char *strpbrk_P(const char *s, const char *accept) + + The strpbrk_P() function locates the first occurrence in the string + \p s of any of the characters in the flash string \p accept. This + function is similar to strpbrk() except that \p accept is a pointer + to a string in program space. + + \return The strpbrk_P() function returns a pointer to the character + in \p s that matches one of the characters in \p accept, or \c NULL + if no such character is found. The terminating zero is not considered + as a part of string: if one or both args are empty, the result will + \c NULL. */ +extern char *strpbrk_P(const char *__s, const char * __accept) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn const char *strrchr_P(const char *s, int val) + \brief Locate character in string. + + The strrchr_P() function returns a pointer to the last occurrence of + the character \p val in the flash string \p s. + + \return The strrchr_P() function returns a pointer to the matched + character or \c NULL if the character is not found. */ +extern const char * strrchr_P(const char *, int __val) __ATTR_CONST__; + +/** \ingroup avr_pgmspace + \fn char *strsep_P(char **sp, const char *delim) + \brief Parse a string into tokens. + + The strsep_P() function locates, in the string referenced by \p *sp, + the first occurrence of any character in the string \p delim (or the + terminating '\\0' character) and replaces it with a '\\0'. The + location of the next character after the delimiter character (or \c + NULL, if the end of the string was reached) is stored in \p *sp. An + ``empty'' field, i.e. one caused by two adjacent delimiter + characters, can be detected by comparing the location referenced by + the pointer returned in \p *sp to '\\0'. This function is similar to + strsep() except that \p delim is a pointer to a string in program + space. + + \return The strsep_P() function returns a pointer to the original + value of \p *sp. If \p *sp is initially \c NULL, strsep_P() returns + \c NULL. */ +extern char *strsep_P(char **__sp, const char * __delim); + +/** \ingroup avr_pgmspace + \fn size_t strspn_P(const char *s, const char *accept) + + The strspn_P() function calculates the length of the initial segment + of \p s which consists entirely of characters in \p accept. This + function is similar to strspn() except that \p accept is a pointer + to a string in program space. + + \return The strspn_P() function returns the number of characters in + the initial segment of \p s which consist only of characters from \p + accept. The terminating zero is not considered as a part of string. */ +extern size_t strspn_P(const char *__s, const char * __accept) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strstr_P(const char *s1, const char *s2) + \brief Locate a substring. + + The strstr_P() function finds the first occurrence of the substring + \p s2 in the string \p s1. The terminating '\\0' characters are not + compared. The strstr_P() function is similar to strstr() except that + \p s2 is pointer to a string in program space. + + \returns The strstr_P() function returns a pointer to the beginning + of the substring, or NULL if the substring is not found. If \p s2 + points to a string of zero length, the function returns \p s1. */ +extern char *strstr_P(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strtok_P(char *s, const char * delim) + \brief Parses the string into tokens. + + strtok_P() parses the string \p s into tokens. The first call to + strtok_P() should have \p s as its first argument. Subsequent calls + should have the first argument set to NULL. If a token ends with a + delimiter, this delimiting character is overwritten with a '\\0' and a + pointer to the next character is saved for the next call to strtok_P(). + The delimiter string \p delim may be different for each call. + + The strtok_P() function is similar to strtok() except that \p delim + is pointer to a string in program space. + + \returns The strtok_P() function returns a pointer to the next token or + NULL when no more tokens are found. + + \note strtok_P() is NOT reentrant. For a reentrant version of this + function see strtok_rP(). + */ +extern char *strtok_P(char *__s, const char * __delim); + +/** \ingroup avr_pgmspace + \fn char *strtok_rP (char *string, const char *delim, char **last) + \brief Parses string into tokens. + + The strtok_rP() function parses \p string into tokens. The first call to + strtok_rP() should have string as its first argument. Subsequent calls + should have the first argument set to NULL. If a token ends with a + delimiter, this delimiting character is overwritten with a '\\0' and a + pointer to the next character is saved for the next call to strtok_rP(). + The delimiter string \p delim may be different for each call. \p last is + a user allocated char* pointer. It must be the same while parsing the + same string. strtok_rP() is a reentrant version of strtok_P(). + + The strtok_rP() function is similar to strtok_r() except that \p delim + is pointer to a string in program space. + + \returns The strtok_rP() function returns a pointer to the next token or + NULL when no more tokens are found. */ +extern char *strtok_rP(char *__s, const char * __delim, char **__last); + +/** \ingroup avr_pgmspace + \fn size_t strlen_PF(uint_farptr_t s) + \brief Obtain the length of a string + + The strlen_PF() function is similar to strlen(), except that \e s is a + far pointer to a string in program space. + + \param s A far pointer to the string in flash + + \returns The strlen_PF() function returns the number of characters in + \e s. The contents of RAMPZ SFR are undefined when the function returns. */ +extern size_t strlen_PF(uint_farptr_t src) __ATTR_CONST__; /* program memory can't change */ + +/** \ingroup avr_pgmspace + \fn size_t strnlen_PF(uint_farptr_t s, size_t len) + \brief Determine the length of a fixed-size string + + The strnlen_PF() function is similar to strnlen(), except that \e s is a + far pointer to a string in program space. + + \param s A far pointer to the string in Flash + \param len The maximum number of length to return + + \returns The strnlen_PF function returns strlen_P(\e s), if that is less + than \e len, or \e len if there is no '\\0' character among the first \e + len characters pointed to by \e s. The contents of RAMPZ SFR are + undefined when the function returns. */ +extern size_t strnlen_PF(uint_farptr_t src, size_t len) __ATTR_CONST__; /* program memory can't change */ + +/** \ingroup avr_pgmspace + \fn void *memcpy_PF(void *dest, uint_farptr_t src, size_t n) + \brief Copy a memory block from flash to SRAM + + The memcpy_PF() function is similar to memcpy(), except the data + is copied from the program space and is addressed using a far pointer. + + \param dest A pointer to the destination buffer + \param src A far pointer to the origin of data in flash memory + \param n The number of bytes to be copied + + \returns The memcpy_PF() function returns a pointer to \e dst. The contents + of RAMPZ SFR are undefined when the function returns. */ +extern void *memcpy_PF(void *dest, uint_farptr_t src, size_t len); + +/** \ingroup avr_pgmspace + \fn char *strcpy_PF(char *dst, uint_farptr_t src) + \brief Duplicate a string + + The strcpy_PF() function is similar to strcpy() except that \e src is a far + pointer to a string in program space. + + \param dst A pointer to the destination string in SRAM + \param src A far pointer to the source string in Flash + + \returns The strcpy_PF() function returns a pointer to the destination + string \e dst. The contents of RAMPZ SFR are undefined when the funcion + returns. */ +extern char *strcpy_PF(char *dest, uint_farptr_t src); + +/** \ingroup avr_pgmspace + \fn char *strncpy_PF(char *dst, uint_farptr_t src, size_t n) + \brief Duplicate a string until a limited length + + The strncpy_PF() function is similar to strcpy_PF() except that not more + than \e n bytes of \e src are copied. Thus, if there is no null byte among + the first \e n bytes of \e src, the result will not be null-terminated. + + In the case where the length of \e src is less than that of \e n, the + remainder of \e dst will be padded with nulls. + + \param dst A pointer to the destination string in SRAM + \param src A far pointer to the source string in Flash + \param n The maximum number of bytes to copy + + \returns The strncpy_PF() function returns a pointer to the destination + string \e dst. The contents of RAMPZ SFR are undefined when the function + returns. */ +extern char *strncpy_PF(char *dest, uint_farptr_t src, size_t len); + +/** \ingroup avr_pgmspace + \fn char *strcat_PF(char *dst, uint_farptr_t src) + \brief Concatenates two strings + + The strcat_PF() function is similar to strcat() except that the \e src + string must be located in program space (flash) and is addressed using + a far pointer + + \param dst A pointer to the destination string in SRAM + \param src A far pointer to the string to be appended in Flash + + \returns The strcat_PF() function returns a pointer to the resulting + string \e dst. The contents of RAMPZ SFR are undefined when the function + returns */ +extern char *strcat_PF(char *dest, uint_farptr_t src); + +/** \ingroup avr_pgmspace + \fn size_t strlcat_PF(char *dst, uint_farptr_t src, size_t n) + \brief Concatenate two strings + + The strlcat_PF() function is similar to strlcat(), except that the \e src + string must be located in program space (flash) and is addressed using + a far pointer. + + Appends src to string dst of size \e n (unlike strncat(), \e n is the + full size of \e dst, not space left). At most \e n-1 characters + will be copied. Always NULL terminates (unless \e n <= strlen(\e dst)). + + \param dst A pointer to the destination string in SRAM + \param src A far pointer to the source string in Flash + \param n The total number of bytes allocated to the destination string + + \returns The strlcat_PF() function returns strlen(\e src) + MIN(\e n, + strlen(initial \e dst)). If retval >= \e n, truncation occurred. The + contents of RAMPZ SFR are undefined when the funcion returns. */ +extern size_t strlcat_PF(char *dst, uint_farptr_t src, size_t siz); + +/** \ingroup avr_pgmspace + \fn char *strncat_PF(char *dst, uint_farptr_t src, size_t n) + \brief Concatenate two strings + + The strncat_PF() function is similar to strncat(), except that the \e src + string must be located in program space (flash) and is addressed using a + far pointer. + + \param dst A pointer to the destination string in SRAM + \param src A far pointer to the source string in Flash + \param n The maximum number of bytes to append + + \returns The strncat_PF() function returns a pointer to the resulting + string \e dst. The contents of RAMPZ SFR are undefined when the function + returns. */ +extern char *strncat_PF(char *dest, uint_farptr_t src, size_t len); + +/** \ingroup avr_pgmspace + \fn int strcmp_PF(const char *s1, uint_farptr_t s2) + \brief Compares two strings + + The strcmp_PF() function is similar to strcmp() except that \e s2 is a far + pointer to a string in program space. + + \param s1 A pointer to the first string in SRAM + \param s2 A far pointer to the second string in Flash + + \returns The strcmp_PF() function returns an integer less than, equal to, + or greater than zero if \e s1 is found, respectively, to be less than, to + match, or be greater than \e s2. The contents of RAMPZ SFR are undefined + when the function returns. */ +extern int strcmp_PF(const char *s1, uint_farptr_t s2) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn int strncmp_PF(const char *s1, uint_farptr_t s2, size_t n) + \brief Compare two strings with limited length + + The strncmp_PF() function is similar to strcmp_PF() except it only + compares the first (at most) \e n characters of \e s1 and \e s2. + + \param s1 A pointer to the first string in SRAM + \param s2 A far pointer to the second string in Flash + \param n The maximum number of bytes to compare + + \returns The strncmp_PF() function returns an integer less than, equal + to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, + respectively, to be less than, to match, or be greater than \e s2. The + contents of RAMPZ SFR are undefined when the function returns. */ +extern int strncmp_PF(const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn int strcasecmp_PF(const char *s1, uint_farptr_t s2) + \brief Compare two strings ignoring case + + The strcasecmp_PF() function compares the two strings \e s1 and \e s2, ignoring + the case of the characters. + + \param s1 A pointer to the first string in SRAM + \param s2 A far pointer to the second string in Flash + + \returns The strcasecmp_PF() function returns an integer less than, equal + to, or greater than zero if \e s1 is found, respectively, to be less than, to + match, or be greater than \e s2. The contents of RAMPZ SFR are undefined + when the function returns. */ +extern int strcasecmp_PF(const char *s1, uint_farptr_t s2) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn int strncasecmp_PF(const char *s1, uint_farptr_t s2, size_t n) + \brief Compare two strings ignoring case + + The strncasecmp_PF() function is similar to strcasecmp_PF(), except it + only compares the first \e n characters of \e s1 and the string in flash is + addressed using a far pointer. + + \param s1 A pointer to a string in SRAM + \param s2 A far pointer to a string in Flash + \param n The maximum number of bytes to compare + + \returns The strncasecmp_PF() function returns an integer less than, equal + to, or greater than zero if \e s1 (or the first \e n bytes thereof) is found, + respectively, to be less than, to match, or be greater than \e s2. The + contents of RAMPZ SFR are undefined when the function returns. */ +extern int strncasecmp_PF(const char *s1, uint_farptr_t s2, size_t n) __ATTR_PURE__; + +/** \ingroup avr_pgmspace + \fn char *strstr_PF(const char *s1, uint_farptr_t s2) + \brief Locate a substring. + + The strstr_PF() function finds the first occurrence of the substring \c s2 + in the string \c s1. The terminating '\\0' characters are not + compared. + The strstr_PF() function is similar to strstr() except that \c s2 is a + far pointer to a string in program space. + + \returns The strstr_PF() function returns a pointer to the beginning of the + substring, or NULL if the substring is not found. + If \c s2 points to a string of zero length, the function returns \c s1. The + contents of RAMPZ SFR are undefined when the function returns. */ +extern char *strstr_PF(const char *s1, uint_farptr_t s2); + +/** \ingroup avr_pgmspace + \fn size_t strlcpy_PF(char *dst, uint_farptr_t src, size_t siz) + \brief Copy a string from progmem to RAM. + + Copy src to string dst of size siz. At most siz-1 characters will be + copied. Always NULL terminates (unless siz == 0). + + \returns The strlcpy_PF() function returns strlen(src). If retval >= siz, + truncation occurred. The contents of RAMPZ SFR are undefined when the + function returns. */ +extern size_t strlcpy_PF(char *dst, uint_farptr_t src, size_t siz); + +/** \ingroup avr_pgmspace + \fn int memcmp_PF(const void *s1, uint_farptr_t s2, size_t len) + \brief Compare memory areas + + The memcmp_PF() function compares the first \p len bytes of the memory + areas \p s1 and flash \p s2. The comparision is performed using unsigned + char operations. It is an equivalent of memcmp_P() function, except + that it is capable working on all FLASH including the exteded area + above 64kB. + + \returns The memcmp_PF() function returns an integer less than, equal + to, or greater than zero if the first \p len bytes of \p s1 is found, + respectively, to be less than, to match, or be greater than the first + \p len bytes of \p s2. */ +extern int memcmp_PF(const void *, uint_farptr_t, size_t) __ATTR_PURE__; + +#ifdef __DOXYGEN__ +/** \ingroup avr_pgmspace + \fn size_t strlen_P(const char *src) + + The strlen_P() function is similar to strlen(), except that src is a + pointer to a string in program space. + + \returns The strlen_P() function returns the number of characters in src. + + \note strlen_P() is implemented as an inline function in the avr/pgmspace.h + header file, which will check if the length of the string is a constant + and known at compile time. If it is not known at compile time, the macro + will issue a call to __strlen_P() which will then calculate the length + of the string as normal. +*/ +static inline size_t strlen_P(const char * s); +#else +extern size_t __strlen_P(const char *) __ATTR_CONST__; /* internal helper function */ +__attribute__((__always_inline__)) static __inline__ size_t strlen_P(const char * s); +static __inline__ size_t strlen_P(const char *s) { + return __builtin_constant_p(__builtin_strlen(s)) + ? __builtin_strlen(s) : __strlen_P(s); +} +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __PGMSPACE_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/portpins.h b/hardware/tools/avr/avr/include/avr/portpins.h new file mode 100644 index 0000000000000000000000000000000000000000..c179edfabe5c315c04f3eec405588c76a274912d --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/portpins.h @@ -0,0 +1,549 @@ +/* Copyright (c) 2003 Theodore A. Roth + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_PORTPINS_H_ +#define _AVR_PORTPINS_H_ 1 + +/* This file should only be included from , never directly. */ + +#ifndef _AVR_IO_H_ +# error "Include instead of this file." +#endif + +/* Define Generic PORTn, DDn, and PINn values. */ + +/* Port Data Register (generic) */ +#define PORT7 7 +#define PORT6 6 +#define PORT5 5 +#define PORT4 4 +#define PORT3 3 +#define PORT2 2 +#define PORT1 1 +#define PORT0 0 + +/* Port Data Direction Register (generic) */ +#define DD7 7 +#define DD6 6 +#define DD5 5 +#define DD4 4 +#define DD3 3 +#define DD2 2 +#define DD1 1 +#define DD0 0 + +/* Port Input Pins (generic) */ +#define PIN7 7 +#define PIN6 6 +#define PIN5 5 +#define PIN4 4 +#define PIN3 3 +#define PIN2 2 +#define PIN1 1 +#define PIN0 0 + +/* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */ + +/* PORT A */ + +#if defined(PA0) && !defined(PORTA0) +# define PORTA0 PA0 +#elif defined(PORTA0) && !defined(PA0) +# define PA0 PORTA0 +#endif +#if defined(PA1) && !defined(PORTA1) +# define PORTA1 PA1 +#elif defined(PORTA1) && !defined(PA1) +# define PA1 PORTA1 +#endif +#if defined(PA2) && !defined(PORTA2) +# define PORTA2 PA2 +#elif defined(PORTA2) && !defined(PA2) +# define PA2 PORTA2 +#endif +#if defined(PA3) && !defined(PORTA3) +# define PORTA3 PA3 +#elif defined(PORTA3) && !defined(PA3) +# define PA3 PORTA3 +#endif +#if defined(PA4) && !defined(PORTA4) +# define PORTA4 PA4 +#elif defined(PORTA4) && !defined(PA4) +# define PA4 PORTA4 +#endif +#if defined(PA5) && !defined(PORTA5) +# define PORTA5 PA5 +#elif defined(PORTA5) && !defined(PA5) +# define PA5 PORTA5 +#endif +#if defined(PA6) && !defined(PORTA6) +# define PORTA6 PA6 +#elif defined(PORTA6) && !defined(PA6) +# define PA6 PORTA6 +#endif +#if defined(PA7) && !defined(PORTA7) +# define PORTA7 PA7 +#elif defined(PORTA7) && !defined(PA7) +# define PA7 PORTA7 +#endif + +/* PORT B */ + +#if defined(PB0) && !defined(PORTB0) +# define PORTB0 PB0 +#elif defined(PORTB0) && !defined(PB0) +# define PB0 PORTB0 +#endif +#if defined(PB1) && !defined(PORTB1) +# define PORTB1 PB1 +#elif defined(PORTB1) && !defined(PB1) +# define PB1 PORTB1 +#endif +#if defined(PB2) && !defined(PORTB2) +# define PORTB2 PB2 +#elif defined(PORTB2) && !defined(PB2) +# define PB2 PORTB2 +#endif +#if defined(PB3) && !defined(PORTB3) +# define PORTB3 PB3 +#elif defined(PORTB3) && !defined(PB3) +# define PB3 PORTB3 +#endif +#if defined(PB4) && !defined(PORTB4) +# define PORTB4 PB4 +#elif defined(PORTB4) && !defined(PB4) +# define PB4 PORTB4 +#endif +#if defined(PB5) && !defined(PORTB5) +# define PORTB5 PB5 +#elif defined(PORTB5) && !defined(PB5) +# define PB5 PORTB5 +#endif +#if defined(PB6) && !defined(PORTB6) +# define PORTB6 PB6 +#elif defined(PORTB6) && !defined(PB6) +# define PB6 PORTB6 +#endif +#if defined(PB7) && !defined(PORTB7) +# define PORTB7 PB7 +#elif defined(PORTB7) && !defined(PB7) +# define PB7 PORTB7 +#endif + +/* PORT C */ + +#if defined(PC0) && !defined(PORTC0) +# define PORTC0 PC0 +#elif defined(PORTC0) && !defined(PC0) +# define PC0 PORTC0 +#endif +#if defined(PC1) && !defined(PORTC1) +# define PORTC1 PC1 +#elif defined(PORTC1) && !defined(PC1) +# define PC1 PORTC1 +#endif +#if defined(PC2) && !defined(PORTC2) +# define PORTC2 PC2 +#elif defined(PORTC2) && !defined(PC2) +# define PC2 PORTC2 +#endif +#if defined(PC3) && !defined(PORTC3) +# define PORTC3 PC3 +#elif defined(PORTC3) && !defined(PC3) +# define PC3 PORTC3 +#endif +#if defined(PC4) && !defined(PORTC4) +# define PORTC4 PC4 +#elif defined(PORTC4) && !defined(PC4) +# define PC4 PORTC4 +#endif +#if defined(PC5) && !defined(PORTC5) +# define PORTC5 PC5 +#elif defined(PORTC5) && !defined(PC5) +# define PC5 PORTC5 +#endif +#if defined(PC6) && !defined(PORTC6) +# define PORTC6 PC6 +#elif defined(PORTC6) && !defined(PC6) +# define PC6 PORTC6 +#endif +#if defined(PC7) && !defined(PORTC7) +# define PORTC7 PC7 +#elif defined(PORTC7) && !defined(PC7) +# define PC7 PORTC7 +#endif + +/* PORT D */ + +#if defined(PD0) && !defined(PORTD0) +# define PORTD0 PD0 +#elif defined(PORTD0) && !defined(PD0) +# define PD0 PORTD0 +#endif +#if defined(PD1) && !defined(PORTD1) +# define PORTD1 PD1 +#elif defined(PORTD1) && !defined(PD1) +# define PD1 PORTD1 +#endif +#if defined(PD2) && !defined(PORTD2) +# define PORTD2 PD2 +#elif defined(PORTD2) && !defined(PD2) +# define PD2 PORTD2 +#endif +#if defined(PD3) && !defined(PORTD3) +# define PORTD3 PD3 +#elif defined(PORTD3) && !defined(PD3) +# define PD3 PORTD3 +#endif +#if defined(PD4) && !defined(PORTD4) +# define PORTD4 PD4 +#elif defined(PORTD4) && !defined(PD4) +# define PD4 PORTD4 +#endif +#if defined(PD5) && !defined(PORTD5) +# define PORTD5 PD5 +#elif defined(PORTD5) && !defined(PD5) +# define PD5 PORTD5 +#endif +#if defined(PD6) && !defined(PORTD6) +# define PORTD6 PD6 +#elif defined(PORTD6) && !defined(PD6) +# define PD6 PORTD6 +#endif +#if defined(PD7) && !defined(PORTD7) +# define PORTD7 PD7 +#elif defined(PORTD7) && !defined(PD7) +# define PD7 PORTD7 +#endif + +/* PORT E */ + +#if defined(PE0) && !defined(PORTE0) +# define PORTE0 PE0 +#elif defined(PORTE0) && !defined(PE0) +# define PE0 PORTE0 +#endif +#if defined(PE1) && !defined(PORTE1) +# define PORTE1 PE1 +#elif defined(PORTE1) && !defined(PE1) +# define PE1 PORTE1 +#endif +#if defined(PE2) && !defined(PORTE2) +# define PORTE2 PE2 +#elif defined(PORTE2) && !defined(PE2) +# define PE2 PORTE2 +#endif +#if defined(PE3) && !defined(PORTE3) +# define PORTE3 PE3 +#elif defined(PORTE3) && !defined(PE3) +# define PE3 PORTE3 +#endif +#if defined(PE4) && !defined(PORTE4) +# define PORTE4 PE4 +#elif defined(PORTE4) && !defined(PE4) +# define PE4 PORTE4 +#endif +#if defined(PE5) && !defined(PORTE5) +# define PORTE5 PE5 +#elif defined(PORTE5) && !defined(PE5) +# define PE5 PORTE5 +#endif +#if defined(PE6) && !defined(PORTE6) +# define PORTE6 PE6 +#elif defined(PORTE6) && !defined(PE6) +# define PE6 PORTE6 +#endif +#if defined(PE7) && !defined(PORTE7) +# define PORTE7 PE7 +#elif defined(PORTE7) && !defined(PE7) +# define PE7 PORTE7 +#endif + +/* PORT F */ + +#if defined(PF0) && !defined(PORTF0) +# define PORTF0 PF0 +#elif defined(PORTF0) && !defined(PF0) +# define PF0 PORTF0 +#endif +#if defined(PF1) && !defined(PORTF1) +# define PORTF1 PF1 +#elif defined(PORTF1) && !defined(PF1) +# define PF1 PORTF1 +#endif +#if defined(PF2) && !defined(PORTF2) +# define PORTF2 PF2 +#elif defined(PORTF2) && !defined(PF2) +# define PF2 PORTF2 +#endif +#if defined(PF3) && !defined(PORTF3) +# define PORTF3 PF3 +#elif defined(PORTF3) && !defined(PF3) +# define PF3 PORTF3 +#endif +#if defined(PF4) && !defined(PORTF4) +# define PORTF4 PF4 +#elif defined(PORTF4) && !defined(PF4) +# define PF4 PORTF4 +#endif +#if defined(PF5) && !defined(PORTF5) +# define PORTF5 PF5 +#elif defined(PORTF5) && !defined(PF5) +# define PF5 PORTF5 +#endif +#if defined(PF6) && !defined(PORTF6) +# define PORTF6 PF6 +#elif defined(PORTF6) && !defined(PF6) +# define PF6 PORTF6 +#endif +#if defined(PF7) && !defined(PORTF7) +# define PORTF7 PF7 +#elif defined(PORTF7) && !defined(PF7) +# define PF7 PORTF7 +#endif + +/* PORT G */ + +#if defined(PG0) && !defined(PORTG0) +# define PORTG0 PG0 +#elif defined(PORTG0) && !defined(PG0) +# define PG0 PORTG0 +#endif +#if defined(PG1) && !defined(PORTG1) +# define PORTG1 PG1 +#elif defined(PORTG1) && !defined(PG1) +# define PG1 PORTG1 +#endif +#if defined(PG2) && !defined(PORTG2) +# define PORTG2 PG2 +#elif defined(PORTG2) && !defined(PG2) +# define PG2 PORTG2 +#endif +#if defined(PG3) && !defined(PORTG3) +# define PORTG3 PG3 +#elif defined(PORTG3) && !defined(PG3) +# define PG3 PORTG3 +#endif +#if defined(PG4) && !defined(PORTG4) +# define PORTG4 PG4 +#elif defined(PORTG4) && !defined(PG4) +# define PG4 PORTG4 +#endif +#if defined(PG5) && !defined(PORTG5) +# define PORTG5 PG5 +#elif defined(PORTG5) && !defined(PG5) +# define PG5 PORTG5 +#endif +#if defined(PG6) && !defined(PORTG6) +# define PORTG6 PG6 +#elif defined(PORTG6) && !defined(PG6) +# define PG6 PORTG6 +#endif +#if defined(PG7) && !defined(PORTG7) +# define PORTG7 PG7 +#elif defined(PORTG7) && !defined(PG7) +# define PG7 PORTG7 +#endif + +/* PORT H */ + +#if defined(PH0) && !defined(PORTH0) +# define PORTH0 PH0 +#elif defined(PORTH0) && !defined(PH0) +# define PH0 PORTH0 +#endif +#if defined(PH1) && !defined(PORTH1) +# define PORTH1 PH1 +#elif defined(PORTH1) && !defined(PH1) +# define PH1 PORTH1 +#endif +#if defined(PH2) && !defined(PORTH2) +# define PORTH2 PH2 +#elif defined(PORTH2) && !defined(PH2) +# define PH2 PORTH2 +#endif +#if defined(PH3) && !defined(PORTH3) +# define PORTH3 PH3 +#elif defined(PORTH3) && !defined(PH3) +# define PH3 PORTH3 +#endif +#if defined(PH4) && !defined(PORTH4) +# define PORTH4 PH4 +#elif defined(PORTH4) && !defined(PH4) +# define PH4 PORTH4 +#endif +#if defined(PH5) && !defined(PORTH5) +# define PORTH5 PH5 +#elif defined(PORTH5) && !defined(PH5) +# define PH5 PORTH5 +#endif +#if defined(PH6) && !defined(PORTH6) +# define PORTH6 PH6 +#elif defined(PORTH6) && !defined(PH6) +# define PH6 PORTH6 +#endif +#if defined(PH7) && !defined(PORTH7) +# define PORTH7 PH7 +#elif defined(PORTH7) && !defined(PH7) +# define PH7 PORTH7 +#endif + +/* PORT J */ + +#if defined(PJ0) && !defined(PORTJ0) +# define PORTJ0 PJ0 +#elif defined(PORTJ0) && !defined(PJ0) +# define PJ0 PORTJ0 +#endif +#if defined(PJ1) && !defined(PORTJ1) +# define PORTJ1 PJ1 +#elif defined(PORTJ1) && !defined(PJ1) +# define PJ1 PORTJ1 +#endif +#if defined(PJ2) && !defined(PORTJ2) +# define PORTJ2 PJ2 +#elif defined(PORTJ2) && !defined(PJ2) +# define PJ2 PORTJ2 +#endif +#if defined(PJ3) && !defined(PORTJ3) +# define PORTJ3 PJ3 +#elif defined(PORTJ3) && !defined(PJ3) +# define PJ3 PORTJ3 +#endif +#if defined(PJ4) && !defined(PORTJ4) +# define PORTJ4 PJ4 +#elif defined(PORTJ4) && !defined(PJ4) +# define PJ4 PORTJ4 +#endif +#if defined(PJ5) && !defined(PORTJ5) +# define PORTJ5 PJ5 +#elif defined(PORTJ5) && !defined(PJ5) +# define PJ5 PORTJ5 +#endif +#if defined(PJ6) && !defined(PORTJ6) +# define PORTJ6 PJ6 +#elif defined(PORTJ6) && !defined(PJ6) +# define PJ6 PORTJ6 +#endif +#if defined(PJ7) && !defined(PORTJ7) +# define PORTJ7 PJ7 +#elif defined(PORTJ7) && !defined(PJ7) +# define PJ7 PORTJ7 +#endif + +/* PORT K */ + +#if defined(PK0) && !defined(PORTK0) +# define PORTK0 PK0 +#elif defined(PORTK0) && !defined(PK0) +# define PK0 PORTK0 +#endif +#if defined(PK1) && !defined(PORTK1) +# define PORTK1 PK1 +#elif defined(PORTK1) && !defined(PK1) +# define PK1 PORTK1 +#endif +#if defined(PK2) && !defined(PORTK2) +# define PORTK2 PK2 +#elif defined(PORTK2) && !defined(PK2) +# define PK2 PORTK2 +#endif +#if defined(PK3) && !defined(PORTK3) +# define PORTK3 PK3 +#elif defined(PORTK3) && !defined(PK3) +# define PK3 PORTK3 +#endif +#if defined(PK4) && !defined(PORTK4) +# define PORTK4 PK4 +#elif defined(PORTK4) && !defined(PK4) +# define PK4 PORTK4 +#endif +#if defined(PK5) && !defined(PORTK5) +# define PORTK5 PK5 +#elif defined(PORTK5) && !defined(PK5) +# define PK5 PORTK5 +#endif +#if defined(PK6) && !defined(PORTK6) +# define PORTK6 PK6 +#elif defined(PORTK6) && !defined(PK6) +# define PK6 PORTK6 +#endif +#if defined(PK7) && !defined(PORTK7) +# define PORTK7 PK7 +#elif defined(PORTK7) && !defined(PK7) +# define PK7 PORTK7 +#endif + +/* PORT L */ + +#if defined(PL0) && !defined(PORTL0) +# define PORTL0 PL0 +#elif defined(PORTL0) && !defined(PL0) +# define PL0 PORTL0 +#endif +#if defined(PL1) && !defined(PORTL1) +# define PORTL1 PL1 +#elif defined(PORTL1) && !defined(PL1) +# define PL1 PORTL1 +#endif +#if defined(PL2) && !defined(PORTL2) +# define PORTL2 PL2 +#elif defined(PORTL2) && !defined(PL2) +# define PL2 PORTL2 +#endif +#if defined(PL3) && !defined(PORTL3) +# define PORTL3 PL3 +#elif defined(PORTL3) && !defined(PL3) +# define PL3 PORTL3 +#endif +#if defined(PL4) && !defined(PORTL4) +# define PORTL4 PL4 +#elif defined(PORTL4) && !defined(PL4) +# define PL4 PORTL4 +#endif +#if defined(PL5) && !defined(PORTL5) +# define PORTL5 PL5 +#elif defined(PORTL5) && !defined(PL5) +# define PL5 PORTL5 +#endif +#if defined(PL6) && !defined(PORTL6) +# define PORTL6 PL6 +#elif defined(PORTL6) && !defined(PL6) +# define PL6 PORTL6 +#endif +#if defined(PL7) && !defined(PORTL7) +# define PORTL7 PL7 +#elif defined(PORTL7) && !defined(PL7) +# define PL7 PORTL7 +#endif + +#endif /* _AVR_PORTPINS_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/power.h b/hardware/tools/avr/avr/include/avr/power.h new file mode 100644 index 0000000000000000000000000000000000000000..ede878f943b41f5635039239845fa692c588e60a --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/power.h @@ -0,0 +1,1946 @@ +/* Copyright (c) 2006, 2007, 2008 Eric B. Weddington + Copyright (c) 2011 Frédéric Nadeau + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_POWER_H_ +#define _AVR_POWER_H_ 1 + +#include +#include + + +/** \file */ +/** \defgroup avr_power : Power Reduction Management + +\code #include \endcode + +Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that +allow you to reduce power consumption by disabling or enabling various on-board +peripherals as needed. Some devices have the XTAL Divide Control Register +(XDIV) which offer similar functionality as System Clock Prescale +Register (CLKPR). + +There are many macros in this header file that provide an easy interface +to enable or disable on-board peripherals to reduce power. See the table below. + +\note Not all AVR devices have a Power Reduction Register (for example +the ATmega8). On those devices without a Power Reduction Register, the +power reduction macros are not available.. + +\note Not all AVR devices contain the same peripherals (for example, the LCD +interface), or they will be named differently (for example, USART and +USART0). Please consult your device's datasheet, or the header file, to +find out which macros are applicable to your device. + +\note For device using the XTAL Divide Control Register (XDIV), when prescaler +is used, Timer/Counter0 can only be used in asynchronous mode. Keep in mind +that Timer/Counter0 source shall be less than ¼th of peripheral clock. +Therefore, when using a typical 32.768 kHz crystal, one shall not scale +the clock below 131.072 kHz. + +*/ + + +/** \addtogroup avr_power + +\anchor avr_powermacros + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Power MacroDescription
power_aca_disable()Disable the Analog Comparator on PortA.
power_aca_enable()Enable the Analog Comparator on PortA.
power_adc_enable()Enable the Analog to Digital Converter module.
power_adc_disable()Disable the Analog to Digital Converter module.
power_adca_disable()Disable the Analog to Digital Converter module on PortA
power_adca_enable()Enable the Analog to Digital Converter module on PortA
power_evsys_disable()Disable the EVSYS module
power_evsys_enable()Enable the EVSYS module
power_hiresc_disable()Disable the HIRES module on PortC
power_hiresc_enable()Enable the HIRES module on PortC
power_lcd_enable()Enable the LCD module.
power_lcd_disable().Disable the LCD module.
power_pga_enable()Enable the Programmable Gain Amplifier module.
power_pga_disable()Disable the Programmable Gain Amplifier module.
power_pscr_enable()Enable the Reduced Power Stage Controller module.
power_pscr_disable()Disable the Reduced Power Stage Controller module.
power_psc0_enable()Enable the Power Stage Controller 0 module.
power_psc0_disable()Disable the Power Stage Controller 0 module.
power_psc1_enable()Enable the Power Stage Controller 1 module.
power_psc1_disable()Disable the Power Stage Controller 1 module.
power_psc2_enable()Enable the Power Stage Controller 2 module.
power_psc2_disable()Disable the Power Stage Controller 2 module.
power_ram0_enable()Enable the SRAM block 0 .
power_ram0_disable()Disable the SRAM block 0.
power_ram1_enable()Enable the SRAM block 1 .
power_ram1_disable()Disable the SRAM block 1.
power_ram2_enable()Enable the SRAM block 2 .
power_ram2_disable()Disable the SRAM block 2.
power_ram3_enable()Enable the SRAM block 3 .
power_ram3_disable()Disable the SRAM block 3.
power_rtc_disable()Disable the RTC module
power_rtc_enable()Enable the RTC module
power_spi_enable()Enable the Serial Peripheral Interface module.
power_spi_disable()Disable the Serial Peripheral Interface module.
power_spic_disable()Disable the SPI module on PortC
power_spic_enable()Enable the SPI module on PortC
power_spid_disable()Disable the SPI module on PortD
power_spid_enable()Enable the SPI module on PortD
power_tc0c_disable()Disable the TC0 module on PortC
power_tc0c_enable()Enable the TC0 module on PortC
power_tc0d_disable()Disable the TC0 module on PortD
power_tc0d_enable()Enable the TC0 module on PortD
power_tc0e_disable()Disable the TC0 module on PortE
power_tc0e_enable()Enable the TC0 module on PortE
power_tc0f_disable()Disable the TC0 module on PortF
power_tc0f_enable()Enable the TC0 module on PortF
power_tc1c_disable()Disable the TC1 module on PortC
power_tc1c_enable()Enable the TC1 module on PortC
power_twic_disable()Disable the Two Wire Interface module on PortC
power_twic_enable()Enable the Two Wire Interface module on PortC
power_twie_disable()Disable the Two Wire Interface module on PortE
power_twie_enable()Enable the Two Wire Interface module on PortE
power_timer0_enable()Enable the Timer 0 module.
power_timer0_disable()Disable the Timer 0 module.
power_timer1_enable()Enable the Timer 1 module.
power_timer1_disable()Disable the Timer 1 module.
power_timer2_enable()Enable the Timer 2 module.
power_timer2_disable()Disable the Timer 2 module.
power_timer3_enable()Enable the Timer 3 module.
power_timer3_disable()Disable the Timer 3 module.
power_timer4_enable()Enable the Timer 4 module.
power_timer4_disable()Disable the Timer 4 module.
power_timer5_enable()Enable the Timer 5 module.
power_timer5_disable()Disable the Timer 5 module.
power_twi_enable()Enable the Two Wire Interface module.
power_twi_disable()Disable the Two Wire Interface module.
power_usart_enable()Enable the USART module.
power_usart_disable()Disable the USART module.
power_usart0_enable()Enable the USART 0 module.
power_usart0_disable()Disable the USART 0 module.
power_usart1_enable()Enable the USART 1 module.
power_usart1_disable()Disable the USART 1 module.
power_usart2_enable()Enable the USART 2 module.
power_usart2_disable()Disable the USART 2 module.
power_usart3_enable()Enable the USART 3 module.
power_usart3_disable()Disable the USART 3 module.
power_usartc0_disable() Disable the USART0 module on PortC
power_usartc0_enable() Enable the USART0 module on PortC
power_usartd0_disable() Disable the USART0 module on PortD
power_usartd0_enable() Enable the USART0 module on PortD
power_usarte0_disable() Disable the USART0 module on PortE
power_usarte0_enable() Enable the USART0 module on PortE
power_usartf0_disable() Disable the USART0 module on PortF
power_usartf0_enable() Enable the USART0 module on PortF
power_usb_enable()Enable the USB module.
power_usb_disable()Disable the USB module.
power_usi_enable()Enable the Universal Serial Interface module.
power_usi_disable()Disable the Universal Serial Interface module.
power_vadc_enable()Enable the Voltage ADC module.
power_vadc_disable()Disable the Voltage ADC module.
power_all_enable()Enable all modules.
power_all_disable()Disable all modules.
+
+ + +@} */ + +#if defined(__AVR_HAVE_PRR_PRADC) +#define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC)) +#define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC)) +#endif + +#if defined(__AVR_HAVE_PRR_PRCAN) +#define power_can_enable() (PRR &= (uint8_t)~(1 << PRCAN)) +#define power_can_disable() (PRR |= (uint8_t)(1 << PRCAN)) +#endif + +#if defined(__AVR_HAVE_PRR_PRLCD) +#define power_lcd_enable() (PRR &= (uint8_t)~(1 << PRLCD)) +#define power_lcd_disable() (PRR |= (uint8_t)(1 << PRLCD)) +#endif + +#if defined(__AVR_HAVE_PRR_PRLIN) +#define power_lin_enable() (PRR &= (uint8_t)~(1 << PRLIN)) +#define power_lin_disable() (PRR |= (uint8_t)(1 << PRLIN)) +#endif + +#if defined(__AVR_HAVE_PRR_PRPSC) +#define power_psc_enable() (PRR &= (uint8_t)~(1 << PRPSC)) +#define power_psc_disable() (PRR |= (uint8_t)(1 << PRPSC)) +#endif + +#if defined(__AVR_HAVE_PRR_PRPSC0) +#define power_psc0_enable() (PRR &= (uint8_t)~(1 << PRPSC0)) +#define power_psc0_disable() (PRR |= (uint8_t)(1 << PRPSC0)) +#endif + +#if defined(__AVR_HAVE_PRR_PRPSC1) +#define power_psc1_enable() (PRR &= (uint8_t)~(1 << PRPSC1)) +#define power_psc1_disable() (PRR |= (uint8_t)(1 << PRPSC1)) +#endif + +#if defined(__AVR_HAVE_PRR_PRPSC2) +#define power_psc2_enable() (PRR &= (uint8_t)~(1 << PRPSC2)) +#define power_psc2_disable() (PRR |= (uint8_t)(1 << PRPSC2)) +#endif + +#if defined(__AVR_HAVE_PRR_PRPSCR) +#define power_pscr_enable() (PRR &= (uint8_t)~(1 << PRPSCR)) +#define power_pscr_disable() (PRR |= (uint8_t)(1 << PRPSCR)) +#endif + +#if defined(__AVR_HAVE_PRR_PRSPI) +#define power_spi_enable() (PRR &= (uint8_t)~(1 << PRSPI)) +#define power_spi_disable() (PRR |= (uint8_t)(1 << PRSPI)) +#endif + +#if defined(__AVR_HAVE_PRR_PRTIM0) +#define power_timer0_enable() (PRR &= (uint8_t)~(1 << PRTIM0)) +#define power_timer0_disable() (PRR |= (uint8_t)(1 << PRTIM0)) +#endif + +#if defined(__AVR_HAVE_PRR_PRTIM1) +#define power_timer1_enable() (PRR &= (uint8_t)~(1 << PRTIM1)) +#define power_timer1_disable() (PRR |= (uint8_t)(1 << PRTIM1)) +#endif + +#if defined(__AVR_HAVE_PRR_PRTIM2) +#define power_timer2_enable() (PRR &= (uint8_t)~(1 << PRTIM2)) +#define power_timer2_disable() (PRR |= (uint8_t)(1 << PRTIM2)) +#endif + +#if defined(__AVR_HAVE_PRR_PRTWI) +#define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI)) +#define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI)) +#endif + +#if defined(__AVR_HAVE_PRR_PRUSART) +#define power_usart_enable() (PRR &= (uint8_t)~(1 << PRUSART)) +#define power_usart_disable() (PRR |= (uint8_t)(1 << PRUSART)) +#endif + +#if defined(__AVR_HAVE_PRR_PRUSART0) +#define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0)) +#define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0)) +#endif + +#if defined(__AVR_HAVE_PRR_PRUSART1) +#define power_usart1_enable() (PRR &= (uint8_t)~(1 << PRUSART1)) +#define power_usart1_disable() (PRR |= (uint8_t)(1 << PRUSART1)) +#endif + +#if defined(__AVR_HAVE_PRR_PRUSI) +#define power_usi_enable() (PRR &= (uint8_t)~(1 << PRUSI)) +#define power_usi_disable() (PRR |= (uint8_t)(1 << PRUSI)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRADC) +#define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC)) +#define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRCO) +#define power_clock_output_enable() (PRR0 &= (uint8_t)~(1 << PRCO)) +#define power_clock_output_disable() (PRR0 |= (uint8_t)(1 << PRCO)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRCRC) +#define power_crc_enable() (PRR0 &= (uint8_t)~(1 << PRCRC)) +#define power_crc_disable() (PRR0 |= (uint8_t)(1 << PRCRC)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRCU) +#define power_crypto_enable() (PRR0 &= (uint8_t)~(1 << PRCU)) +#define power_crypto_disable() (PRR0 |= (uint8_t)(1 << PRCU)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRDS) +#define power_irdriver_enable() (PRR0 &= (uint8_t)~(1 << PRDS)) +#define power_irdriver_disable() (PRR0 |= (uint8_t)(1 << PRDS)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRLFR) +#define power_lfreceiver_enable() (PRR0 &= (uint8_t)~(1 << PRLFR)) +#define power_lfreceiver_disable() (PRR0 |= (uint8_t)(1 << PRLFR)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRLFRS) +#define power_lfrs_enable() (PRR0 &= (uint8_t)~(1 << PRLFRS)) +#define power_lfrs_disable() (PRR0 |= (uint8_t)(1 << PRLFRS)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRLIN) +#define power_lin_enable() (PRR0 &= (uint8_t)~(1 << PRLIN)) +#define power_lin_disable() (PRR0 |= (uint8_t)(1 << PRLIN)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRPGA) +#define power_pga_enable() (PRR0 &= (uint8_t)~(1 << PRPGA)) +#define power_pga_disable() (PRR0 |= (uint8_t)(1 << PRPGA)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRRXDC) +#define power_receive_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRRXDC)) +#define power_receive_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRRXDC)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRSPI) +#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI)) +#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRSPI0) +#define power_spi_enable() (PRR0 &= (uint8_t)~(1 << PRSPI0)) +#define power_spi_disable() (PRR0 |= (uint8_t)(1 << PRSPI0)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRT0) +#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRT0)) +#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRT0)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTIM0) +#define power_timer0_enable() (PRR0 &= (uint8_t)~(1 << PRTIM0)) +#define power_timer0_disable() (PRR0 |= (uint8_t)(1 << PRTIM0)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRT1) +#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRT1)) +#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRT1)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTIM1) +#define power_timer1_enable() (PRR0 &= (uint8_t)~(1 << PRTIM1)) +#define power_timer1_disable() (PRR0 |= (uint8_t)(1 << PRTIM1)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRT2) +#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRT2)) +#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRT2)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTIM2) +#define power_timer2_enable() (PRR0 &= (uint8_t)~(1 << PRTIM2)) +#define power_timer2_disable() (PRR0 |= (uint8_t)(1 << PRTIM2)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRT3) +#define power_timer3_enable() (PRR0 &= (uint8_t)~(1 << PRT3)) +#define power_timer3_disable() (PRR0 |= (uint8_t)(1 << PRT3)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTM) +#define power_timermodulator_enable() (PRR0 &= (uint8_t)~(1 << PRTM)) +#define power_timermodulator_disable() (PRR0 |= (uint8_t)(1 << PRTM)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTWI) +#define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI)) +#define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTWI0) +#define power_twi_enable() (PRR0 &= (uint8_t)~(1 << PRTWI0)) +#define power_twi_disable() (PRR0 |= (uint8_t)(1 << PRTWI0)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTWI1) +#define power_twi1_enable() (PRR0 &= (uint8_t)~(1 << PRTWI1)) +#define power_twi1_disable() (PRR0 |= (uint8_t)(1 << PRTWI1)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRTXDC) +#define power_transmit_dsp_control_enable() (PRR0 &= (uint8_t)~(1 << PRTXDC)) +#define power_transmit_dsp_control_disable() (PRR0 |= (uint8_t)(1 << PRTXDC)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRUSART0) +#define power_usart0_enable() (PRR0 &= (uint8_t)~(1 << PRUSART0)) +#define power_usart0_disable() (PRR0 |= (uint8_t)(1 << PRUSART0)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRUSART1) +#define power_usart1_enable() (PRR0 &= (uint8_t)~(1 << PRUSART1)) +#define power_usart1_disable() (PRR0 |= (uint8_t)(1 << PRUSART1)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRVADC) +#define power_vadc_enable() (PRR0 &= (uint8_t)~(1 << PRVADC)) +#define power_vadc_disable() (PRR0 |= (uint8_t)(1 << PRVADC)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRVM) +#define power_voltage_monitor_enable() (PRR0 &= (uint8_t)~(1 << PRVM)) +#define power_voltage_monitor_disable() (PRR0 |= (uint8_t)(1 << PRVM)) +#endif + +#if defined(__AVR_HAVE_PRR0_PRVRM) +#define power_vrm_enable() (PRR0 &= (uint8_t)~(1 << PRVRM)) +#define power_vrm_disable() (PRR0 |= (uint8_t)(1 << PRVRM)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRAES) +#define power_aes_enable() (PRR1 &= (uint8_t)~(1 << PRAES)) +#define power_aes_disable() (PRR1 |= (uint8_t)(1 << PRAES)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRCI) +#define power_cinterface_enable() (PRR1 &= (uint8_t)~(1 << PRCI)) +#define power_cinterface_disable() (PRR1 |= (uint8_t)(1 << PRCI)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRHSSPI) +#define power_hsspi_enable() (PRR1 &= (uint8_t)~(1 << PRHSSPI)) +#define power_hsspi_disable() (PRR1 |= (uint8_t)(1 << PRHSSPI)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRKB) +#define power_kb_enable() (PRR1 &= (uint8_t)~(1 << PRKB)) +#define power_kb_disable() (PRR1 |= (uint8_t)(1 << PRKB)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRLFPH) +#define power_lfph_enable() (PRR1 &= (uint8_t)~(1 << PRLFPH)) +#define power_lfph_disable() (PRR1 |= (uint8_t)(1 << PRLFPH)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRLFR) +#define power_lfreceiver_enable() (PRR1 &= (uint8_t)~(1 << PRLFR)) +#define power_lfreceiver_disable() (PRR1 |= (uint8_t)(1 << PRLFR)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRLFTP) +#define power_lftp_enable() (PRR1 &= (uint8_t)~(1 << PRLFTP)) +#define power_lftp_disable() (PRR1 |= (uint8_t)(1 << PRLFTP)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRSCI) +#define power_sci_enable() (PRR1 &= (uint8_t)~(1 << PRSCI)) +#define power_sci_disable() (PRR1 |= (uint8_t)(1 << PRSCI)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRSPI) +#define power_spi_enable() (PRR1 &= (uint8_t)~(1 << PRSPI)) +#define power_spi_disable() (PRR1 |= (uint8_t)(1 << PRSPI)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRSPI1) +#define power_spi1_enable() (PRR1 &= (uint8_t)~(1 << PRSPI1)) +#define power_spi1_disable() (PRR1 |= (uint8_t)(1 << PRSPI1)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRT1) +#define power_timer1_enable() (PRR1 &= (uint8_t)~(1 << PRT1)) +#define power_timer1_disable() (PRR1 |= (uint8_t)(1 << PRT1)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRT2) +#define power_timer2_enable() (PRR1 &= (uint8_t)~(1 << PRT2)) +#define power_timer2_disable() (PRR1 |= (uint8_t)(1 << PRT2)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRT3) +#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRT3)) +#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRT3)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRT4) +#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRT4)) +#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRT4)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRT5) +#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRT5)) +#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRT5)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRTIM3) +#define power_timer3_enable() (PRR1 &= (uint8_t)~(1 << PRTIM3)) +#define power_timer3_disable() (PRR1 |= (uint8_t)(1 << PRTIM3)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRTIM4) +#define power_timer4_enable() (PRR1 &= (uint8_t)~(1 << PRTIM4)) +#define power_timer4_disable() (PRR1 |= (uint8_t)(1 << PRTIM4)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRTIM5) +#define power_timer5_enable() (PRR1 &= (uint8_t)~(1 << PRTIM5)) +#define power_timer5_disable() (PRR1 |= (uint8_t)(1 << PRTIM5)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRTRX24) +#define power_transceiver_enable() (PRR1 &= (uint8_t)~(1 << PRTRX24)) +#define power_transceiver_disable() (PRR1 |= (uint8_t)(1 << PRTRX24)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRTWI1) +#define power_twi1_enable() (PRR1 &= (uint8_t)~(1 << PRTWI1)) +#define power_twi1_disable() (PRR1 |= (uint8_t)(1 << PRTWI1)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRUSART1) +#define power_usart1_enable() (PRR1 &= (uint8_t)~(1 << PRUSART1)) +#define power_usart1_disable() (PRR1 |= (uint8_t)(1 << PRUSART1)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRUSART2) +#define power_usart2_enable() (PRR1 &= (uint8_t)~(1 << PRUSART2)) +#define power_usart2_disable() (PRR1 |= (uint8_t)(1 << PRUSART2)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRUSART3) +#define power_usart3_enable() (PRR1 &= (uint8_t)~(1 << PRUSART3)) +#define power_usart3_disable() (PRR1 |= (uint8_t)(1 << PRUSART3)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRUSB) +#define power_usb_enable() (PRR1 &= (uint8_t)~(1 << PRUSB)) +#define power_usb_disable() (PRR1 |= (uint8_t)(1 << PRUSB)) +#endif + +#if defined(__AVR_HAVE_PRR1_PRUSBH) +#define power_usbh_enable() (PRR1 &= (uint8_t)~(1 << PRUSBH)) +#define power_usbh_disable() (PRR1 |= (uint8_t)(1 << PRUSBH)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRDF) +#define power_data_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRDF)) +#define power_data_fifo_disable() (PRR2 |= (uint8_t)(1 << PRDF)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRIDS) +#define power_id_scan_enable() (PRR2 &= (uint8_t)~(1 << PRIDS)) +#define power_id_scan_disable() (PRR2 |= (uint8_t)(1 << PRIDS)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRRAM0) +#define power_ram0_enable() (PRR2 &= (uint8_t)~(1 << PRRAM0)) +#define power_ram0_disable() (PRR2 |= (uint8_t)(1 << PRRAM0)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRRAM1) +#define power_ram1_enable() (PRR2 &= (uint8_t)~(1 << PRRAM1)) +#define power_ram1_disable() (PRR2 |= (uint8_t)(1 << PRRAM1)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRRAM2) +#define power_ram2_enable() (PRR2 &= (uint8_t)~(1 << PRRAM2)) +#define power_ram2_disable() (PRR2 |= (uint8_t)(1 << PRRAM2)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRRAM3) +#define power_ram3_enable() (PRR2 &= (uint8_t)~(1 << PRRAM3)) +#define power_ram3_disable() (PRR2 |= (uint8_t)(1 << PRRAM3)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRRS) +#define power_rssi_buffer_enable() (PRR2 &= (uint8_t)~(1 << PRRS)) +#define power_rssi_buffer_disable() (PRR2 |= (uint8_t)(1 << PRRS)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRSF) +#define power_preamble_rssi_fifo_enable() (PRR2 &= (uint8_t)~(1 << PRSF)) +#define power_preamble_rssi_fifo_disable() (PRR2 |= (uint8_t)(1 << PRSF)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRSPI1) +#define power_spi1_enable() (PRR2 &= (uint8_t)~(1 << PRSPI1)) +#define power_spi1_disable() (PRR2 |= (uint8_t)(1 << PRSPI1)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRSPI2) +#define power_spi2_enable() (PRR2 &= (uint8_t)~(1 << PRSPI2)) +#define power_spi2_disable() (PRR2 |= (uint8_t)(1 << PRSPI2)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRSSM) +#define power_sequencer_state_machine_enable() (PRR2 &= (uint8_t)~(1 << PRSSM)) +#define power_sequencer_state_machine_disable() (PRR2 |= (uint8_t)(1 << PRSSM)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRTM) +#define power_tx_modulator_enable() (PRR2 &= (uint8_t)~(1 << PRTM)) +#define power_tx_modulator_disable() (PRR2 |= (uint8_t)(1 << PRTM)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRTWI1) +#define power_twi1_enable() (PRR2 &= (uint8_t)~(1 << PRTWI1)) +#define power_twi1_disable() (PRR2 |= (uint8_t)(1 << PRTWI1)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRTWI2) +#define power_twi2_enable() (PRR2 &= (uint8_t)~(1 << PRTWI2)) +#define power_twi2_disable() (PRR2 |= (uint8_t)(1 << PRTWI2)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRUSART2) +#define power_usart2_enable() (PRR2 &= (uint8_t)~(1 << PRUSART2)) +#define power_usart2_disable() (PRR2 |= (uint8_t)(1 << PRUSART2)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRXA) +#define power_rx_buffer_A_enable() (PRR2 &= (uint8_t)~(1 << PRXA)) +#define power_rx_buffer_A_disable() (PRR2 |= (uint8_t)(1 << PRXA)) +#endif + +#if defined(__AVR_HAVE_PRR2_PRXB) +#define power_rx_buffer_B_enable() (PRR2 &= (uint8_t)~(1 << PRXB)) +#define power_rx_buffer_B_disable() (PRR2 |= (uint8_t)(1 << PRXB)) +#endif + +#if defined(__AVR_HAVE_PRGEN_AES) +#define power_aes_enable() (PR_PRGEN &= (uint8_t)~(PR_AES_bm)) +#define power_aes_disable() (PR_PRGEN |= (uint8_t)PR_AES_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_DMA) +#define power_dma_enable() (PR_PRGEN &= (uint8_t)~(PR_DMA_bm)) +#define power_dma_disable() (PR_PRGEN |= (uint8_t)PR_DMA_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_EBI) +#define power_ebi_enable() (PR_PRGEN &= (uint8_t)~(PR_EBI_bm)) +#define power_ebi_disable() (PR_PRGEN |= (uint8_t)PR_EBI_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_EDMA) +#define power_edma_enable() (PR_PRGEN &= (uint8_t)~(PR_EDMA_bm)) +#define power_edma_disable() (PR_PRGEN |= (uint8_t)PR_EDMA_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_EVSYS) +#define power_evsys_enable() (PR_PRGEN &= (uint8_t)~(PR_EVSYS_bm)) +#define power_evsys_disable() (PR_PRGEN |= (uint8_t)PR_EVSYS_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_LCD) +#define power_lcd_enable() (PR_PRGEN &= (uint8_t)~(PR_LCD_bm)) +#define power_lcd_disable() (PR_PRGEN |= (uint8_t)PR_LCD_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_RTC) +#define power_rtc_enable() (PR_PRGEN &= (uint8_t)~(PR_RTC_bm)) +#define power_rtc_disable() (PR_PRGEN |= (uint8_t)PR_RTC_bm) +#endif + +#if defined(__AVR_HAVE_PRGEN_USB) +#define power_usb_enable() (PR_PRGEN &= (uint8_t)~(PR_USB_bm)) +#define power_usb_disable() (PR_PRGEN &= (uint8_t)(PR_USB_bm)) +#endif + +#if defined(__AVR_HAVE_PRGEN_XCL) +#define power_xcl_enable() (PR_PRGEN &= (uint8_t)~(PR_XCL_bm)) +#define power_xcl_disable() (PR_PRGEN |= (uint8_t)PR_XCL_bm) +#endif + +#if defined(__AVR_HAVE_PRPA_AC) +#define power_aca_enable() (PR_PRPA &= (uint8_t)~(PR_AC_bm)) +#define power_aca_disable() (PR_PRPA |= (uint8_t)PR_AC_bm) +#endif + +#if defined(__AVR_HAVE_PRPA_ADC) +#define power_adca_enable() (PR_PRPA &= (uint8_t)~(PR_ADC_bm)) +#define power_adca_disable() (PR_PRPA |= (uint8_t)PR_ADC_bm) +#endif + +#if defined(__AVR_HAVE_PRPA_DAC) +#define power_daca_enable() (PR_PRPA &= (uint8_t)~(PR_DAC_bm)) +#define power_daca_disable() (PR_PRPA |= (uint8_t)PR_DAC_bm) +#endif + +#if defined(__AVR_HAVE_PRPB_AC) +#define power_acb_enable() (PR_PRPB &= (uint8_t)~(PR_AC_bm)) +#define power_acb_disable() (PR_PRPB |= (uint8_t)PR_AC_bm) +#endif + +#if defined(__AVR_HAVE_PRPB_ADC) +#define power_adcb_enable() (PR_PRPB &= (uint8_t)~(PR_ADC_bm)) +#define power_adcb_disable() (PR_PRPB |= (uint8_t)PR_ADC_bm) +#endif + +#if defined(__AVR_HAVE_PRPB_DAC) +#define power_dacb_enable() (PR_PRPB &= (uint8_t)~(PR_DAC_bm)) +#define power_dacb_disable() (PR_PRPB |= (uint8_t)PR_DAC_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_HIRES) +#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm)) +#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_SPI) +#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) +#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_TC0) +#define power_tc0c_enable() (PR_PRPC &= (uint8_t)~(PR_TC0_bm)) +#define power_tc0c_disable() (PR_PRPC |= (uint8_t)PR_TC0_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_TC1) +#define power_tc1c_enable() (PR_PRPC &= (uint8_t)~(PR_TC1_bm)) +#define power_tc1c_disable() (PR_PRPC |= (uint8_t)PR_TC1_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_TC4) +#define power_tc4c_enable() (PR_PRPC &= (uint8_t)~(PR_TC4_bm)) +#define power_tc4c_disable() (PR_PRPC |= (uint8_t)PR_TC4_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_TC5) +#define power_tc5c_enable() (PR_PRPC &= (uint8_t)~(PR_TC5_bm)) +#define power_tc5c_disable() (PR_PRPC |= (uint8_t)PR_TC5_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_TWI) +#define power_twic_enable() (PR_PRPC &= (uint8_t)~(PR_TWI_bm)) +#define power_twic_disable() (PR_PRPC |= (uint8_t)PR_TWI_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_USART0) +#define power_usartc0_enable() (PR_PRPC &= (uint8_t)~(PR_USART0_bm)) +#define power_usartc0_disable() (PR_PRPC |= (uint8_t)PR_USART0_bm) +#endif + +#if defined(__AVR_HAVE_PRPC_USART1) +#define power_usartc1_enable() (PR_PRPC &= (uint8_t)~(PR_USART1_bm)) +#define power_usartc1_disable() (PR_PRPC |= (uint8_t)PR_USART1_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_HIRES) +#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm)) +#define power_hiresd_disable() (PR_PRPD |= (uint8_t)PR_HIRES_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_SPI) +#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm)) +#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_TC0) +#define power_tc0d_enable() (PR_PRPD &= (uint8_t)~(PR_TC0_bm)) +#define power_tc0d_disable() (PR_PRPD |= (uint8_t)PR_TC0_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_TC1) +#define power_tc1d_enable() (PR_PRPD &= (uint8_t)~(PR_TC1_bm)) +#define power_tc1d_disable() (PR_PRPD |= (uint8_t)PR_TC1_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_TC5) +#define power_tc5d_enable() (PR_PRPD &= (uint8_t)~(PR_TC5_bm)) +#define power_tc5d_disable() (PR_PRPD |= (uint8_t)PR_TC5_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_TWI) +#define power_twid_enable() (PR_PRPD &= (uint8_t)~(PR_TWI_bm)) +#define power_twid_disable() (PR_PRPD |= (uint8_t)PR_TWI_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_USART0) +#define power_usartd0_enable() (PR_PRPD &= (uint8_t)~(PR_USART0_bm)) +#define power_usartd0_disable() (PR_PRPD |= (uint8_t)PR_USART0_bm) +#endif + +#if defined(__AVR_HAVE_PRPD_USART1) +#define power_usartd1_enable() (PR_PRPD &= (uint8_t)~(PR_USART1_bm)) +#define power_usartd1_disable() (PR_PRPD |= (uint8_t)PR_USART1_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_HIRES) +#define power_hirese_enable() (PR_PRPE &= (uint8_t)~(PR_HIRES_bm)) +#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_SPI) +#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm)) +#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_TC0) +#define power_tc0e_enable() (PR_PRPE &= (uint8_t)~(PR_TC0_bm)) +#define power_tc0e_disable() (PR_PRPE |= (uint8_t)PR_TC0_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_TC1) +#define power_tc1e_enable() (PR_PRPE &= (uint8_t)~(PR_TC1_bm)) +#define power_tc1e_disable() (PR_PRPE |= (uint8_t)PR_TC1_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_TWI) +#define power_twie_enable() (PR_PRPE &= (uint8_t)~(PR_TWI_bm)) +#define power_twie_disable() (PR_PRPE |= (uint8_t)PR_TWI_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_USART0) +#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm)) +#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm) +#endif + +#if defined(__AVR_HAVE_PRPE_USART1) +#define power_usarte1_enable() (PR_PRPE &= (uint8_t)~(PR_USART1_bm)) +#define power_usarte1_disable() (PR_PRPE |= (uint8_t)PR_USART1_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_HIRES) +#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm)) +#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_SPI) +#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm)) +#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_TC0) +#define power_tc0f_enable() (PR_PRPF &= (uint8_t)~(PR_TC0_bm)) +#define power_tc0f_disable() (PR_PRPF |= (uint8_t)PR_TC0_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_TC1) +#define power_tc1f_enable() (PR_PRPF &= (uint8_t)~(PR_TC1_bm)) +#define power_tc1f_disable() (PR_PRPF |= (uint8_t)PR_TC1_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_TWI) +#define power_twif_enable() (PR_PRPF &= (uint8_t)~(PR_TWI_bm)) +#define power_twif_disable() (PR_PRPF |= (uint8_t)PR_TWI_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_USART0) +#define power_usartf0_enable() (PR_PRPF &= (uint8_t)~(PR_USART0_bm)) +#define power_usartf0_disable() (PR_PRPF |= (uint8_t)PR_USART0_bm) +#endif + +#if defined(__AVR_HAVE_PRPF_USART1) +#define power_usartf1_enable() (PR_PRPF &= (uint8_t)~(PR_USART1_bm)) +#define power_usartf1_disable() (PR_PRPF |= (uint8_t)PR_USART1_bm) +#endif + +static __inline void +__attribute__ ((__always_inline__)) +__power_all_enable() +{ +#ifdef __AVR_HAVE_PRR + PRR &= (uint8_t)~(__AVR_HAVE_PRR); +#endif + +#ifdef __AVR_HAVE_PRR0 + PRR0 &= (uint8_t)~(__AVR_HAVE_PRR0); +#endif + +#ifdef __AVR_HAVE_PRR1 + PRR1 &= (uint8_t)~(__AVR_HAVE_PRR1); +#endif + +#ifdef __AVR_HAVE_PRR2 + PRR2 &= (uint8_t)~(__AVR_HAVE_PRR2); +#endif + +#ifdef __AVR_HAVE_PRGEN + PR_PRGEN &= (uint8_t)~(__AVR_HAVE_PRGEN); +#endif + +#ifdef __AVR_HAVE_PRPA + PR_PRPA &= (uint8_t)~(__AVR_HAVE_PRPA); +#endif + +#ifdef __AVR_HAVE_PRPB + PR_PRPB &= (uint8_t)~(__AVR_HAVE_PRPB); +#endif + +#ifdef __AVR_HAVE_PRPC + PR_PRPC &= (uint8_t)~(__AVR_HAVE_PRPC); +#endif + +#ifdef __AVR_HAVE_PRPD + PR_PRPD &= (uint8_t)~(__AVR_HAVE_PRPD); +#endif + +#ifdef __AVR_HAVE_PRPE + PR_PRPE &= (uint8_t)~(__AVR_HAVE_PRPE); +#endif + +#ifdef __AVR_HAVE_PRPF + PR_PRPF &= (uint8_t)~(__AVR_HAVE_PRPF); +#endif +} + +static __inline void +__attribute__ ((__always_inline__)) +__power_all_disable() +{ +#ifdef __AVR_HAVE_PRR + PRR |= (uint8_t)(__AVR_HAVE_PRR); +#endif + +#ifdef __AVR_HAVE_PRR0 + PRR0 |= (uint8_t)(__AVR_HAVE_PRR0); +#endif + +#ifdef __AVR_HAVE_PRR1 + PRR1 |= (uint8_t)(__AVR_HAVE_PRR1); +#endif + +#ifdef __AVR_HAVE_PRR2 + PRR2 |= (uint8_t)(__AVR_HAVE_PRR2); +#endif + +#ifdef __AVR_HAVE_PRGEN + PR_PRGEN |= (uint8_t)(__AVR_HAVE_PRGEN); +#endif + +#ifdef __AVR_HAVE_PRPA + PR_PRPA |= (uint8_t)(__AVR_HAVE_PRPA); +#endif + +#ifdef __AVR_HAVE_PRPB + PR_PRPB |= (uint8_t)(__AVR_HAVE_PRPB); +#endif + +#ifdef __AVR_HAVE_PRPC + PR_PRPC |= (uint8_t)(__AVR_HAVE_PRPC); +#endif + +#ifdef __AVR_HAVE_PRPD + PR_PRPD |= (uint8_t)(__AVR_HAVE_PRPD); +#endif + +#ifdef __AVR_HAVE_PRPE + PR_PRPE |= (uint8_t)(__AVR_HAVE_PRPE); +#endif + +#ifdef __AVR_HAVE_PRPF + PR_PRPF |= (uint8_t)(__AVR_HAVE_PRPF); +#endif +} + +#ifndef __DOXYGEN__ +#ifndef power_all_enable +#define power_all_enable() __power_all_enable() +#endif + +#ifndef power_all_disable +#define power_all_disable() __power_all_disable() +#endif +#endif /* !__DOXYGEN__ */ + + +#if defined(__AVR_AT90CAN32__) \ +|| defined(__AVR_AT90CAN64__) \ +|| defined(__AVR_AT90CAN128__) \ +|| defined(__AVR_AT90PWM1__) \ +|| defined(__AVR_AT90PWM2__) \ +|| defined(__AVR_AT90PWM2B__) \ +|| defined(__AVR_AT90PWM3__) \ +|| defined(__AVR_AT90PWM3B__) \ +|| defined(__AVR_AT90PWM81__) \ +|| defined(__AVR_AT90PWM161__) \ +|| defined(__AVR_AT90PWM216__) \ +|| defined(__AVR_AT90PWM316__) \ +|| defined(__AVR_AT90SCR100__) \ +|| defined(__AVR_AT90USB646__) \ +|| defined(__AVR_AT90USB647__) \ +|| defined(__AVR_AT90USB82__) \ +|| defined(__AVR_AT90USB1286__) \ +|| defined(__AVR_AT90USB1287__) \ +|| defined(__AVR_AT90USB162__) \ +|| defined(__AVR_ATA5505__) \ +|| defined(__AVR_ATA5272__) \ +|| defined(__AVR_ATA6617C__) \ +|| defined(__AVR_ATA664251__) \ +|| defined(__AVR_ATmega1280__) \ +|| defined(__AVR_ATmega1281__) \ +|| defined(__AVR_ATmega1284__) \ +|| defined(__AVR_ATmega128RFA1__) \ +|| defined(__AVR_ATmega1284RFR2__) \ +|| defined(__AVR_ATmega128RFR2__) \ +|| defined(__AVR_ATmega1284P__) \ +|| defined(__AVR_ATmega162__) \ +|| defined(__AVR_ATmega164A__) \ +|| defined(__AVR_ATmega164P__) \ +|| defined(__AVR_ATmega164PA__) \ +|| defined(__AVR_ATmega165__) \ +|| defined(__AVR_ATmega165A__) \ +|| defined(__AVR_ATmega165P__) \ +|| defined(__AVR_ATmega165PA__) \ +|| defined(__AVR_ATmega168__) \ +|| defined(__AVR_ATmega168A__) \ +|| defined(__AVR_ATmega168P__) \ +|| defined(__AVR_ATmega168PA__) \ +|| defined(__AVR_ATmega168PB__) \ +|| defined(__AVR_ATmega169__) \ +|| defined(__AVR_ATmega169A__) \ +|| defined(__AVR_ATmega169P__) \ +|| defined(__AVR_ATmega169PA__) \ +|| defined(__AVR_ATmega16M1__) \ +|| defined(__AVR_ATmega16U2__) \ +|| defined(__AVR_ATmega16U4__) \ +|| defined(__AVR_ATmega2560__) \ +|| defined(__AVR_ATmega2561__) \ +|| defined(__AVR_ATmega2564RFR2__) \ +|| defined(__AVR_ATmega256RFR2__) \ +|| defined(__AVR_ATmega324A__) \ +|| defined(__AVR_ATmega324P__) \ +|| defined(__AVR_ATmega324PA__) \ +|| defined(__AVR_ATmega324PB__) \ +|| defined(__AVR_ATmega325__) \ +|| defined(__AVR_ATmega325A__) \ +|| defined(__AVR_ATmega325P__) \ +|| defined(__AVR_ATmega325PA__) \ +|| defined(__AVR_ATmega3250__) \ +|| defined(__AVR_ATmega3250A__) \ +|| defined(__AVR_ATmega3250P__) \ +|| defined(__AVR_ATmega3250PA__) \ +|| defined(__AVR_ATmega328__) \ +|| defined(__AVR_ATmega328P__) \ +|| defined(__AVR_ATmega328PB__) \ +|| defined(__AVR_ATmega329__) \ +|| defined(__AVR_ATmega329A__) \ +|| defined(__AVR_ATmega329P__) \ +|| defined(__AVR_ATmega329PA__) \ +|| defined(__AVR_ATmega3290__) \ +|| defined(__AVR_ATmega3290A__) \ +|| defined(__AVR_ATmega3290P__) \ +|| defined(__AVR_ATmega3290PA__) \ +|| defined(__AVR_ATmega32C1__) \ +|| defined(__AVR_ATmega32M1__) \ +|| defined(__AVR_ATmega32U2__) \ +|| defined(__AVR_ATmega32U4__) \ +|| defined(__AVR_ATmega32U6__) \ +|| defined(__AVR_ATmega48__) \ +|| defined(__AVR_ATmega48A__) \ +|| defined(__AVR_ATmega48PA__) \ +|| defined(__AVR_ATmega48PB__) \ +|| defined(__AVR_ATmega48P__) \ +|| defined(__AVR_ATmega640__) \ +|| defined(__AVR_ATmega649P__) \ +|| defined(__AVR_ATmega644__) \ +|| defined(__AVR_ATmega644A__) \ +|| defined(__AVR_ATmega644P__) \ +|| defined(__AVR_ATmega644PA__) \ +|| defined(__AVR_ATmega645__) \ +|| defined(__AVR_ATmega645A__) \ +|| defined(__AVR_ATmega645P__) \ +|| defined(__AVR_ATmega6450__) \ +|| defined(__AVR_ATmega6450A__) \ +|| defined(__AVR_ATmega6450P__) \ +|| defined(__AVR_ATmega649__) \ +|| defined(__AVR_ATmega649A__) \ +|| defined(__AVR_ATmega64M1__) \ +|| defined(__AVR_ATmega64C1__) \ +|| defined(__AVR_ATmega88A__) \ +|| defined(__AVR_ATmega88PA__) \ +|| defined(__AVR_ATmega88PB__) \ +|| defined(__AVR_ATmega6490__) \ +|| defined(__AVR_ATmega6490A__) \ +|| defined(__AVR_ATmega6490P__) \ +|| defined(__AVR_ATmega644RFR2__) \ +|| defined(__AVR_ATmega64RFR2__) \ +|| defined(__AVR_ATmega88__) \ +|| defined(__AVR_ATmega88P__) \ +|| defined(__AVR_ATmega8U2__) \ +|| defined(__AVR_ATmega16U2__) \ +|| defined(__AVR_ATmega32U2__) \ +|| defined(__AVR_ATtiny48__) \ +|| defined(__AVR_ATtiny88__) \ +|| defined(__AVR_ATtiny87__) \ +|| defined(__AVR_ATtiny167__) \ +|| defined(__DOXYGEN__) + + +/** \addtogroup avr_power + +Some of the newer AVRs contain a System Clock Prescale Register (CLKPR) that +allows you to decrease the system clock frequency and the power consumption +when the need for processing power is low. +On some earlier AVRs (ATmega103, ATmega64, ATmega128), similar +functionality can be achieved through the XTAL Divide Control Register. +Below are two macros and an enumerated type that can be used to +interface to the Clock Prescale Register or +XTAL Divide Control Register. + +\note Not all AVR devices have a clock prescaler. On those devices +without a Clock Prescale Register or XTAL Divide Control Register, these +macros are not available. +*/ + + +/** \addtogroup avr_power +\code +typedef enum +{ + clock_div_1 = 0, + clock_div_2 = 1, + clock_div_4 = 2, + clock_div_8 = 3, + clock_div_16 = 4, + clock_div_32 = 5, + clock_div_64 = 6, + clock_div_128 = 7, + clock_div_256 = 8, + clock_div_1_rc = 15, // ATmega128RFA1 only +} clock_div_t; +\endcode +Clock prescaler setting enumerations for device using +System Clock Prescale Register. + +\code +typedef enum +{ + clock_div_1 = 1, + clock_div_2 = 2, + clock_div_4 = 4, + clock_div_8 = 8, + clock_div_16 = 16, + clock_div_32 = 32, + clock_div_64 = 64, + clock_div_128 = 128 +} clock_div_t; +\endcode +Clock prescaler setting enumerations for device using +XTAL Divide Control Register. + +*/ +#ifndef __DOXYGEN__ +typedef enum +{ + clock_div_1 = 0, + clock_div_2 = 1, + clock_div_4 = 2, + clock_div_8 = 3, + clock_div_16 = 4, + clock_div_32 = 5, + clock_div_64 = 6, + clock_div_128 = 7, + clock_div_256 = 8 +#if defined(__AVR_ATmega128RFA1__) \ +|| defined(__AVR_ATmega2564RFR2__) \ +|| defined(__AVR_ATmega1284RFR2__) \ +|| defined(__AVR_ATmega644RFR2__) \ +|| defined(__AVR_ATmega256RFR2__) \ +|| defined(__AVR_ATmega128RFR2__) \ +|| defined(__AVR_ATmega64RFR2__) + , clock_div_1_rc = 15 +#endif +} clock_div_t; + +static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__)); +#endif /* !__DOXYGEN__ */ + +/** + \ingroup avr_power + \fn clock_prescale_set(clock_div_t x) + +Set the clock prescaler register select bits, selecting a system clock +division setting. This function is inlined, even if compiler +optimizations are disabled. + +The type of \c x is \c clock_div_t. + +\note For device with XTAL Divide Control Register (XDIV), \c x can actually range +from 1 to 129. Thus, one does not need to use \c clock_div_t type as argument. +*/ +void clock_prescale_set(clock_div_t __x) +{ + uint8_t __tmp = _BV(CLKPCE); + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "sts %1, %0" "\n\t" + "sts %1, %2" "\n\t" + "out __SREG__, __tmp_reg__" + : /* no outputs */ + : "d" (__tmp), + "M" (_SFR_MEM_ADDR(CLKPR)), + "d" (__x) + : "r0"); +} + +/** \addtogroup avr_power +\def clock_prescale_get() +Gets and returns the clock prescaler register setting. The return type is \c clock_div_t. + +\note For device with XTAL Divide Control Register (XDIV), return can actually +range from 1 to 129. Care should be taken has the return value could differ from the +typedef enum clock_div_t. This should only happen if clock_prescale_set was previously +called with a value other than those defined by \c clock_div_t. +*/ +#define clock_prescale_get() (clock_div_t)(CLKPR & (uint8_t)((1< 129)) + { + return;//Invalid value. + } + else + { + uint8_t __tmp = 0; + //Algo explained: + //1 - Clear XDIV in order for it to accept a new value (actually only + // XDIVEN need to be cleared, but clearing XDIV is faster than + // read-modify-write since we will rewrite XDIV later anyway) + //2 - wait 8 clock cycle for stability, see datasheet erreta + //3 - Exist if requested prescaller is 1 + //4 - Calculate XDIV6..0 value = 129 - __x + //5 - Set XDIVEN bit in calculated value + //6 - write XDIV with calculated value + //7 - wait 8 clock cycle for stability, see datasheet erreta + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "out %1, __zero_reg__" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "cpi %0, 0x01" "\n\t" + "breq L_%=" "\n\t" + "ldi %2, 0x81" "\n\t" //129 + "sub %2, %0" "\n\t" + "ori %2, 0x80" "\n\t" //128 + "out %1, %2" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "nop" "\n\t" + "L_%=: " "out __SREG__, __tmp_reg__" + : /* no outputs */ + :"d" (__x), + "I" (_SFR_IO_ADDR(XDIV)), + "d" (__tmp) + : "r0"); + } +} + +static __inline__ clock_div_t clock_prescale_get(void) __attribute__((__always_inline__)); + +clock_div_t clock_prescale_get(void) +{ + if(bit_is_clear(XDIV, XDIVEN)) + { + return 1; + } + else + { + return (clock_div_t)(129 - (XDIV & 0x7F)); + } +} + +#elif defined(__AVR_ATtiny4__) \ +|| defined(__AVR_ATtiny5__) \ +|| defined(__AVR_ATtiny9__) \ +|| defined(__AVR_ATtiny10__) \ +|| defined(__AVR_ATtiny20__) \ +|| defined(__AVR_ATtiny40__) \ + +typedef enum +{ + clock_div_1 = 0, + clock_div_2 = 1, + clock_div_4 = 2, + clock_div_8 = 3, + clock_div_16 = 4, + clock_div_32 = 5, + clock_div_64 = 6, + clock_div_128 = 7, + clock_div_256 = 8 +} clock_div_t; + +static __inline__ void clock_prescale_set(clock_div_t) __attribute__((__always_inline__)); + +void clock_prescale_set(clock_div_t __x) +{ + uint8_t __tmp = 0xD8; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "out %1, %0" "\n\t" + "out %2, %3" "\n\t" + "out __SREG__, __tmp_reg__" + : /* no outputs */ + : "d" (__tmp), + "I" (_SFR_IO_ADDR(CCP)), + "I" (_SFR_IO_ADDR(CLKPSR)), + "d" (__x) + : "r16"); +} + +#define clock_prescale_get() (clock_div_t)(CLKPSR & (uint8_t)((1< + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* avr/sfr_defs.h - macros for accessing AVR special function registers */ + +/* $Id$ */ + +#ifndef _AVR_SFR_DEFS_H_ +#define _AVR_SFR_DEFS_H_ 1 + +/** \defgroup avr_sfr_notes Additional notes from + \ingroup avr_sfr + + The \c file is included by all of the \c + files, which use macros defined here to make the special function register + definitions look like C variables or simple constants, depending on the + _SFR_ASM_COMPAT define. Some examples from \c to + show how to define such macros: + +\code +#define PORTA _SFR_IO8(0x02) +#define EEAR _SFR_IO16(0x21) +#define UDR0 _SFR_MEM8(0xC6) +#define TCNT3 _SFR_MEM16(0x94) +#define CANIDT _SFR_MEM32(0xF0) +\endcode + + If \c _SFR_ASM_COMPAT is not defined, C programs can use names like + PORTA directly in C expressions (also on the left side of + assignment operators) and GCC will do the right thing (use short I/O + instructions if possible). The \c __SFR_OFFSET definition is not used in + any way in this case. + + Define \c _SFR_ASM_COMPAT as 1 to make these names work as simple constants + (addresses of the I/O registers). This is necessary when included in + preprocessed assembler (*.S) source files, so it is done automatically if + \c __ASSEMBLER__ is defined. By default, all addresses are defined as if + they were memory addresses (used in \c lds/sts instructions). To use these + addresses in \c in/out instructions, you must subtract 0x20 from them. + + For more backwards compatibility, insert the following at the start of your + old assembler source file: + +\code +#define __SFR_OFFSET 0 +\endcode + + This automatically subtracts 0x20 from I/O space addresses, but it's a + hack, so it is recommended to change your source: wrap such addresses in + macros defined here, as shown below. After this is done, the + __SFR_OFFSET definition is no longer necessary and can be removed. + + Real example - this code could be used in a boot loader that is portable + between devices with \c SPMCR at different addresses. + +\verbatim +: #define SPMCR _SFR_IO8(0x37) +: #define SPMCR _SFR_MEM8(0x68) +\endverbatim + +\code +#if _SFR_IO_REG_P(SPMCR) + out _SFR_IO_ADDR(SPMCR), r24 +#else + sts _SFR_MEM_ADDR(SPMCR), r24 +#endif +\endcode + + You can use the \c in/out/cbi/sbi/sbic/sbis instructions, without the + _SFR_IO_REG_P test, if you know that the register is in the I/O + space (as with \c SREG, for example). If it isn't, the assembler will + complain (I/O address out of range 0...0x3f), so this should be fairly + safe. + + If you do not define \c __SFR_OFFSET (so it will be 0x20 by default), all + special register addresses are defined as memory addresses (so \c SREG is + 0x5f), and (if code size and speed are not important, and you don't like + the ugly \#if above) you can always use lds/sts to access them. But, this + will not work if __SFR_OFFSET != 0x20, so use a different macro + (defined only if __SFR_OFFSET == 0x20) for safety: + +\code + sts _SFR_ADDR(SPMCR), r24 +\endcode + + In C programs, all 3 combinations of \c _SFR_ASM_COMPAT and + __SFR_OFFSET are supported - the \c _SFR_ADDR(SPMCR) macro can be + used to get the address of the \c SPMCR register (0x57 or 0x68 depending on + device). */ + +#ifdef __ASSEMBLER__ +#define _SFR_ASM_COMPAT 1 +#elif !defined(_SFR_ASM_COMPAT) +#define _SFR_ASM_COMPAT 0 +#endif + +#ifndef __ASSEMBLER__ +/* These only work in C programs. */ +#include + +#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) +#define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr)) +#define _MMIO_DWORD(mem_addr) (*(volatile uint32_t *)(mem_addr)) +#endif + +#if _SFR_ASM_COMPAT + +#ifndef __SFR_OFFSET +/* Define as 0 before including this file for compatibility with old asm + sources that don't subtract __SFR_OFFSET from symbolic I/O addresses. */ +# if __AVR_ARCH__ >= 100 +# define __SFR_OFFSET 0x00 +# else +# define __SFR_OFFSET 0x20 +# endif +#endif + +#if (__SFR_OFFSET != 0) && (__SFR_OFFSET != 0x20) +#error "__SFR_OFFSET must be 0 or 0x20" +#endif + +#define _SFR_MEM8(mem_addr) (mem_addr) +#define _SFR_MEM16(mem_addr) (mem_addr) +#define _SFR_MEM32(mem_addr) (mem_addr) +#define _SFR_IO8(io_addr) ((io_addr) + __SFR_OFFSET) +#define _SFR_IO16(io_addr) ((io_addr) + __SFR_OFFSET) + +#define _SFR_IO_ADDR(sfr) ((sfr) - __SFR_OFFSET) +#define _SFR_MEM_ADDR(sfr) (sfr) +#define _SFR_IO_REG_P(sfr) ((sfr) < 0x40 + __SFR_OFFSET) + +#if (__SFR_OFFSET == 0x20) +/* No need to use ?: operator, so works in assembler too. */ +#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) +#elif !defined(__ASSEMBLER__) +#define _SFR_ADDR(sfr) (_SFR_IO_REG_P(sfr) ? (_SFR_IO_ADDR(sfr) + 0x20) : _SFR_MEM_ADDR(sfr)) +#endif + +#else /* !_SFR_ASM_COMPAT */ + +#ifndef __SFR_OFFSET +# if __AVR_ARCH__ >= 100 +# define __SFR_OFFSET 0x00 +# else +# define __SFR_OFFSET 0x20 +# endif +#endif + +#define _SFR_MEM8(mem_addr) _MMIO_BYTE(mem_addr) +#define _SFR_MEM16(mem_addr) _MMIO_WORD(mem_addr) +#define _SFR_MEM32(mem_addr) _MMIO_DWORD(mem_addr) +#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + __SFR_OFFSET) +#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + __SFR_OFFSET) + +#define _SFR_MEM_ADDR(sfr) ((uint16_t) &(sfr)) +#define _SFR_IO_ADDR(sfr) (_SFR_MEM_ADDR(sfr) - __SFR_OFFSET) +#define _SFR_IO_REG_P(sfr) (_SFR_MEM_ADDR(sfr) < 0x40 + __SFR_OFFSET) + +#define _SFR_ADDR(sfr) _SFR_MEM_ADDR(sfr) + +#endif /* !_SFR_ASM_COMPAT */ + +#define _SFR_BYTE(sfr) _MMIO_BYTE(_SFR_ADDR(sfr)) +#define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr)) +#define _SFR_DWORD(sfr) _MMIO_DWORD(_SFR_ADDR(sfr)) + +/** \name Bit manipulation */ + +/*@{*/ +/** \def _BV + \ingroup avr_sfr + + \code #include \endcode + + Converts a bit number into a byte value. + + \note The bit shift is performed by the compiler which then inserts the + result into the code. Thus, there is no run-time overhead when using + _BV(). */ + +#define _BV(bit) (1 << (bit)) + +/*@}*/ + +#ifndef _VECTOR +#define _VECTOR(N) __vector_ ## N +#endif + +#ifndef __ASSEMBLER__ + + +/** \name IO register bit manipulation */ + +/*@{*/ + + + +/** \def bit_is_set + \ingroup avr_sfr + + \code #include \endcode + + Test whether bit \c bit in IO register \c sfr is set. + This will return a 0 if the bit is clear, and non-zero + if the bit is set. */ + +#define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit)) + +/** \def bit_is_clear + \ingroup avr_sfr + + \code #include \endcode + + Test whether bit \c bit in IO register \c sfr is clear. + This will return non-zero if the bit is clear, and a 0 + if the bit is set. */ + +#define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit))) + +/** \def loop_until_bit_is_set + \ingroup avr_sfr + + \code #include \endcode + + Wait until bit \c bit in IO register \c sfr is set. */ + +#define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit)) + +/** \def loop_until_bit_is_clear + \ingroup avr_sfr + + \code #include \endcode + + Wait until bit \c bit in IO register \c sfr is clear. */ + +#define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit)) + +/*@}*/ + +#endif /* !__ASSEMBLER__ */ + +#endif /* _SFR_DEFS_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/signal.h b/hardware/tools/avr/avr/include/avr/signal.h new file mode 100644 index 0000000000000000000000000000000000000000..8f83399b04172799c41525e0726a5991bfba14a7 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/signal.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2002,2005,2006 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_SIGNAL_H_ +#define _AVR_SIGNAL_H_ + +#warning "This header file is obsolete. Use ." +#include + +#endif /* _AVR_SIGNAL_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/signature.h b/hardware/tools/avr/avr/include/avr/signature.h new file mode 100644 index 0000000000000000000000000000000000000000..40fea7b8d734da3f0deeb4e854debb00656c2435 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/signature.h @@ -0,0 +1,85 @@ +/* Copyright (c) 2009, Atmel Corporation + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* avr/signature.h - Signature API */ + +#ifndef _AVR_SIGNATURE_H_ +#define _AVR_SIGNATURE_H_ 1 + +/** \file */ +/** \defgroup avr_signature : Signature Support + + \par Introduction + + The header file allows the user to automatically + and easily include the device's signature data in a special section of + the final linked ELF file. + + This value can then be used by programming software to compare the on-device + signature with the signature recorded in the ELF file to look for a match + before programming the device. + + \par API Usage Example + + Usage is very simple; just include the header file: + + \code + #include + \endcode + + This will declare a constant unsigned char array and it is initialized with + the three signature bytes, MSB first, that are defined in the device I/O + header file. This array is then placed in the .signature section in the + resulting linked ELF file. + + The three signature bytes that are used to initialize the array are + these defined macros in the device I/O header file, from MSB to LSB: + SIGNATURE_2, SIGNATURE_1, SIGNATURE_0. + + This header file should only be included once in an application. +*/ + +#ifndef __ASSEMBLER__ + +#include + +#if defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) + +const unsigned char __signature[3] +__attribute__((__used__, __section__(".signature"))) = + { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 }; + +#endif /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */ + +#endif /* __ASSEMBLER__ */ + +#endif /* _AVR_SIGNATURE_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/sleep.h b/hardware/tools/avr/avr/include/avr/sleep.h new file mode 100644 index 0000000000000000000000000000000000000000..fa0d8f077352184dad13459c5dfed14e49d16823 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/sleep.h @@ -0,0 +1,357 @@ +/* Copyright (c) 2002, 2004 Theodore A. Roth + Copyright (c) 2004, 2007, 2008 Eric B. Weddington + Copyright (c) 2005, 2006, 2007 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _AVR_SLEEP_H_ +#define _AVR_SLEEP_H_ 1 + +#include +#include + + +/** \file */ + +/** \defgroup avr_sleep : Power Management and Sleep Modes + + \code #include \endcode + + Use of the \c SLEEP instruction can allow an application to reduce its + power comsumption considerably. AVR devices can be put into different + sleep modes. Refer to the datasheet for the details relating to the device + you are using. + + There are several macros provided in this header file to actually + put the device into sleep mode. The simplest way is to optionally + set the desired sleep mode using \c set_sleep_mode() (it usually + defaults to idle mode where the CPU is put on sleep but all + peripheral clocks are still running), and then call + \c sleep_mode(). This macro automatically sets the sleep enable bit, goes + to sleep, and clears the sleep enable bit. + + Example: + \code + #include + + ... + set_sleep_mode(); + sleep_mode(); + \endcode + + Note that unless your purpose is to completely lock the CPU (until a + hardware reset), interrupts need to be enabled before going to sleep. + + As the \c sleep_mode() macro might cause race conditions in some + situations, the individual steps of manipulating the sleep enable + (SE) bit, and actually issuing the \c SLEEP instruction, are provided + in the macros \c sleep_enable(), \c sleep_disable(), and + \c sleep_cpu(). This also allows for test-and-sleep scenarios that + take care of not missing the interrupt that will awake the device + from sleep. + + Example: + \code + #include + #include + + ... + set_sleep_mode(); + cli(); + if (some_condition) + { + sleep_enable(); + sei(); + sleep_cpu(); + sleep_disable(); + } + sei(); + \endcode + + This sequence ensures an atomic test of \c some_condition with + interrupts being disabled. If the condition is met, sleep mode + will be prepared, and the \c SLEEP instruction will be scheduled + immediately after an \c SEI instruction. As the intruction right + after the \c SEI is guaranteed to be executed before an interrupt + could trigger, it is sure the device will really be put to sleep. + + Some devices have the ability to disable the Brown Out Detector (BOD) before + going to sleep. This will also reduce power while sleeping. If the + specific AVR device has this ability then an additional macro is defined: + \c sleep_bod_disable(). This macro generates inlined assembly code + that will correctly implement the timed sequence for disabling the BOD + before sleeping. However, there is a limited number of cycles after the + BOD has been disabled that the device can be put into sleep mode, otherwise + the BOD will not truly be disabled. Recommended practice is to disable + the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then + put the device to sleep (\c sleep_cpu()), like so: + + \code + #include + #include + + ... + set_sleep_mode(); + cli(); + if (some_condition) + { + sleep_enable(); + sleep_bod_disable(); + sei(); + sleep_cpu(); + sleep_disable(); + } + sei(); + \endcode +*/ + + +/* Define an internal sleep control register and an internal sleep enable bit mask. */ +#if defined(SLEEP_CTRL) + + /* XMEGA devices */ + #define _SLEEP_CONTROL_REG SLEEP_CTRL + #define _SLEEP_ENABLE_MASK SLEEP_SEN_bm + #define _SLEEP_SMODE_GROUP_MASK SLEEP_SMODE_gm + +#elif defined(SLPCTRL) + + /* New xmega devices */ + #define _SLEEP_CONTROL_REG SLPCTRL_CTRLA + #define _SLEEP_ENABLE_MASK SLPCTRL_SEN_bm + #define _SLEEP_SMODE_GROUP_MASK SLPCTRL_SMODE_gm + +#elif defined(SMCR) + + #define _SLEEP_CONTROL_REG SMCR + #define _SLEEP_ENABLE_MASK _BV(SE) + +#elif defined(__AVR_AT94K__) + + #define _SLEEP_CONTROL_REG MCUR + #define _SLEEP_ENABLE_MASK _BV(SE) + +#elif !defined(__DOXYGEN__) + + #define _SLEEP_CONTROL_REG MCUCR + #define _SLEEP_ENABLE_MASK _BV(SE) + +#endif + + +/* Special casing these three devices - they are the + only ones that need to write to more than one register. */ +#if defined(__AVR_ATmega161__) + + #define set_sleep_mode(mode) \ + do { \ + MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \ + EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \ + } while(0) + + +#elif defined(__AVR_ATmega162__) \ +|| defined(__AVR_ATmega8515__) + + #define set_sleep_mode(mode) \ + do { \ + MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \ + MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \ + EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \ + } while(0) + +/* For xmegas, check presence of SLEEP_SMODE_bm and define set_sleep_mode accordingly. */ +#elif defined(__AVR_XMEGA__) + +#define set_sleep_mode(mode) \ + do { \ + _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_SLEEP_SMODE_GROUP_MASK)) | (mode)); \ + } while(0) + +/* For everything else, check for presence of SM and define set_sleep_mode accordingly. */ +#else +#if defined(SM2) + + #define set_sleep_mode(mode) \ + do { \ + _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \ + } while(0) + +#elif defined(SM1) + + #define set_sleep_mode(mode) \ + do { \ + _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \ + } while(0) + +#elif defined(SM) + + #define set_sleep_mode(mode) \ + do { \ + _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~_BV(SM)) | (mode)); \ + } while(0) + +#else + + #error "No SLEEP mode defined for this device." + +#endif /* if defined(SM2) */ +#endif /* #if defined(__AVR_ATmega161__) */ + + + +/** \ingroup avr_sleep + + Put the device in sleep mode. How the device is brought out of sleep mode + depends on the specific mode selected with the set_sleep_mode() function. + See the data sheet for your device for more details. */ + + +#if defined(__DOXYGEN__) + +/** \ingroup avr_sleep + + Set the SE (sleep enable) bit. +*/ +extern void sleep_enable (void); + +#else + +#define sleep_enable() \ +do { \ + _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK; \ +} while(0) + +#endif + + +#if defined(__DOXYGEN__) + +/** \ingroup avr_sleep + + Clear the SE (sleep enable) bit. +*/ +extern void sleep_disable (void); + +#else + +#define sleep_disable() \ +do { \ + _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK); \ +} while(0) + +#endif + + +/** \ingroup avr_sleep + + Put the device into sleep mode. The SE bit must be set + beforehand, and it is recommended to clear it afterwards. +*/ +#if defined(__DOXYGEN__) + +extern void sleep_cpu (void); + +#else + +#define sleep_cpu() \ +do { \ + __asm__ __volatile__ ( "sleep" "\n\t" :: ); \ +} while(0) + +#endif + + +#if defined(__DOXYGEN__) + +/** \ingroup avr_sleep + + Put the device into sleep mode, taking care of setting + the SE bit before, and clearing it afterwards. */ +extern void sleep_mode (void); + +#else + +#define sleep_mode() \ +do { \ + sleep_enable(); \ + sleep_cpu(); \ + sleep_disable(); \ +} while (0) + +#endif + + +#if defined(__DOXYGEN__) + +/** \ingroup avr_sleep + + Disable BOD before going to sleep. + Not available on all devices. +*/ +extern void sleep_bod_disable (void); + +#else + +#if defined(BODS) && defined(BODSE) + +#ifdef BODCR + +#define BOD_CONTROL_REG BODCR + +#else + +#define BOD_CONTROL_REG MCUCR + +#endif + +#define sleep_bod_disable() \ +do { \ + uint8_t tempreg; \ + __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \ + "ori %[tempreg], %[bods_bodse]" "\n\t" \ + "out %[mcucr], %[tempreg]" "\n\t" \ + "andi %[tempreg], %[not_bodse]" "\n\t" \ + "out %[mcucr], %[tempreg]" \ + : [tempreg] "=&d" (tempreg) \ + : [mcucr] "I" _SFR_IO_ADDR(BOD_CONTROL_REG), \ + [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \ + [not_bodse] "i" (~_BV(BODSE))); \ +} while (0) + +#endif + +#endif + + +/*@}*/ + +#endif /* _AVR_SLEEP_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/version.h b/hardware/tools/avr/avr/include/avr/version.h new file mode 100644 index 0000000000000000000000000000000000000000..2deaf8617e3477f50cabdbb89adfed822020f5a8 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/version.h @@ -0,0 +1,90 @@ +/* Copyright (c) 2005, Joerg Wunsch -*- c -*- + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/** \defgroup avr_version : avr-libc version macros + \code #include \endcode + + This header file defines macros that contain version numbers and + strings describing the current version of avr-libc. + + The version number itself basically consists of three pieces that + are separated by a dot: the major number, the minor number, and + the revision number. For development versions (which use an odd + minor number), the string representation additionally gets the + date code (YYYYMMDD) appended. + + This file will also be included by \c . That way, + portable tests can be implemented using \c that can be + used in code that wants to remain backwards-compatible to library + versions prior to the date when the library version API had been + added, as referenced but undefined C preprocessor macros + automatically evaluate to 0. +*/ + +#ifndef _AVR_VERSION_H_ +#define _AVR_VERSION_H_ + +/** \ingroup avr_version + String literal representation of the current library version. */ +#define __AVR_LIBC_VERSION_STRING__ "2.0.0" + +/** \ingroup avr_version + Numerical representation of the current library version. + + In the numerical representation, the major number is multiplied by + 10000, the minor number by 100, and all three parts are then + added. It is intented to provide a monotonically increasing + numerical value that can easily be used in numerical checks. + */ +#define __AVR_LIBC_VERSION__ 20000UL + +/** \ingroup avr_version + String literal representation of the release date. */ +#define __AVR_LIBC_DATE_STRING__ "20150208" + +/** \ingroup avr_version + Numerical representation of the release date. */ +#define __AVR_LIBC_DATE_ 20150208UL + +/** \ingroup avr_version + Library major version number. */ +#define __AVR_LIBC_MAJOR__ 2 + +/** \ingroup avr_version + Library minor version number. */ +#define __AVR_LIBC_MINOR__ 0 + +/** \ingroup avr_version + Library revision number. */ +#define __AVR_LIBC_REVISION__ 0 + +#endif /* _AVR_VERSION_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/wdt.h b/hardware/tools/avr/avr/include/avr/wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..2b4a02e1d2ebdf02a218f3bdcf800d44c3745a94 --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/wdt.h @@ -0,0 +1,645 @@ +/* Copyright (c) 2002, 2004 Marek Michalkiewicz + Copyright (c) 2005, 2006, 2007 Eric B. Weddington + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + avr/wdt.h - macros for AVR watchdog timer + */ + +#ifndef _AVR_WDT_H_ +#define _AVR_WDT_H_ + +#include +#include + +/** \file */ +/** \defgroup avr_watchdog : Watchdog timer handling + \code #include \endcode + + This header file declares the interface to some inline macros + handling the watchdog timer present in many AVR devices. In order + to prevent the watchdog timer configuration from being + accidentally altered by a crashing application, a special timed + sequence is required in order to change it. The macros within + this header file handle the required sequence automatically + before changing any value. Interrupts will be disabled during + the manipulation. + + \note Depending on the fuse configuration of the particular + device, further restrictions might apply, in particular it might + be disallowed to turn off the watchdog timer. + + Note that for newer devices (ATmega88 and newer, effectively any + AVR that has the option to also generate interrupts), the watchdog + timer remains active even after a system reset (except a power-on + condition), using the fastest prescaler value (approximately 15 + ms). It is therefore required to turn off the watchdog early + during program startup, the datasheet recommends a sequence like + the following: + + \code + #include + #include + + uint8_t mcusr_mirror __attribute__ ((section (".noinit"))); + + void get_mcusr(void) \ + __attribute__((naked)) \ + __attribute__((section(".init3"))); + void get_mcusr(void) + { + mcusr_mirror = MCUSR; + MCUSR = 0; + wdt_disable(); + } + \endcode + + Saving the value of MCUSR in \c mcusr_mirror is only needed if the + application later wants to examine the reset source, but in particular, + clearing the watchdog reset flag before disabling the + watchdog is required, according to the datasheet. +*/ + +/** + \ingroup avr_watchdog + Reset the watchdog timer. When the watchdog timer is enabled, + a call to this instruction is required before the timer expires, + otherwise a watchdog-initiated device reset will occur. +*/ + +#define wdt_reset() __asm__ __volatile__ ("wdr") + +#ifndef __DOXYGEN__ + +#if defined(WDP3) +# define _WD_PS3_MASK _BV(WDP3) +#else +# define _WD_PS3_MASK 0x00 +#endif + +#if defined(WDTCSR) +# define _WD_CONTROL_REG WDTCSR +#elif defined(WDTCR) +# define _WD_CONTROL_REG WDTCR +#else +# define _WD_CONTROL_REG WDT +#endif + +#if defined(WDTOE) +#define _WD_CHANGE_BIT WDTOE +#else +#define _WD_CHANGE_BIT WDCE +#endif + +#endif /* !__DOXYGEN__ */ + + +/** + \ingroup avr_watchdog + Enable the watchdog timer, configuring it for expiry after + \c timeout (which is a combination of the \c WDP0 through + \c WDP2 bits to write into the \c WDTCR register; For those devices + that have a \c WDTCSR register, it uses the combination of the \c WDP0 + through \c WDP3 bits). + + See also the symbolic constants \c WDTO_15MS et al. +*/ + + +#if defined(__AVR_XMEGA__) + +#if defined (WDT_CTRLA) && !defined(RAMPD) + +#define wdt_enable(timeout) \ +do { \ +uint8_t temp; \ +__asm__ __volatile__ ( \ + "wdr" "\n\t" \ + "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ + "lds %[tmp], %[wdt_reg]" "\n\t" \ + "sbr %[tmp], %[wdt_enable_timeout]" "\n\t" \ + "sts %[wdt_reg], %[tmp]" "\n\t" \ + "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ + "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ + "rjmp 1b" "\n\t" \ + : [tmp] "=r" (temp) \ + : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ + [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ + [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)), \ + [wdt_enable_timeout] "M" (timeout), \ + [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ + [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ +); \ +} while(0) + +#define wdt_disable() \ +do { \ +uint8_t temp; \ +__asm__ __volatile__ ( \ + "wdr" "\n\t" \ + "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ + "lds %[tmp], %[wdt_reg]" "\n\t" \ + "cbr %[tmp], %[timeout_mask]" "\n\t" \ + "sts %[wdt_reg], %[tmp]" "\n\t" \ + : [tmp] "=r" (temp) \ + : [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ + [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ + [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRLA)),\ + [timeout_mask] "I" (WDT_PERIOD_gm) \ +); \ +} while(0) + +#else // defined (WDT_CTRLA) && !defined(RAMPD) + +/* + wdt_enable(timeout) for xmega devices +** write signature (CCP_IOREG_gc) that enables change of protected I/O + registers to the CCP register +** At the same time, + 1) set WDT change enable (WDT_CEN_bm) + 2) enable WDT (WDT_ENABLE_bm) + 3) set timeout (timeout) +** Synchronization starts when ENABLE bit of WDT is set. So, wait till it + finishes (SYNCBUSY of STATUS register is automatically cleared after the + sync is finished). +*/ +#define wdt_enable(timeout) \ +do { \ +uint8_t temp; \ +__asm__ __volatile__ ( \ + "in __tmp_reg__, %[rampd]" "\n\t" \ + "out %[rampd], __zero_reg__" "\n\t" \ + "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ + "sts %[wdt_reg], %[wdt_enable_timeout]" "\n\t" \ + "1:lds %[tmp], %[wdt_status_reg]" "\n\t" \ + "sbrc %[tmp], %[wdt_syncbusy_bit]" "\n\t" \ + "rjmp 1b" "\n\t" \ + "out %[rampd], __tmp_reg__" "\n\t" \ + : [tmp] "=r" (temp) \ + : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ + [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ + [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ + [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ + [wdt_enable_timeout] "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | timeout)), \ + [wdt_status_reg] "n" (_SFR_MEM_ADDR(WDT_STATUS)), \ + [wdt_syncbusy_bit] "I" (WDT_SYNCBUSY_bm) \ + : "r0" \ +); \ +} while(0) + +#define wdt_disable() \ +__asm__ __volatile__ ( \ + "in __tmp_reg__, %[rampd]" "\n\t" \ + "out %[rampd], __zero_reg__" "\n\t" \ + "out %[ccp_reg], %[ioreg_cen_mask]" "\n\t" \ + "sts %[wdt_reg], %[disable_mask]" "\n\t" \ + "out %[rampd], __tmp_reg__" "\n\t" \ + : \ + : [rampd] "I" (_SFR_IO_ADDR(RAMPD)), \ + [ccp_reg] "I" (_SFR_IO_ADDR(CCP)), \ + [ioreg_cen_mask] "r" ((uint8_t)CCP_IOREG_gc), \ + [wdt_reg] "n" (_SFR_MEM_ADDR(WDT_CTRL)), \ + [disable_mask] "r" ((uint8_t)((~WDT_ENABLE_bm) | WDT_CEN_bm)) \ + : "r0" \ +); + +#endif // defined (WDT_CTRLA) && !defined(RAMPD) + +#elif defined(__AVR_TINY__) + +#define wdt_enable(value) \ +__asm__ __volatile__ ( \ + "in __tmp_reg__,__SREG__" "\n\t" \ + "cli" "\n\t" \ + "wdr" "\n\t" \ + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ + "out %[WDTREG],%[WDVALUE]" "\n\t" \ + "out __SREG__,__tmp_reg__" "\n\t" \ + : /* no outputs */ \ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ + [SIGNATURE] "r" ((uint8_t)0xD8), \ + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ + [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) \ + | _BV(WDE) | (value & 0x07) )) \ + : "r16" \ +) + +#define wdt_disable() \ +do { \ +uint8_t temp_wd; \ +__asm__ __volatile__ ( \ + "in __tmp_reg__,__SREG__" "\n\t" \ + "cli" "\n\t" \ + "wdr" "\n\t" \ + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" \ + "in %[TEMP_WD],%[WDTREG]" "\n\t" \ + "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" \ + "out %[WDTREG],%[TEMP_WD]" "\n\t" \ + "out __SREG__,__tmp_reg__" "\n\t" \ + : /*no output */ \ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), \ + [SIGNATURE] "r" ((uint8_t)0xD8), \ + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ + [TEMP_WD] "d" (temp_wd), \ + [WDVALUE] "n" (1 << WDE) \ + : "r16" \ +); \ +}while(0) + +#elif defined(CCP) + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_enable (const uint8_t value) +{ + if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "sts %[WDTREG],%[WDVALUE]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /* no outputs */ + : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) + | _BV(WDE) | (value & 0x07) )) + : "r0" + ); + } + else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "out %[WDTREG],%[WDVALUE]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /* no outputs */ + : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) + | _BV(WDE) | (value & 0x07) )) + : "r0" + ); + } + else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "sts %[WDTREG],%[WDVALUE]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /* no outputs */ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) + | _BV(WDE) | (value & 0x07) )) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "out %[WDTREG],%[WDVALUE]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /* no outputs */ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + [WDVALUE] "r" ((uint8_t)((value & 0x08 ? _WD_PS3_MASK : 0x00) + | _BV(WDE) | (value & 0x07) )) + : "r0" + ); + } +} + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_disable (void) +{ + if (!_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) + { + uint8_t temp_wd; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "lds %[TEMP_WD],%[WDTREG]" "\n\t" + "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" + "sts %[WDTREG],%[TEMP_WD]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /*no output */ + : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + [TEMP_WD] "d" (temp_wd), + [WDVALUE] "n" (1 << WDE) + : "r0" + ); + } + else if (!_SFR_IO_REG_P (CCP) && _SFR_IO_REG_P(_WD_CONTROL_REG)) + { + uint8_t temp_wd; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "in %[TEMP_WD],%[WDTREG]" "\n\t" + "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" + "out %[WDTREG],%[TEMP_WD]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /*no output */ + : [CCPADDRESS] "n" (_SFR_MEM_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + [TEMP_WD] "d" (temp_wd), + [WDVALUE] "n" (1 << WDE) + : "r0" + ); + } + else if (_SFR_IO_REG_P (CCP) && !_SFR_IO_REG_P(_WD_CONTROL_REG)) + { + uint8_t temp_wd; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "lds %[TEMP_WD],%[WDTREG]" "\n\t" + "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" + "sts %[WDTREG],%[TEMP_WD]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /*no output */ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + [TEMP_WD] "d" (temp_wd), + [WDVALUE] "n" (1 << WDE) + : "r0" + ); + } + else + { + uint8_t temp_wd; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %[CCPADDRESS],%[SIGNATURE]" "\n\t" + "in %[TEMP_WD],%[WDTREG]" "\n\t" + "cbr %[TEMP_WD],%[WDVALUE]" "\n\t" + "out %[WDTREG],%[TEMP_WD]" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : /*no output */ + : [CCPADDRESS] "I" (_SFR_IO_ADDR(CCP)), + [SIGNATURE] "r" ((uint8_t)0xD8), + [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + [TEMP_WD] "d" (temp_wd), + [WDVALUE] "n" (1 << WDE) + : "r0" + ); + } +} + +#else + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_enable (const uint8_t value) +{ + if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "out %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "out %0, %2" "\n \t" + : /* no outputs */ + : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDE) | (value & 0x07)) ) + : "r0" + ); + } + else + { + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "sts %0, %1" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + "sts %0, %2" "\n \t" + : /* no outputs */ + : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))), + "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | + _BV(WDE) | (value & 0x07)) ) + : "r0" + ); + } +} + +static __inline__ +__attribute__ ((__always_inline__)) +void wdt_disable (void) +{ + if (_SFR_IO_REG_P (_WD_CONTROL_REG)) + { + uint8_t register temp_reg; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "in %[TEMPREG],%[WDTREG]" "\n\t" + "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" + "out %[WDTREG],%[TEMPREG]" "\n\t" + "out %[WDTREG],__zero_reg__" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : [TEMPREG] "=d" (temp_reg) + : [WDTREG] "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), + [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) + : "r0" + ); + } + else + { + uint8_t register temp_reg; + __asm__ __volatile__ ( + "in __tmp_reg__,__SREG__" "\n\t" + "cli" "\n\t" + "wdr" "\n\t" + "lds %[TEMPREG],%[WDTREG]" "\n\t" + "ori %[TEMPREG],%[WDCE_WDE]" "\n\t" + "sts %[WDTREG],%[TEMPREG]" "\n\t" + "sts %[WDTREG],__zero_reg__" "\n\t" + "out __SREG__,__tmp_reg__" "\n\t" + : [TEMPREG] "=d" (temp_reg) + : [WDTREG] "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), + [WDCE_WDE] "n" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) + : "r0" + ); + } +} + +#endif + + +/** + \ingroup avr_watchdog + Symbolic constants for the watchdog timeout. Since the watchdog + timer is based on a free-running RC oscillator, the times are + approximate only and apply to a supply voltage of 5 V. At lower + supply voltages, the times will increase. For older devices, the + times will be as large as three times when operating at Vcc = 3 V, + while the newer devices (e. g. ATmega128, ATmega8) only experience + a negligible change. + + Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, + 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) + Symbolic constants are formed by the prefix + \c WDTO_, followed by the time. + + Example that would select a watchdog timer expiry of approximately + 500 ms: + \code + wdt_enable(WDTO_500MS); + \endcode +*/ +#define WDTO_15MS 0 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_30MS 1 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_60MS 2 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_120MS 3 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_250MS 4 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_500MS 5 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_1S 6 + +/** \ingroup avr_watchdog + See \c WDTO_15MS */ +#define WDTO_2S 7 + +#if defined(__DOXYGEN__) || defined(WDP3) + +/** \ingroup avr_watchdog + See \c WDTO_15MS + Note: This is only available on the + ATtiny2313, + ATtiny24, ATtiny44, ATtiny84, ATtiny84A, + ATtiny25, ATtiny45, ATtiny85, + ATtiny261, ATtiny461, ATtiny861, + ATmega48, ATmega88, ATmega168, + ATmega48P, ATmega88P, ATmega168P, ATmega328P, + ATmega164P, ATmega324P, ATmega644P, ATmega644, + ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, + ATmega8HVA, ATmega16HVA, ATmega32HVB, + ATmega406, ATmega1284P, + AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, + AT90PWM81, AT90PWM161, + AT90USB82, AT90USB162, + AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, + ATtiny48, ATtiny88. + + Note: This value does not match the bit pattern of the + respective control register. It is solely meant to be used together + with wdt_enable(). + */ +#define WDTO_4S 8 + +/** \ingroup avr_watchdog + See \c WDTO_15MS + Note: This is only available on the + ATtiny2313, + ATtiny24, ATtiny44, ATtiny84, ATtiny84A, + ATtiny25, ATtiny45, ATtiny85, + ATtiny261, ATtiny461, ATtiny861, + ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168, + ATmega48P, ATmega88P, ATmega168P, ATmega328P, + ATmega164P, ATmega324P, ATmega644P, ATmega644, + ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, + ATmega8HVA, ATmega16HVA, ATmega32HVB, + ATmega406, ATmega1284P, + ATmega2564RFR2, ATmega256RFR2, ATmega1284RFR2, ATmega128RFR2, ATmega644RFR2, ATmega64RFR2 + AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, + AT90PWM81, AT90PWM161, + AT90USB82, AT90USB162, + AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, + ATtiny48, ATtiny88, + ATxmega16a4u, ATxmega32a4u, + ATxmega16c4, ATxmega32c4, + ATxmega128c3, ATxmega192c3, ATxmega256c3. + + Note: This value does not match the bit pattern of the + respective control register. It is solely meant to be used together + with wdt_enable(). + */ +#define WDTO_8S 9 + +#endif /* defined(__DOXYGEN__) || defined(WDP3) */ + + +#endif /* _AVR_WDT_H_ */ diff --git a/hardware/tools/avr/avr/include/avr/xmega.h b/hardware/tools/avr/avr/include/avr/xmega.h new file mode 100644 index 0000000000000000000000000000000000000000..54375abbb5c2d36250d4c282ed018b86fb701cea --- /dev/null +++ b/hardware/tools/avr/avr/include/avr/xmega.h @@ -0,0 +1,100 @@ +/* Copyright (c) 2012 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + * This file is included by whenever compiling for an Xmega + * device. It abstracts certain features common to the Xmega device + * families. + */ + +#ifndef _AVR_XMEGA_H +#define _AVR_XMEGA_H + +#ifdef __DOXYGEN__ +/** + \def _PROTECTED_WRITE + \ingroup avr_io + + Write value \c value to IO register \c reg that is protected through + the Xmega configuration change protection (CCP) mechanism. This + implements the timed sequence that is required for CCP. + + Example to modify the CPU clock: + \code + #include + + _PROTECTED_WRITE(CLK_PSCTRL, CLK_PSADIV0_bm); + _PROTECTED_WRITE(CLK_CTRL, CLK_SCLKSEL0_bm); + \endcode + */ +#define _PROTECTED_WRITE(reg, value) + +/** + \def _PROTECTED_WRITE_SPM + \ingroup avr_io + + Write value \c value to register \c reg that is protected through + the Xmega configuration change protection (CCP) key for self + programming (SPM). This implements the timed sequence that is + required for CCP. + + Example to modify the CPU clock: + \code + #include + + _PROTECTED_WRITE_SPM(NVMCTRL_CTRLA, NVMCTRL_CMD_PAGEERASEWRITE_gc); + \endcode + */ +#define _PROTECTED_WRITE_SPM(reg, value) + +#else /* !__DOXYGEN__ */ + +#define _PROTECTED_WRITE(reg, value) \ + __asm__ __volatile__("out %[ccp], %[ccp_ioreg]" "\n\t" \ + "sts %[ioreg], %[val]" \ + : \ + : [ccp] "I" (_SFR_IO_ADDR(CCP)), \ + [ccp_ioreg] "d" ((uint8_t)CCP_IOREG_gc), \ + [ioreg] "n" (_SFR_MEM_ADDR(reg)), \ + [val] "r" ((uint8_t)value)) + +#define _PROTECTED_WRITE_SPM(reg, value) \ + __asm__ __volatile__("out %[ccp], %[ccp_spm_mask]" "\n\t" \ + "sts %[ioreg], %[val]" \ + : \ + : [ccp] "I" (_SFR_IO_ADDR(CCP)), \ + [ccp_spm_mask] "d" ((uint8_t)CCP_SPM_gc), \ + [ioreg] "n" (_SFR_MEM_ADDR(reg)), \ + [val] "r" ((uint8_t)value)) +#endif /* DOXYGEN */ + +#endif /* _AVR_XMEGA_H */ diff --git a/hardware/tools/avr/avr/include/compat/deprecated.h b/hardware/tools/avr/avr/include/compat/deprecated.h new file mode 100644 index 0000000000000000000000000000000000000000..a43fe0633a355c95e3adfbfdef16b3cd872d3409 --- /dev/null +++ b/hardware/tools/avr/avr/include/compat/deprecated.h @@ -0,0 +1,226 @@ +/* Copyright (c) 2005,2006 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _COMPAT_DEPRECATED_H_ +#define _COMPAT_DEPRECATED_H_ + +/** \defgroup deprecated_items : Deprecated items + + This header file contains several items that used to be available + in previous versions of this library, but have eventually been + deprecated over time. + + \code #include \endcode + + These items are supplied within that header file for backward + compatibility reasons only, so old source code that has been + written for previous library versions could easily be maintained + until its end-of-life. Use of any of these items in new code is + strongly discouraged. + */ + +/** \name Allowing specific system-wide interrupts + + In addition to globally enabling interrupts, each device's particular + interrupt needs to be enabled separately if interrupts for this device are + desired. While some devices maintain their interrupt enable bit inside + the device's register set, external and timer interrupts have system-wide + configuration registers. + + Example: + + \code + // Enable timer 1 overflow interrupts. + timer_enable_int(_BV(TOIE1)); + + // Do some work... + + // Disable all timer interrupts. + timer_enable_int(0); + \endcode + + \note Be careful when you use these functions. If you already have a + different interrupt enabled, you could inadvertantly disable it by + enabling another intterupt. */ + +/*@{*/ + +/** \ingroup deprecated_items + \def enable_external_int(mask) + \deprecated + + This macro gives access to the \c GIMSK register (or \c EIMSK register + if using an AVR Mega device or \c GICR register for others). Although this + macro is essentially the same as assigning to the register, it does + adapt slightly to the type of device being used. This macro is + unavailable if none of the registers listed above are defined. */ + +/* Define common register definition if available. */ +#if defined(EIMSK) +# define __EICR EIMSK +#elif defined(GIMSK) +# define __EICR GIMSK +#elif defined(GICR) +# define __EICR GICR +#endif + +/* If common register defined, define macro. */ +#if defined(__EICR) || defined(__DOXYGEN__) +#define enable_external_int(mask) (__EICR = mask) +#endif + +/** \ingroup deprecated_items + \deprecated + + This function modifies the \c timsk register. + The value you pass via \c ints is device specific. */ + +static __inline__ void timer_enable_int (unsigned char ints) +{ +#ifdef TIMSK + TIMSK = ints; +#endif +} + +/** \def INTERRUPT(signame) + \ingroup deprecated_items + \deprecated + + Introduces an interrupt handler function that runs with global interrupts + initially enabled. This allows interrupt handlers to be interrupted. + + As this macro has been used by too many unsuspecting people in the + past, it has been deprecated, and will be removed in a future + version of the library. Users who want to legitimately re-enable + interrupts in their interrupt handlers as quickly as possible are + encouraged to explicitly declare their handlers as described + \ref attr_interrupt "above". +*/ + +#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4) +# define __INTR_ATTRS used, externally_visible +#else /* GCC < 4.1 */ +# define __INTR_ATTRS used +#endif + +#ifdef __cplusplus +#define INTERRUPT(signame) \ +extern "C" void signame(void); \ +void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ +void signame (void) +#else +#define INTERRUPT(signame) \ +void signame (void) __attribute__ ((interrupt,__INTR_ATTRS)); \ +void signame (void) +#endif + +/*@}*/ + +/** + \name Obsolete IO macros + + Back in a time when AVR-GCC and avr-libc could not handle IO port + access in the direct assignment form as they are handled now, all + IO port access had to be done through specific macros that + eventually resulted in inline assembly instructions performing the + desired action. + + These macros became obsolete, as reading and writing IO ports can + be done by simply using the IO port name in an expression, and all + bit manipulation (including those on IO ports) can be done using + generic C bit manipulation operators. + + The macros in this group simulate the historical behaviour. While + they are supposed to be applied to IO ports, the emulation actually + uses standard C methods, so they could be applied to arbitrary + memory locations as well. +*/ + +/*@{*/ + +/** + \ingroup deprecated_items + \def inp(port) + \deprecated + + Read a value from an IO port \c port. +*/ +#define inp(port) (port) + +/** + \ingroup deprecated_items + \def outp(val, port) + \deprecated + + Write \c val to IO port \c port. +*/ +#define outp(val, port) (port) = (val) + +/** + \ingroup deprecated_items + \def inb(port) + \deprecated + + Read a value from an IO port \c port. +*/ +#define inb(port) (port) + +/** + \ingroup deprecated_items + \def outb(port, val) + \deprecated + + Write \c val to IO port \c port. +*/ +#define outb(port, val) (port) = (val) + +/** + \ingroup deprecated_items + \def sbi(port, bit) + \deprecated + + Set \c bit in IO port \c port. +*/ +#define sbi(port, bit) (port) |= (1 << (bit)) + +/** + \ingroup deprecated_items + \def cbi(port, bit) + \deprecated + + Clear \c bit in IO port \c port. +*/ +#define cbi(port, bit) (port) &= ~(1 << (bit)) + +/*@}*/ + +#endif /* _COMPAT_DEPRECATED_H_ */ diff --git a/hardware/tools/avr/avr/include/compat/ina90.h b/hardware/tools/avr/avr/include/compat/ina90.h new file mode 100644 index 0000000000000000000000000000000000000000..076593ae8bfa1f917bb59a9da9a0c59c7e0b7546 --- /dev/null +++ b/hardware/tools/avr/avr/include/compat/ina90.h @@ -0,0 +1,99 @@ +/* Copyright (c) 2002,2004 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ +/* copied from: Id: avr/ina90.h,v 1.8 2004/11/09 19:16:09 arcanum Exp */ + +/* + ina90.h + + Contributors: + Created by Marek Michalkiewicz + */ + +/** + \defgroup compat_ina90 : Compatibility with IAR EWB 3.x + + \code #include \endcode + + This is an attempt to provide some compatibility with + header files that come with IAR C, to make porting applications + between different compilers easier. No 100% compatibility though. + + \note For actual documentation, please see the IAR manual. + */ + +#ifndef _INA90_H_ +#define _INA90_H_ 1 + +#define _CLI() do { __asm__ __volatile__ ("cli"); } while (0) +#define _SEI() do { __asm__ __volatile__ ("sei"); } while (0) +#define _NOP() do { __asm__ __volatile__ ("nop"); } while (0) +#define _WDR() do { __asm__ __volatile__ ("wdr"); } while (0) +#define _SLEEP() do { __asm__ __volatile__ ("sleep"); } while (0) +#define _OPC(op) do { __asm__ __volatile__ (".word %0" : : "n" (op)); } while (0) + +/* _LPM, _ELPM */ +#include +#define _LPM(x) do { __LPM(x); } while (0) +#define _ELPM(x) do { __ELPM(x); } while (0) + +/* _EEGET, _EEPUT */ +#include + +#define input(port) (port) +#define output(port, val) do { (port) = (val); } while (0) + +#define __inp_blk__(port, addr, cnt, op) do { \ + unsigned char __i = (cnt); \ + unsigned char *__addr = (addr); \ + while (__i) { \ + *(__addr op) = input(port); \ + __i--; \ + } \ + } while (0) + +#define input_block_inc(port, addr, cnt) __inp_blk__(port, addr, cnt, ++) +#define input_block_dec(port, addr, cnt) __inp_blk__(port, addr, cnt, --) + +#define __out_blk__(port, addr, cnt, op) do { \ + unsigned char __i = (cnt); \ + const unsigned char *__addr = (addr); \ + while (__i) { \ + output(port, *(__addr op)); \ + __i--; \ + } \ + } while (0) + +#define output_block_inc(port, addr, cnt) __out_blk__(port, addr, cnt, ++) +#define output_block_dec(port, addr, cnt) __out_blk__(port, addr, cnt, --) + +#endif + diff --git a/hardware/tools/avr/avr/include/compat/twi.h b/hardware/tools/avr/avr/include/compat/twi.h new file mode 100644 index 0000000000000000000000000000000000000000..082852fdfa967e0b4c19369a2d0d3d25a35684e3 --- /dev/null +++ b/hardware/tools/avr/avr/include/compat/twi.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2005 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _COMPAT_TWI_H_ +#define _COMPAT_TWI_H_ + +#include + +#endif /* _COMPAT_TWI_H_ */ diff --git a/hardware/tools/avr/avr/include/ctype.h b/hardware/tools/avr/avr/include/ctype.h new file mode 100644 index 0000000000000000000000000000000000000000..82bce45cd66f539e46c4c05bfe70d2ad2d90d77f --- /dev/null +++ b/hardware/tools/avr/avr/include/ctype.h @@ -0,0 +1,193 @@ +/* Copyright (c) 2002,2007 Michael Stumpf + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + ctype.h - character conversion macros and ctype macros + + Author : Michael Stumpf + Michael.Stumpf@t-online.de +*/ + +#ifndef __CTYPE_H_ +#define __CTYPE_H_ 1 + +#ifndef __ATTR_CONST__ +#define __ATTR_CONST__ __attribute__((__const__)) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file */ +/** \defgroup ctype : Character Operations + These functions perform various operations on characters. + + \code #include \endcode + +*/ + +/** \name Character classification routines + + These functions perform character classification. They return true or + false status depending whether the character passed to the function falls + into the function's classification (i.e. isdigit() returns true if its + argument is any value '0' though '9', inclusive). If the input is not + an unsigned char value, all of this function return false. */ + + /* @{ */ + +/** \ingroup ctype + + Checks for an alphanumeric character. It is equivalent to (isalpha(c) + || isdigit(c)). */ + +extern int isalnum(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for an alphabetic character. It is equivalent to (isupper(c) || + islower(c)). */ + +extern int isalpha(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks whether \c c is a 7-bit unsigned char value that fits into the + ASCII character set. */ + +extern int isascii(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for a blank character, that is, a space or a tab. */ + +extern int isblank(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for a control character. */ + +extern int iscntrl(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for a digit (0 through 9). */ + +extern int isdigit(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for any printable character except space. */ + +extern int isgraph(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for a lower-case character. */ + +extern int islower(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for any printable character including space. */ + +extern int isprint(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for any printable character which is not a space or an alphanumeric + character. */ + +extern int ispunct(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for white-space characters. For the avr-libc library, these are: + space, form-feed ('\\f'), newline ('\\n'), carriage return ('\\r'), + horizontal tab ('\\t'), and vertical tab ('\\v'). */ + +extern int isspace(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for an uppercase letter. */ + +extern int isupper(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7 8 9 a b c d e + f A B C D E F. */ + +extern int isxdigit(int __c) __ATTR_CONST__; + +/* @} */ + +/** \name Character convertion routines + + This realization permits all possible values of integer argument. + The toascii() function clears all highest bits. The tolower() and + toupper() functions return an input argument as is, if it is not an + unsigned char value. */ + +/* @{ */ + +/** \ingroup ctype + + Converts \c c to a 7-bit unsigned char value that fits into the ASCII + character set, by clearing the high-order bits. + + \warning Many people will be unhappy if you use this function. This + function will convert accented letters into random characters. */ + +extern int toascii(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Converts the letter \c c to lower case, if possible. */ + +extern int tolower(int __c) __ATTR_CONST__; + +/** \ingroup ctype + + Converts the letter \c c to upper case, if possible. */ + +extern int toupper(int __c) __ATTR_CONST__; + +/* @} */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/tools/avr/avr/include/errno.h b/hardware/tools/avr/avr/include/errno.h new file mode 100644 index 0000000000000000000000000000000000000000..f7c8cc8bce0d9cfa0d63e53c55188d6976890f7b --- /dev/null +++ b/hardware/tools/avr/avr/include/errno.h @@ -0,0 +1,154 @@ +/* Copyright (c) 2002,2007 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef __ERRNO_H_ +#define __ERRNO_H_ 1 + +/** \file */ +/** \defgroup avr_errno : System Errors + + \code #include \endcode + + Some functions in the library set the global variable \c errno when an + error occurs. The file, \c , provides symbolic names for various + error codes. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \ingroup avr_errno + \brief Error code for last error encountered by library + + The variable \c errno holds the last error code encountered by + a library function. This variable must be cleared by the + user prior to calling a library function. + + \warning The \c errno global variable is not safe to use in a threaded or + multi-task system. A race condition can occur if a task is interrupted + between the call which sets \c error and when the task examines \c + errno. If another task changes \c errno during this time, the result will + be incorrect for the interrupted task. */ +extern int errno; + +#ifdef __cplusplus +} +#endif + +/** \ingroup avr_errno + \def EDOM + + Domain error. */ +#define EDOM 33 + +/** \ingroup avr_errno + \def ERANGE + + Range error. */ +#define ERANGE 34 + +#ifndef __DOXYGEN__ + +/* ((((('E'-64)*26+('N'-64))*26+('O'-64))*26+('S'-64))*26+('Y'-64))*26+'S'-64 */ +#define ENOSYS ((int)(66081697 & 0x7fff)) + +/* (((('E'-64)*26+('I'-64))*26+('N'-64))*26+('T'-64))*26+('R'-64) */ +#define EINTR ((int)(2453066 & 0x7fff)) + +#define E2BIG ENOERR +#define EACCES ENOERR +#define EADDRINUSE ENOERR +#define EADDRNOTAVAIL ENOERR +#define EAFNOSUPPORT ENOERR +#define EAGAIN ENOERR +#define EALREADY ENOERR +#define EBADF ENOERR +#define EBUSY ENOERR +#define ECHILD ENOERR +#define ECONNABORTED ENOERR +#define ECONNREFUSED ENOERR +#define ECONNRESET ENOERR +#define EDEADLK ENOERR +#define EDESTADDRREQ ENOERR +#define EEXIST ENOERR +#define EFAULT ENOERR +#define EFBIG ENOERR +#define EHOSTUNREACH ENOERR +#define EILSEQ ENOERR +#define EINPROGRESS ENOERR +#define EINVAL ENOERR +#define EIO ENOERR +#define EISCONN ENOERR +#define EISDIR ENOERR +#define ELOOP ENOERR +#define EMFILE ENOERR +#define EMLINK ENOERR +#define EMSGSIZE ENOERR +#define ENAMETOOLONG ENOERR +#define ENETDOWN ENOERR +#define ENETRESET ENOERR +#define ENETUNREACH ENOERR +#define ENFILE ENOERR +#define ENOBUFS ENOERR +#define ENODEV ENOERR +#define ENOENT ENOERR +#define ENOEXEC ENOERR +#define ENOLCK ENOERR +#define ENOMEM ENOERR +#define ENOMSG ENOERR +#define ENOPROTOOPT ENOERR +#define ENOSPC ENOERR +#define ENOTCONN ENOERR +#define ENOTDIR ENOERR +#define ENOTEMPTY ENOERR +#define ENOTSOCK ENOERR +#define ENOTTY ENOERR +#define ENXIO ENOERR +#define EOPNOTSUPP ENOERR +#define EPERM ENOERR +#define EPIPE ENOERR +#define EPROTONOSUPPORT ENOERR +#define EPROTOTYPE ENOERR +#define EROFS ENOERR +#define ESPIPE ENOERR +#define ESRCH ENOERR +#define ETIMEDOUT ENOERR +#define EWOULDBLOCK ENOERR +#define EXDEV ENOERR + +/* ((((('E'-64)*26+('N'-64))*26+('O'-64))*26+('E'-64))*26+('R'-64))*26+'R'-64 */ +#define ENOERR ((int)(66072050 & 0xffff)) + +#endif /* !__DOXYGEN__ */ + +#endif diff --git a/hardware/tools/avr/avr/include/fcntl.h b/hardware/tools/avr/avr/include/fcntl.h new file mode 100644 index 0000000000000000000000000000000000000000..a12c43b15a9ea213d712b87f9f64657b2eab2d32 --- /dev/null +++ b/hardware/tools/avr/avr/include/fcntl.h @@ -0,0 +1 @@ +#include diff --git a/hardware/tools/avr/avr/include/inttypes.h b/hardware/tools/avr/avr/include/inttypes.h new file mode 100644 index 0000000000000000000000000000000000000000..6e69d745ea3101ddf19163b870fa00f5f8f1c66d --- /dev/null +++ b/hardware/tools/avr/avr/include/inttypes.h @@ -0,0 +1,555 @@ +/* Copyright (c) 2004,2005,2007,2012 Joerg Wunsch + Copyright (c) 2005, Carlos Lamas + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef __INTTYPES_H_ +#define __INTTYPES_H_ + +#include + +/** \file */ +/** \defgroup avr_inttypes : Integer Type conversions + \code #include \endcode + + This header file includes the exact-width integer definitions from + , and extends them with additional facilities + provided by the implementation. + + Currently, the extensions include two additional integer types + that could hold a "far" pointer (i.e. a code pointer that can + address more than 64 KB), as well as standard names for all printf + and scanf formatting options that are supported by the \ref avr_stdio. + As the library does not support the full range of conversion + specifiers from ISO 9899:1999, only those conversions that are + actually implemented will be listed here. + + The idea behind these conversion macros is that, for each of the + types defined by , a macro will be supplied that portably + allows formatting an object of that type in printf() or scanf() + operations. Example: + + \code + #include + + uint8_t smallval; + int32_t longval; + ... + printf("The hexadecimal value of smallval is %" PRIx8 + ", the decimal value of longval is %" PRId32 ".\n", + smallval, longval); + \endcode +*/ + +/** \name Far pointers for memory access >64K */ + +/*@{*/ +/** \ingroup avr_inttypes + signed integer type that can hold a pointer > 64 KB */ +typedef int32_t int_farptr_t; + +/** \ingroup avr_inttypes + unsigned integer type that can hold a pointer > 64 KB */ +typedef uint32_t uint_farptr_t; +/*@}*/ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + + +/** \name macros for printf and scanf format specifiers + + For C++, these are only included if __STDC_LIMIT_MACROS + is defined before including . + */ + +/*@{*/ +/** \ingroup avr_inttypes + decimal printf format for int8_t */ +#define PRId8 "d" +/** \ingroup avr_inttypes + decimal printf format for int_least8_t */ +#define PRIdLEAST8 "d" +/** \ingroup avr_inttypes + decimal printf format for int_fast8_t */ +#define PRIdFAST8 "d" + +/** \ingroup avr_inttypes + integer printf format for int8_t */ +#define PRIi8 "i" +/** \ingroup avr_inttypes + integer printf format for int_least8_t */ +#define PRIiLEAST8 "i" +/** \ingroup avr_inttypes + integer printf format for int_fast8_t */ +#define PRIiFAST8 "i" + + +/** \ingroup avr_inttypes + decimal printf format for int16_t */ +#define PRId16 "d" +/** \ingroup avr_inttypes + decimal printf format for int_least16_t */ +#define PRIdLEAST16 "d" +/** \ingroup avr_inttypes + decimal printf format for int_fast16_t */ +#define PRIdFAST16 "d" + +/** \ingroup avr_inttypes + integer printf format for int16_t */ +#define PRIi16 "i" +/** \ingroup avr_inttypes + integer printf format for int_least16_t */ +#define PRIiLEAST16 "i" +/** \ingroup avr_inttypes + integer printf format for int_fast16_t */ +#define PRIiFAST16 "i" + + +/** \ingroup avr_inttypes + decimal printf format for int32_t */ +#define PRId32 "ld" +/** \ingroup avr_inttypes + decimal printf format for int_least32_t */ +#define PRIdLEAST32 "ld" +/** \ingroup avr_inttypes + decimal printf format for int_fast32_t */ +#define PRIdFAST32 "ld" + +/** \ingroup avr_inttypes + integer printf format for int32_t */ +#define PRIi32 "li" +/** \ingroup avr_inttypes + integer printf format for int_least32_t */ +#define PRIiLEAST32 "li" +/** \ingroup avr_inttypes + integer printf format for int_fast32_t */ +#define PRIiFAST32 "li" + + +#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf + +#define PRId64 "lld" +#define PRIdLEAST64 "lld" +#define PRIdFAST64 "lld" + +#define PRIi64 "lli" +#define PRIiLEAST64 "lli" +#define PRIiFAST64 "lli" + + +#define PRIdMAX "lld" +#define PRIiMAX "lli" + +#endif + +/** \ingroup avr_inttypes + decimal printf format for intptr_t */ +#define PRIdPTR PRId16 +/** \ingroup avr_inttypes + integer printf format for intptr_t */ +#define PRIiPTR PRIi16 + +/** \ingroup avr_inttypes + octal printf format for uint8_t */ +#define PRIo8 "o" +/** \ingroup avr_inttypes + octal printf format for uint_least8_t */ +#define PRIoLEAST8 "o" +/** \ingroup avr_inttypes + octal printf format for uint_fast8_t */ +#define PRIoFAST8 "o" + +/** \ingroup avr_inttypes + decimal printf format for uint8_t */ +#define PRIu8 "u" +/** \ingroup avr_inttypes + decimal printf format for uint_least8_t */ +#define PRIuLEAST8 "u" +/** \ingroup avr_inttypes + decimal printf format for uint_fast8_t */ +#define PRIuFAST8 "u" + +/** \ingroup avr_inttypes + hexadecimal printf format for uint8_t */ +#define PRIx8 "x" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_least8_t */ +#define PRIxLEAST8 "x" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_fast8_t */ +#define PRIxFAST8 "x" + +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint8_t */ +#define PRIX8 "X" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_least8_t */ +#define PRIXLEAST8 "X" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_fast8_t */ +#define PRIXFAST8 "X" + + +/** \ingroup avr_inttypes + octal printf format for uint16_t */ +#define PRIo16 "o" +/** \ingroup avr_inttypes + octal printf format for uint_least16_t */ +#define PRIoLEAST16 "o" +/** \ingroup avr_inttypes + octal printf format for uint_fast16_t */ +#define PRIoFAST16 "o" + +/** \ingroup avr_inttypes + decimal printf format for uint16_t */ +#define PRIu16 "u" +/** \ingroup avr_inttypes + decimal printf format for uint_least16_t */ +#define PRIuLEAST16 "u" +/** \ingroup avr_inttypes + decimal printf format for uint_fast16_t */ +#define PRIuFAST16 "u" + +/** \ingroup avr_inttypes + hexadecimal printf format for uint16_t */ +#define PRIx16 "x" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_least16_t */ +#define PRIxLEAST16 "x" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_fast16_t */ +#define PRIxFAST16 "x" + +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint16_t */ +#define PRIX16 "X" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_least16_t */ +#define PRIXLEAST16 "X" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_fast16_t */ +#define PRIXFAST16 "X" + + +/** \ingroup avr_inttypes + octal printf format for uint32_t */ +#define PRIo32 "lo" +/** \ingroup avr_inttypes + octal printf format for uint_least32_t */ +#define PRIoLEAST32 "lo" +/** \ingroup avr_inttypes + octal printf format for uint_fast32_t */ +#define PRIoFAST32 "lo" + +/** \ingroup avr_inttypes + decimal printf format for uint32_t */ +#define PRIu32 "lu" +/** \ingroup avr_inttypes + decimal printf format for uint_least32_t */ +#define PRIuLEAST32 "lu" +/** \ingroup avr_inttypes + decimal printf format for uint_fast32_t */ +#define PRIuFAST32 "lu" + +/** \ingroup avr_inttypes + hexadecimal printf format for uint32_t */ +#define PRIx32 "lx" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_least32_t */ +#define PRIxLEAST32 "lx" +/** \ingroup avr_inttypes + hexadecimal printf format for uint_fast32_t */ +#define PRIxFAST32 "lx" + +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint32_t */ +#define PRIX32 "lX" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_least32_t */ +#define PRIXLEAST32 "lX" +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uint_fast32_t */ +#define PRIXFAST32 "lX" + + +#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf + +#define PRIo64 "llo" +#define PRIoLEAST64 "llo" +#define PRIoFAST64 "llo" + +#define PRIu64 "llu" +#define PRIuLEAST64 "llu" +#define PRIuFAST64 "llu" + +#define PRIx64 "llx" +#define PRIxLEAST64 "llx" +#define PRIxFAST64 "llx" + +#define PRIX64 "llX" +#define PRIXLEAST64 "llX" +#define PRIXFAST64 "llX" + +#define PRIoMAX "llo" +#define PRIuMAX "llu" +#define PRIxMAX "llx" +#define PRIXMAX "llX" + +#endif + +/** \ingroup avr_inttypes + octal printf format for uintptr_t */ +#define PRIoPTR PRIo16 +/** \ingroup avr_inttypes + decimal printf format for uintptr_t */ +#define PRIuPTR PRIu16 +/** \ingroup avr_inttypes + hexadecimal printf format for uintptr_t */ +#define PRIxPTR PRIx16 +/** \ingroup avr_inttypes + uppercase hexadecimal printf format for uintptr_t */ +#define PRIXPTR PRIX16 + + +/** \ingroup avr_inttypes + decimal scanf format for int8_t */ +#define SCNd8 "hhd" +/** \ingroup avr_inttypes + decimal scanf format for int_least8_t */ +#define SCNdLEAST8 "hhd" +/** \ingroup avr_inttypes + decimal scanf format for int_fast8_t */ +#define SCNdFAST8 "hhd" + +/** \ingroup avr_inttypes + generic-integer scanf format for int8_t */ +#define SCNi8 "hhi" +/** \ingroup avr_inttypes + generic-integer scanf format for int_least8_t */ +#define SCNiLEAST8 "hhi" +/** \ingroup avr_inttypes + generic-integer scanf format for int_fast8_t */ +#define SCNiFAST8 "hhi" + + +/** \ingroup avr_inttypes + decimal scanf format for int16_t */ +#define SCNd16 "d" +/** \ingroup avr_inttypes + decimal scanf format for int_least16_t */ +#define SCNdLEAST16 "d" +/** \ingroup avr_inttypes + decimal scanf format for int_fast16_t */ +#define SCNdFAST16 "d" + +/** \ingroup avr_inttypes + generic-integer scanf format for int16_t */ +#define SCNi16 "i" +/** \ingroup avr_inttypes + generic-integer scanf format for int_least16_t */ +#define SCNiLEAST16 "i" +/** \ingroup avr_inttypes + generic-integer scanf format for int_fast16_t */ +#define SCNiFAST16 "i" + + +/** \ingroup avr_inttypes + decimal scanf format for int32_t */ +#define SCNd32 "ld" +/** \ingroup avr_inttypes + decimal scanf format for int_least32_t */ +#define SCNdLEAST32 "ld" +/** \ingroup avr_inttypes + decimal scanf format for int_fast32_t */ +#define SCNdFAST32 "ld" + +/** \ingroup avr_inttypes + generic-integer scanf format for int32_t */ +#define SCNi32 "li" +/** \ingroup avr_inttypes + generic-integer scanf format for int_least32_t */ +#define SCNiLEAST32 "li" +/** \ingroup avr_inttypes + generic-integer scanf format for int_fast32_t */ +#define SCNiFAST32 "li" + + +#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf + +#define SCNd64 "lld" +#define SCNdLEAST64 "lld" +#define SCNdFAST64 "lld" + +#define SCNi64 "lli" +#define SCNiLEAST64 "lli" +#define SCNiFAST64 "lli" + +#define SCNdMAX "lld" +#define SCNiMAX "lli" + +#endif + +/** \ingroup avr_inttypes + decimal scanf format for intptr_t */ +#define SCNdPTR SCNd16 +/** \ingroup avr_inttypes + generic-integer scanf format for intptr_t */ +#define SCNiPTR SCNi16 + +/** \ingroup avr_inttypes + octal scanf format for uint8_t */ +#define SCNo8 "hho" +/** \ingroup avr_inttypes + octal scanf format for uint_least8_t */ +#define SCNoLEAST8 "hho" +/** \ingroup avr_inttypes + octal scanf format for uint_fast8_t */ +#define SCNoFAST8 "hho" + +/** \ingroup avr_inttypes + decimal scanf format for uint8_t */ +#define SCNu8 "hhu" +/** \ingroup avr_inttypes + decimal scanf format for uint_least8_t */ +#define SCNuLEAST8 "hhu" +/** \ingroup avr_inttypes + decimal scanf format for uint_fast8_t */ +#define SCNuFAST8 "hhu" + +/** \ingroup avr_inttypes + hexadecimal scanf format for uint8_t */ +#define SCNx8 "hhx" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_least8_t */ +#define SCNxLEAST8 "hhx" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_fast8_t */ +#define SCNxFAST8 "hhx" + +/** \ingroup avr_inttypes + octal scanf format for uint16_t */ +#define SCNo16 "o" +/** \ingroup avr_inttypes + octal scanf format for uint_least16_t */ +#define SCNoLEAST16 "o" +/** \ingroup avr_inttypes + octal scanf format for uint_fast16_t */ +#define SCNoFAST16 "o" + +/** \ingroup avr_inttypes + decimal scanf format for uint16_t */ +#define SCNu16 "u" +/** \ingroup avr_inttypes + decimal scanf format for uint_least16_t */ +#define SCNuLEAST16 "u" +/** \ingroup avr_inttypes + decimal scanf format for uint_fast16_t */ +#define SCNuFAST16 "u" + +/** \ingroup avr_inttypes + hexadecimal scanf format for uint16_t */ +#define SCNx16 "x" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_least16_t */ +#define SCNxLEAST16 "x" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_fast16_t */ +#define SCNxFAST16 "x" + + +/** \ingroup avr_inttypes + octal scanf format for uint32_t */ +#define SCNo32 "lo" +/** \ingroup avr_inttypes + octal scanf format for uint_least32_t */ +#define SCNoLEAST32 "lo" +/** \ingroup avr_inttypes + octal scanf format for uint_fast32_t */ +#define SCNoFAST32 "lo" + +/** \ingroup avr_inttypes + decimal scanf format for uint32_t */ +#define SCNu32 "lu" +/** \ingroup avr_inttypes + decimal scanf format for uint_least32_t */ +#define SCNuLEAST32 "lu" +/** \ingroup avr_inttypes + decimal scanf format for uint_fast32_t */ +#define SCNuFAST32 "lu" + +/** \ingroup avr_inttypes + hexadecimal scanf format for uint32_t */ +#define SCNx32 "lx" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_least32_t */ +#define SCNxLEAST32 "lx" +/** \ingroup avr_inttypes + hexadecimal scanf format for uint_fast32_t */ +#define SCNxFAST32 "lx" + + +#ifdef __avr_libc_does_not_implement_long_long_in_printf_or_scanf + +#define SCNo64 "llo" +#define SCNoLEAST64 "llo" +#define SCNoFAST64 "llo" + +#define SCNu64 "llu" +#define SCNuLEAST64 "llu" +#define SCNuFAST64 "llu" + +#define SCNx64 "llx" +#define SCNxLEAST64 "llx" +#define SCNxFAST64 "llx" + +#define SCNoMAX "llo" +#define SCNuMAX "llu" +#define SCNxMAX "llx" + +#endif + +/** \ingroup avr_inttypes + octal scanf format for uintptr_t */ +#define SCNoPTR SCNo16 +/** \ingroup avr_inttypes + decimal scanf format for uintptr_t */ +#define SCNuPTR SCNu16 +/** \ingroup avr_inttypes + hexadecimal scanf format for uintptr_t */ +#define SCNxPTR SCNx16 + +/*@}*/ + + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + + +#endif /* __INTTYPES_H_ */ diff --git a/hardware/tools/avr/avr/include/locale.h b/hardware/tools/avr/avr/include/locale.h new file mode 100644 index 0000000000000000000000000000000000000000..91ae7bc764be06ec0a641f6480a214c91e952427 --- /dev/null +++ b/hardware/tools/avr/avr/include/locale.h @@ -0,0 +1,17 @@ +#ifndef _LOCALE_H +#define _LOCALE_H + +#if 1 /* ??? unimplemented */ +#define LC_ALL 0 +#define LC_COLLATE 1 +#define LC_CTYPE 2 +#define LC_MESSAGES 3 +#define LC_MONETARY 4 +#define LC_NUMERIC 5 +#define LC_TIME 6 +struct lconv; +extern char *setlocale(int category, const char *locale); +extern struct lconv *localeconv(void); +#endif + +#endif /* L_OCALE_H */ diff --git a/hardware/tools/avr/avr/include/math.h b/hardware/tools/avr/avr/include/math.h new file mode 100644 index 0000000000000000000000000000000000000000..92e2b12d07cea1744ec386700b33859a759d824f --- /dev/null +++ b/hardware/tools/avr/avr/include/math.h @@ -0,0 +1,462 @@ +/* Copyright (c) 2002,2007-2009 Michael Stumpf + + Portions of documentation Copyright (c) 1990 - 1994 + The Regents of the University of California. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + math.h - mathematical functions + + Author : Michael Stumpf + Michael.Stumpf@t-online.de + + __ATTR_CONST__ added by marekm@linux.org.pl for functions + that "do not examine any values except their arguments, and have + no effects except the return value", for better optimization by gcc. + */ + +#ifndef __MATH_H +#define __MATH_H + +/** \file */ +/** \defgroup avr_math : Mathematics + \code #include \endcode + + This header file declares basic mathematics constants and + functions. + + \par Notes: + - In order to access the functions declared herein, it is usually + also required to additionally link against the library \c libm.a. + See also the related \ref faq_libm "FAQ entry". + - Math functions do not raise exceptions and do not change the + \c errno variable. Therefore the majority of them are declared + with const attribute, for better optimization by GCC. */ + + +/** \ingroup avr_math */ +/*@{*/ + +/** The constant \a e. */ +#define M_E 2.7182818284590452354 + +/** The logarithm of the \a e to base 2. */ +#define M_LOG2E 1.4426950408889634074 /* log_2 e */ + +/** The logarithm of the \a e to base 10. */ +#define M_LOG10E 0.43429448190325182765 /* log_10 e */ + +/** The natural logarithm of the 2. */ +#define M_LN2 0.69314718055994530942 /* log_e 2 */ + +/** The natural logarithm of the 10. */ +#define M_LN10 2.30258509299404568402 /* log_e 10 */ + +/** The constant \a pi. */ +#define M_PI 3.14159265358979323846 /* pi */ + +/** The constant \a pi/2. */ +#define M_PI_2 1.57079632679489661923 /* pi/2 */ + +/** The constant \a pi/4. */ +#define M_PI_4 0.78539816339744830962 /* pi/4 */ + +/** The constant \a 1/pi. */ +#define M_1_PI 0.31830988618379067154 /* 1/pi */ + +/** The constant \a 2/pi. */ +#define M_2_PI 0.63661977236758134308 /* 2/pi */ + +/** The constant \a 2/sqrt(pi). */ +#define M_2_SQRTPI 1.12837916709551257390 /* 2/sqrt(pi) */ + +/** The square root of 2. */ +#define M_SQRT2 1.41421356237309504880 /* sqrt(2) */ + +/** The constant \a 1/sqrt(2). */ +#define M_SQRT1_2 0.70710678118654752440 /* 1/sqrt(2) */ + +/** NAN constant. */ +#define NAN __builtin_nan("") + +/** INFINITY constant. */ +#define INFINITY __builtin_inf() + + +#ifndef __ATTR_CONST__ +# define __ATTR_CONST__ __attribute__((__const__)) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + The cos() function returns the cosine of \a __x, measured in radians. + */ +extern double cos(double __x) __ATTR_CONST__; +#define cosf cos /**< The alias for cos(). */ + +/** + The sin() function returns the sine of \a __x, measured in radians. + */ +extern double sin(double __x) __ATTR_CONST__; +#define sinf sin /**< The alias for sin(). */ + +/** + The tan() function returns the tangent of \a __x, measured in radians. + */ +extern double tan(double __x) __ATTR_CONST__; +#define tanf tan /**< The alias for tan(). */ + +/** + The fabs() function computes the absolute value of a floating-point + number \a __x. + */ +extern double fabs(double __x) __ATTR_CONST__; +#define fabsf fabs /**< The alias for fabs(). */ + +/** + The function fmod() returns the floating-point remainder of __x / + __y. + */ +extern double fmod(double __x, double __y) __ATTR_CONST__; +#define fmodf fmod /**< The alias for fmod(). */ + +/** + The modf() function breaks the argument \a __x into integral and + fractional parts, each of which has the same sign as the argument. + It stores the integral part as a double in the object pointed to by + \a __iptr. + + The modf() function returns the signed fractional part of \a __x. + + \note This implementation skips writing by zero pointer. However, + the GCC 4.3 can replace this function with inline code that does not + permit to use NULL address for the avoiding of storing. + */ +extern double modf(double __x, double *__iptr); + +/** An alias for modf(). */ +extern float modff (float __x, float *__iptr); + +/** + The sqrt() function returns the non-negative square root of \a __x. + */ +extern double sqrt(double __x) __ATTR_CONST__; + +/** An alias for sqrt(). */ +extern float sqrtf (float) __ATTR_CONST__; + +/** + The cbrt() function returns the cube root of \a __x. + */ +extern double cbrt(double __x) __ATTR_CONST__; +#define cbrtf cbrt /**< The alias for cbrt(). */ + +/** + The hypot() function returns sqrt(__x*__x + __y*__y). This + is the length of the hypotenuse of a right triangle with sides of + length \a __x and \a __y, or the distance of the point (\a __x, \a + __y) from the origin. Using this function instead of the direct + formula is wise, since the error is much smaller. No underflow with + small \a __x and \a __y. No overflow if result is in range. + */ +extern double hypot (double __x, double __y) __ATTR_CONST__; +#define hypotf hypot /**< The alias for hypot(). */ + +/** + The function square() returns __x * __x. + + \note This function does not belong to the C standard definition. + */ +extern double square(double __x) __ATTR_CONST__; +#define squaref square /**< The alias for square(). */ + +/** + The floor() function returns the largest integral value less than or + equal to \a __x, expressed as a floating-point number. + */ +extern double floor(double __x) __ATTR_CONST__; +#define floorf floor /**< The alias for floor(). */ + +/** + The ceil() function returns the smallest integral value greater than + or equal to \a __x, expressed as a floating-point number. + */ +extern double ceil(double __x) __ATTR_CONST__; +#define ceilf ceil /**< The alias for ceil(). */ + +/** + The frexp() function breaks a floating-point number into a normalized + fraction and an integral power of 2. It stores the integer in the \c + int object pointed to by \a __pexp. + + If \a __x is a normal float point number, the frexp() function + returns the value \c v, such that \c v has a magnitude in the + interval [1/2, 1) or zero, and \a __x equals \c v times 2 raised to + the power \a __pexp. If \a __x is zero, both parts of the result are + zero. If \a __x is not a finite number, the frexp() returns \a __x as + is and stores 0 by \a __pexp. + + \note This implementation permits a zero pointer as a directive to + skip a storing the exponent. + */ +extern double frexp(double __x, int *__pexp); +#define frexpf frexp /**< The alias for frexp(). */ + +/** + The ldexp() function multiplies a floating-point number by an integral + power of 2. It returns the value of \a __x times 2 raised to the power + \a __exp. + */ +extern double ldexp(double __x, int __exp) __ATTR_CONST__; +#define ldexpf ldexp /**< The alias for ldexp(). */ + +/** + The exp() function returns the exponential value of \a __x. + */ +extern double exp(double __x) __ATTR_CONST__; +#define expf exp /**< The alias for exp(). */ + +/** + The cosh() function returns the hyperbolic cosine of \a __x. + */ +extern double cosh(double __x) __ATTR_CONST__; +#define coshf cosh /**< The alias for cosh(). */ + +/** + The sinh() function returns the hyperbolic sine of \a __x. + */ +extern double sinh(double __x) __ATTR_CONST__; +#define sinhf sinh /**< The alias for sinh(). */ + +/** + The tanh() function returns the hyperbolic tangent of \a __x. + */ +extern double tanh(double __x) __ATTR_CONST__; +#define tanhf tanh /**< The alias for tanh(). */ + +/** + The acos() function computes the principal value of the arc cosine of + \a __x. The returned value is in the range [0, pi] radians. A domain + error occurs for arguments not in the range [-1, +1]. + */ +extern double acos(double __x) __ATTR_CONST__; +#define acosf acos /**< The alias for acos(). */ + +/** + The asin() function computes the principal value of the arc sine of + \a __x. The returned value is in the range [-pi/2, pi/2] radians. A + domain error occurs for arguments not in the range [-1, +1]. + */ +extern double asin(double __x) __ATTR_CONST__; +#define asinf asin /**< The alias for asin(). */ + +/** + The atan() function computes the principal value of the arc tangent + of \a __x. The returned value is in the range [-pi/2, pi/2] radians. + */ +extern double atan(double __x) __ATTR_CONST__; +#define atanf atan /**< The alias for atan(). */ + +/** + The atan2() function computes the principal value of the arc tangent + of __y / __x, using the signs of both arguments to determine + the quadrant of the return value. The returned value is in the range + [-pi, +pi] radians. + */ +extern double atan2(double __y, double __x) __ATTR_CONST__; +#define atan2f atan2 /**< The alias for atan2(). */ + +/** + The log() function returns the natural logarithm of argument \a __x. + */ +extern double log(double __x) __ATTR_CONST__; +#define logf log /**< The alias for log(). */ + +/** + The log10() function returns the logarithm of argument \a __x to base 10. + */ +extern double log10(double __x) __ATTR_CONST__; +#define log10f log10 /**< The alias for log10(). */ + +/** + The function pow() returns the value of \a __x to the exponent \a __y. + */ +extern double pow(double __x, double __y) __ATTR_CONST__; +#define powf pow /**< The alias for pow(). */ + +/** + The function isnan() returns 1 if the argument \a __x represents a + "not-a-number" (NaN) object, otherwise 0. + */ +extern int isnan(double __x) __ATTR_CONST__; +#define isnanf isnan /**< The alias for isnan(). */ + +/** + The function isinf() returns 1 if the argument \a __x is positive + infinity, -1 if \a __x is negative infinity, and 0 otherwise. + + \note The GCC 4.3 can replace this function with inline code that + returns the 1 value for both infinities (gcc bug #35509). + */ +extern int isinf(double __x) __ATTR_CONST__; +#define isinff isinf /**< The alias for isinf(). */ + +/** + The isfinite() function returns a nonzero value if \a __x is finite: + not plus or minus infinity, and not NaN. + */ +__ATTR_CONST__ static inline int isfinite (double __x) +{ + unsigned char __exp; + __asm__ ( + "mov %0, %C1 \n\t" + "lsl %0 \n\t" + "mov %0, %D1 \n\t" + "rol %0 " + : "=r" (__exp) + : "r" (__x) ); + return __exp != 0xff; +} +#define isfinitef isfinite /**< The alias for isfinite(). */ + +/** + The copysign() function returns \a __x but with the sign of \a __y. + They work even if \a __x or \a __y are NaN or zero. +*/ +__ATTR_CONST__ static inline double copysign (double __x, double __y) +{ + __asm__ ( + "bst %D2, 7 \n\t" + "bld %D0, 7 " + : "=r" (__x) + : "0" (__x), "r" (__y) ); + return __x; +} +#define copysignf copysign /**< The alias for copysign(). */ + +/** + The signbit() function returns a nonzero value if the value of \a __x + has its sign bit set. This is not the same as `\a __x < 0.0', + because IEEE 754 floating point allows zero to be signed. The + comparison `-0.0 < 0.0' is false, but `signbit (-0.0)' will return a + nonzero value. + */ +extern int signbit (double __x) __ATTR_CONST__; +#define signbitf signbit /**< The alias for signbit(). */ + +/** + The fdim() function returns max(__x - __y, 0). If \a __x or + \a __y or both are NaN, NaN is returned. + */ +extern double fdim (double __x, double __y) __ATTR_CONST__; +#define fdimf fdim /**< The alias for fdim(). */ + +/** + The fma() function performs floating-point multiply-add. This is the + operation (__x * __y) + __z, but the intermediate result is + not rounded to the destination type. This can sometimes improve the + precision of a calculation. + */ +extern double fma (double __x, double __y, double __z) __ATTR_CONST__; +#define fmaf fma /**< The alias for fma(). */ + +/** + The fmax() function returns the greater of the two values \a __x and + \a __y. If an argument is NaN, the other argument is returned. If + both arguments are NaN, NaN is returned. + */ +extern double fmax (double __x, double __y) __ATTR_CONST__; +#define fmaxf fmax /**< The alias for fmax(). */ + +/** + The fmin() function returns the lesser of the two values \a __x and + \a __y. If an argument is NaN, the other argument is returned. If + both arguments are NaN, NaN is returned. + */ +extern double fmin (double __x, double __y) __ATTR_CONST__; +#define fminf fmin /**< The alias for fmin(). */ + +/** + The trunc() function rounds \a __x to the nearest integer not larger + in absolute value. + */ +extern double trunc (double __x) __ATTR_CONST__; +#define truncf trunc /**< The alias for trunc(). */ + +/** + The round() function rounds \a __x to the nearest integer, but rounds + halfway cases away from zero (instead of to the nearest even integer). + Overflow is impossible. + + \return The rounded value. If \a __x is an integral or infinite, \a + __x itself is returned. If \a __x is \c NaN, then \c NaN is returned. + */ +extern double round (double __x) __ATTR_CONST__; +#define roundf round /**< The alias for round(). */ + +/** + The lround() function rounds \a __x to the nearest integer, but rounds + halfway cases away from zero (instead of to the nearest even integer). + This function is similar to round() function, but it differs in type of + return value and in that an overflow is possible. + + \return The rounded long integer value. If \a __x is not a finite number + or an overflow was, this realization returns the \c LONG_MIN value + (0x80000000). + */ +extern long lround (double __x) __ATTR_CONST__; +#define lroundf lround /**< The alias for lround(). */ + +/** + The lrint() function rounds \a __x to the nearest integer, rounding the + halfway cases to the even integer direction. (That is both 1.5 and 2.5 + values are rounded to 2). This function is similar to rint() function, + but it differs in type of return value and in that an overflow is + possible. + + \return The rounded long integer value. If \a __x is not a finite + number or an overflow was, this realization returns the \c LONG_MIN + value (0x80000000). + */ +extern long lrint (double __x) __ATTR_CONST__; +#define lrintf lrint /**< The alias for lrint(). */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ +#endif /* !__MATH_H */ diff --git a/hardware/tools/avr/avr/include/setjmp.h b/hardware/tools/avr/avr/include/setjmp.h new file mode 100644 index 0000000000000000000000000000000000000000..1038a1e0c0444b6f04ff634d09397f632332ec9d --- /dev/null +++ b/hardware/tools/avr/avr/include/setjmp.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2002,2007 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef __SETJMP_H_ +#define __SETJMP_H_ 1 + +#ifdef __cplusplus +extern "C" { +#endif + +/* + jmp_buf: + offset size description + 0 16/2 call-saved registers (r2-r17) + (AVR_TINY arch has only 2 call saved registers (r18,r19)) + 16/2 2 frame pointer (r29:r28) + 18/4 2 stack pointer (SPH:SPL) + 20/6 1 status register (SREG) + 21/7 2/3 return address (PC) (2 bytes used for <=128Kw flash) + 23/24/9 = total size (AVR_TINY arch always has 2 bytes PC) + */ + +#if !defined(__DOXYGEN__) + +#if defined(__AVR_TINY__) +# define _JBLEN 9 +#elif defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__ +# define _JBLEN 24 +#else +# define _JBLEN 23 +#endif +typedef struct _jmp_buf { unsigned char _jb[_JBLEN]; } jmp_buf[1]; + +#endif /* not __DOXYGEN__ */ + +/** \file */ +/** \defgroup setjmp : Non-local goto + + While the C language has the dreaded \c goto statement, it can only be + used to jump to a label in the same (local) function. In order to jump + directly to another (non-local) function, the C library provides the + setjmp() and longjmp() functions. setjmp() and longjmp() are useful for + dealing with errors and interrupts encountered in a low-level subroutine + of a program. + + \note setjmp() and longjmp() make programs hard to understand and maintain. + If possible, an alternative should be used. + + \note longjmp() can destroy changes made to global register + variables (see \ref faq_regbind). + + For a very detailed discussion of setjmp()/longjmp(), see Chapter 7 of + Advanced Programming in the UNIX Environment, by W. Richard + Stevens. + + Example: + + \code + #include + + jmp_buf env; + + int main (void) + { + if (setjmp (env)) + { + ... handle error ... + } + + while (1) + { + ... main processing loop which calls foo() some where ... + } + } + + ... + + void foo (void) + { + ... blah, blah, blah ... + + if (err) + { + longjmp (env, 1); + } + } + \endcode */ + +#if !(defined(__ATTR_NORETURN__) || defined(__DOXYGEN__)) +#define __ATTR_NORETURN__ __attribute__((__noreturn__)) +#endif + +/** \ingroup setjmp + \brief Save stack context for non-local goto. + + \code #include \endcode + + setjmp() saves the stack context/environment in \e __jmpb for later use by + longjmp(). The stack context will be invalidated if the function which + called setjmp() returns. + + \param __jmpb Variable of type \c jmp_buf which holds the stack + information such that the environment can be restored. + + \returns setjmp() returns 0 if returning directly, and + non-zero when returning from longjmp() using the saved context. */ + +extern int setjmp(jmp_buf __jmpb); + +/** \ingroup setjmp + \brief Non-local jump to a saved stack context. + + \code #include \endcode + + longjmp() restores the environment saved by the last call of setjmp() with + the corresponding \e __jmpb argument. After longjmp() is completed, + program execution continues as if the corresponding call of setjmp() had + just returned the value \e __ret. + + \note longjmp() cannot cause 0 to be returned. If longjmp() is invoked + with a second argument of 0, 1 will be returned instead. + + \param __jmpb Information saved by a previous call to setjmp(). + \param __ret Value to return to the caller of setjmp(). + + \returns This function never returns. */ + +extern void longjmp(jmp_buf __jmpb, int __ret) __ATTR_NORETURN__; + +#ifdef __cplusplus +} +#endif + +#endif /* !__SETJMP_H_ */ diff --git a/hardware/tools/avr/avr/include/signal.h b/hardware/tools/avr/avr/include/signal.h new file mode 100644 index 0000000000000000000000000000000000000000..5274fcd0586d03b9d610b4f9d3c56fe8859d2f5a --- /dev/null +++ b/hardware/tools/avr/avr/include/signal.h @@ -0,0 +1,20 @@ +#ifndef _SIGNAL_H +#define _SIGNAL_H + +/* A minimal header to allow libstdc++-v3 pre-compiled headers to build. + We just pretend that there are signal / raise functions, even though + they are not implemented. */ +typedef void (*sighandler_t)(int); +extern sighandler_t signal(int signum, sighandler_t handler); + +#define SIG_DFL ((sighandler_t)0) +#define SIG_ERR ((sighandler_t)((void*)signal+1)) +#define SIG_HOLD ((sighandler_t)((void*)signal+2)) +#define SIG_IGN ((sighandler_t)((void*)signal+3)) + +volatile signed char sig_atomic_t; +typedef int sigset_t; + +extern int raise(int sig); + +#endif /* _SIGNAL_H */ diff --git a/hardware/tools/avr/avr/include/stdfix-avrlibc.h b/hardware/tools/avr/avr/include/stdfix-avrlibc.h new file mode 100644 index 0000000000000000000000000000000000000000..d1339991aca1527b1cdad6ba451fe79e00cd0c6b --- /dev/null +++ b/hardware/tools/avr/avr/include/stdfix-avrlibc.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2013 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _STDFIX_AVRLIBC_H +#define _STDFIX_AVRLIBC_H + +/* + * avr-libc addendum file for Embedded C Fixed-Point support + * + * See: ISO/IEC TR 18037 + * http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1169.pdf + */ + +#ifndef _AVRGCC_STDFIX_H /* Defined in stdfix.h from avr-gcc */ +#warning please include directly rather than +#endif /* _AVRGCC_STDFIX_H */ + +/* Room for avr-libc specific extensions */ + +#endif /* _STDFIX_AVRLIBC_H */ diff --git a/hardware/tools/avr/avr/include/stdint.h b/hardware/tools/avr/avr/include/stdint.h new file mode 100644 index 0000000000000000000000000000000000000000..a882e304b982ab662c180474cb8600075330384b --- /dev/null +++ b/hardware/tools/avr/avr/include/stdint.h @@ -0,0 +1,706 @@ +/* Copyright (c) 2002,2004,2005 Marek Michalkiewicz + Copyright (c) 2005, Carlos Lamas + Copyright (c) 2005,2007 Joerg Wunsch + Copyright (c) 2013 Embecosm + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + * ISO/IEC 9899:1999 7.18 Integer types + */ + +#ifndef __STDINT_H_ +#define __STDINT_H_ + +/** \file */ +/** \defgroup avr_stdint : Standard Integer Types + \code #include \endcode + + Use [u]intN_t if you need exactly N bits. + + Since these typedefs are mandated by the C99 standard, they are preferred + over rolling your own typedefs. */ + +#ifndef __DOXYGEN__ +/* + * __USING_MINT8 is defined to 1 if the -mint8 option is in effect. + */ +#if __INT_MAX__ == 127 +# define __USING_MINT8 1 +#else +# define __USING_MINT8 0 +#endif + +#endif /* !__DOXYGEN__ */ + +/* Integer types */ + +#if defined(__DOXYGEN__) + +/* doxygen gets confused by the __attribute__ stuff */ + +/** \name Exact-width integer types + Integer types having exactly the specified width */ + +/*@{*/ + +/** \ingroup avr_stdint + 8-bit signed type. */ + +typedef signed char int8_t; + +/** \ingroup avr_stdint + 8-bit unsigned type. */ + +typedef unsigned char uint8_t; + +/** \ingroup avr_stdint + 16-bit signed type. */ + +typedef signed int int16_t; + +/** \ingroup avr_stdint + 16-bit unsigned type. */ + +typedef unsigned int uint16_t; + +/** \ingroup avr_stdint + 32-bit signed type. */ + +typedef signed long int int32_t; + +/** \ingroup avr_stdint + 32-bit unsigned type. */ + +typedef unsigned long int uint32_t; + +/** \ingroup avr_stdint + 64-bit signed type. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef signed long long int int64_t; + +/** \ingroup avr_stdint + 64-bit unsigned type. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef unsigned long long int uint64_t; + +/*@}*/ + +#else /* !defined(__DOXYGEN__) */ + +/* actual implementation goes here */ + +typedef signed int int8_t __attribute__((__mode__(__QI__))); +typedef unsigned int uint8_t __attribute__((__mode__(__QI__))); +typedef signed int int16_t __attribute__ ((__mode__ (__HI__))); +typedef unsigned int uint16_t __attribute__ ((__mode__ (__HI__))); +typedef signed int int32_t __attribute__ ((__mode__ (__SI__))); +typedef unsigned int uint32_t __attribute__ ((__mode__ (__SI__))); +#if !__USING_MINT8 +typedef signed int int64_t __attribute__((__mode__(__DI__))); +typedef unsigned int uint64_t __attribute__((__mode__(__DI__))); +#endif + +#endif /* defined(__DOXYGEN__) */ + +/** \name Integer types capable of holding object pointers + These allow you to declare variables of the same size as a pointer. */ + +/*@{*/ + +/** \ingroup avr_stdint + Signed pointer compatible type. */ + +typedef int16_t intptr_t; + +/** \ingroup avr_stdint + Unsigned pointer compatible type. */ + +typedef uint16_t uintptr_t; + +/*@}*/ + +/** \name Minimum-width integer types + Integer types having at least the specified width */ + +/*@{*/ + +/** \ingroup avr_stdint + signed int with at least 8 bits. */ + +typedef int8_t int_least8_t; + +/** \ingroup avr_stdint + unsigned int with at least 8 bits. */ + +typedef uint8_t uint_least8_t; + +/** \ingroup avr_stdint + signed int with at least 16 bits. */ + +typedef int16_t int_least16_t; + +/** \ingroup avr_stdint + unsigned int with at least 16 bits. */ + +typedef uint16_t uint_least16_t; + +/** \ingroup avr_stdint + signed int with at least 32 bits. */ + +typedef int32_t int_least32_t; + +/** \ingroup avr_stdint + unsigned int with at least 32 bits. */ + +typedef uint32_t uint_least32_t; + +#if !__USING_MINT8 || defined(__DOXYGEN__) +/** \ingroup avr_stdint + signed int with at least 64 bits. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef int64_t int_least64_t; + +/** \ingroup avr_stdint + unsigned int with at least 64 bits. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef uint64_t uint_least64_t; +#endif + +/*@}*/ + + +/** \name Fastest minimum-width integer types + Integer types being usually fastest having at least the specified width */ + +/*@{*/ + +/** \ingroup avr_stdint + fastest signed int with at least 8 bits. */ + +typedef int8_t int_fast8_t; + +/** \ingroup avr_stdint + fastest unsigned int with at least 8 bits. */ + +typedef uint8_t uint_fast8_t; + +/** \ingroup avr_stdint + fastest signed int with at least 16 bits. */ + +typedef int16_t int_fast16_t; + +/** \ingroup avr_stdint + fastest unsigned int with at least 16 bits. */ + +typedef uint16_t uint_fast16_t; + +/** \ingroup avr_stdint + fastest signed int with at least 32 bits. */ + +typedef int32_t int_fast32_t; + +/** \ingroup avr_stdint + fastest unsigned int with at least 32 bits. */ + +typedef uint32_t uint_fast32_t; + +#if !__USING_MINT8 || defined(__DOXYGEN__) +/** \ingroup avr_stdint + fastest signed int with at least 64 bits. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef int64_t int_fast64_t; + +/** \ingroup avr_stdint + fastest unsigned int with at least 64 bits. + \note This type is not available when the compiler + option -mint8 is in effect. */ + +typedef uint64_t uint_fast64_t; +#endif + +/*@}*/ + + +/** \name Greatest-width integer types + Types designating integer data capable of representing any value of + any integer type in the corresponding signed or unsigned category */ + +/*@{*/ + +#if __USING_MINT8 +typedef int32_t intmax_t; + +typedef uint32_t uintmax_t; +#else /* !__USING_MINT8 */ +/** \ingroup avr_stdint + largest signed int available. */ + +typedef int64_t intmax_t; + +/** \ingroup avr_stdint + largest unsigned int available. */ + +typedef uint64_t uintmax_t; +#endif /* __USING_MINT8 */ + +/*@}*/ + +#ifndef __DOXYGEN__ +/* Helping macro */ +#ifndef __CONCAT +#define __CONCATenate(left, right) left ## right +#define __CONCAT(left, right) __CONCATenate(left, right) +#endif + +#endif /* !__DOXYGEN__ */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/** \name Limits of specified-width integer types + C++ implementations should define these macros only when + __STDC_LIMIT_MACROS is defined before is included */ + +/*@{*/ + +/** \ingroup avr_stdint + largest positive value an int8_t can hold. */ + +#define INT8_MAX 0x7f + +/** \ingroup avr_stdint + smallest negative value an int8_t can hold. */ + +#define INT8_MIN (-INT8_MAX - 1) + +#if __USING_MINT8 + +#define UINT8_MAX (__CONCAT(INT8_MAX, U) * 2U + 1U) + +#define INT16_MAX 0x7fffL +#define INT16_MIN (-INT16_MAX - 1L) +#define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2UL + 1UL) + +#define INT32_MAX 0x7fffffffLL +#define INT32_MIN (-INT32_MAX - 1LL) +#define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2ULL + 1ULL) + +#else /* !__USING_MINT8 */ + +/** \ingroup avr_stdint + largest value an uint8_t can hold. */ + +#define UINT8_MAX (INT8_MAX * 2 + 1) + +/** \ingroup avr_stdint + largest positive value an int16_t can hold. */ + +#define INT16_MAX 0x7fff + +/** \ingroup avr_stdint + smallest negative value an int16_t can hold. */ + +#define INT16_MIN (-INT16_MAX - 1) + +/** \ingroup avr_stdint + largest value an uint16_t can hold. */ + +#define UINT16_MAX (__CONCAT(INT16_MAX, U) * 2U + 1U) + +/** \ingroup avr_stdint + largest positive value an int32_t can hold. */ + +#define INT32_MAX 0x7fffffffL + +/** \ingroup avr_stdint + smallest negative value an int32_t can hold. */ + +#define INT32_MIN (-INT32_MAX - 1L) + +/** \ingroup avr_stdint + largest value an uint32_t can hold. */ + +#define UINT32_MAX (__CONCAT(INT32_MAX, U) * 2UL + 1UL) + +#endif /* __USING_MINT8 */ + +/** \ingroup avr_stdint + largest positive value an int64_t can hold. */ + +#define INT64_MAX 0x7fffffffffffffffLL + +/** \ingroup avr_stdint + smallest negative value an int64_t can hold. */ + +#define INT64_MIN (-INT64_MAX - 1LL) + +/** \ingroup avr_stdint + largest value an uint64_t can hold. */ + +#define UINT64_MAX (__CONCAT(INT64_MAX, U) * 2ULL + 1ULL) + +/*@}*/ + +/** \name Limits of minimum-width integer types */ +/*@{*/ + +/** \ingroup avr_stdint + largest positive value an int_least8_t can hold. */ + +#define INT_LEAST8_MAX INT8_MAX + +/** \ingroup avr_stdint + smallest negative value an int_least8_t can hold. */ + +#define INT_LEAST8_MIN INT8_MIN + +/** \ingroup avr_stdint + largest value an uint_least8_t can hold. */ + +#define UINT_LEAST8_MAX UINT8_MAX + +/** \ingroup avr_stdint + largest positive value an int_least16_t can hold. */ + +#define INT_LEAST16_MAX INT16_MAX + +/** \ingroup avr_stdint + smallest negative value an int_least16_t can hold. */ + +#define INT_LEAST16_MIN INT16_MIN + +/** \ingroup avr_stdint + largest value an uint_least16_t can hold. */ + +#define UINT_LEAST16_MAX UINT16_MAX + +/** \ingroup avr_stdint + largest positive value an int_least32_t can hold. */ + +#define INT_LEAST32_MAX INT32_MAX + +/** \ingroup avr_stdint + smallest negative value an int_least32_t can hold. */ + +#define INT_LEAST32_MIN INT32_MIN + +/** \ingroup avr_stdint + largest value an uint_least32_t can hold. */ + +#define UINT_LEAST32_MAX UINT32_MAX + +/** \ingroup avr_stdint + largest positive value an int_least64_t can hold. */ + +#define INT_LEAST64_MAX INT64_MAX + +/** \ingroup avr_stdint + smallest negative value an int_least64_t can hold. */ + +#define INT_LEAST64_MIN INT64_MIN + +/** \ingroup avr_stdint + largest value an uint_least64_t can hold. */ + +#define UINT_LEAST64_MAX UINT64_MAX + +/*@}*/ + +/** \name Limits of fastest minimum-width integer types */ + +/*@{*/ + +/** \ingroup avr_stdint + largest positive value an int_fast8_t can hold. */ + +#define INT_FAST8_MAX INT8_MAX + +/** \ingroup avr_stdint + smallest negative value an int_fast8_t can hold. */ + +#define INT_FAST8_MIN INT8_MIN + +/** \ingroup avr_stdint + largest value an uint_fast8_t can hold. */ + +#define UINT_FAST8_MAX UINT8_MAX + +/** \ingroup avr_stdint + largest positive value an int_fast16_t can hold. */ + +#define INT_FAST16_MAX INT16_MAX + +/** \ingroup avr_stdint + smallest negative value an int_fast16_t can hold. */ + +#define INT_FAST16_MIN INT16_MIN + +/** \ingroup avr_stdint + largest value an uint_fast16_t can hold. */ + +#define UINT_FAST16_MAX UINT16_MAX + +/** \ingroup avr_stdint + largest positive value an int_fast32_t can hold. */ + +#define INT_FAST32_MAX INT32_MAX + +/** \ingroup avr_stdint + smallest negative value an int_fast32_t can hold. */ + +#define INT_FAST32_MIN INT32_MIN + +/** \ingroup avr_stdint + largest value an uint_fast32_t can hold. */ + +#define UINT_FAST32_MAX UINT32_MAX + +/** \ingroup avr_stdint + largest positive value an int_fast64_t can hold. */ + +#define INT_FAST64_MAX INT64_MAX + +/** \ingroup avr_stdint + smallest negative value an int_fast64_t can hold. */ + +#define INT_FAST64_MIN INT64_MIN + +/** \ingroup avr_stdint + largest value an uint_fast64_t can hold. */ + +#define UINT_FAST64_MAX UINT64_MAX + +/*@}*/ + +/** \name Limits of integer types capable of holding object pointers */ + +/*@{*/ + +/** \ingroup avr_stdint + largest positive value an intptr_t can hold. */ + +#define INTPTR_MAX INT16_MAX + +/** \ingroup avr_stdint + smallest negative value an intptr_t can hold. */ + +#define INTPTR_MIN INT16_MIN + +/** \ingroup avr_stdint + largest value an uintptr_t can hold. */ + +#define UINTPTR_MAX UINT16_MAX + +/*@}*/ + +/** \name Limits of greatest-width integer types */ + +/*@{*/ + +/** \ingroup avr_stdint + largest positive value an intmax_t can hold. */ + +#define INTMAX_MAX INT64_MAX + +/** \ingroup avr_stdint + smallest negative value an intmax_t can hold. */ + +#define INTMAX_MIN INT64_MIN + +/** \ingroup avr_stdint + largest value an uintmax_t can hold. */ + +#define UINTMAX_MAX UINT64_MAX + +/*@}*/ + +/** \name Limits of other integer types + C++ implementations should define these macros only when + __STDC_LIMIT_MACROS is defined before is included */ + +/*@{*/ + +/** \ingroup avr_stdint + largest positive value a ptrdiff_t can hold. */ + +#define PTRDIFF_MAX INT16_MAX + +/** \ingroup avr_stdint + smallest negative value a ptrdiff_t can hold. */ + +#define PTRDIFF_MIN INT16_MIN + + +/* Limits of sig_atomic_t */ +/* signal.h is currently not implemented (not avr/signal.h) */ + +/** \ingroup avr_stdint + largest positive value a sig_atomic_t can hold. */ + +#define SIG_ATOMIC_MAX INT8_MAX + +/** \ingroup avr_stdint + smallest negative value a sig_atomic_t can hold. */ + +#define SIG_ATOMIC_MIN INT8_MIN + + +/** \ingroup avr_stdint + largest value a size_t can hold. */ + +#define SIZE_MAX UINT16_MAX + + +/* Limits of wchar_t */ +/* wchar.h is currently not implemented */ +/* #define WCHAR_MAX */ +/* #define WCHAR_MIN */ + + +/* Limits of wint_t */ +/* wchar.h is currently not implemented */ +#ifndef WCHAR_MAX +#define WCHAR_MAX __WCHAR_MAX__ +#define WCHAR_MIN __WCHAR_MIN__ +#endif +#ifndef WINT_MAX +#define WINT_MAX __WINT_MAX__ +#define WINT_MIN __WINT_MIN__ +#endif + + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#if (!defined __cplusplus || __cplusplus >= 201103L \ + || defined __STDC_CONSTANT_MACROS) + +/** \name Macros for integer constants + C++ implementations should define these macros only when + __STDC_CONSTANT_MACROS is defined before is included. + + These definitions are valid for integer constants without suffix and + for macros defined as integer constant without suffix */ + +/* The GNU C preprocessor defines special macros in the implementation + namespace to allow a definition that works in #if expressions. */ +#ifdef __INT8_C +#define INT8_C(c) __INT8_C(c) +#define INT16_C(c) __INT16_C(c) +#define INT32_C(c) __INT32_C(c) +#define INT64_C(c) __INT64_C(c) +#define UINT8_C(c) __UINT8_C(c) +#define UINT16_C(c) __UINT16_C(c) +#define UINT32_C(c) __UINT32_C(c) +#define UINT64_C(c) __UINT64_C(c) +#define INTMAX_C(c) __INTMAX_C(c) +#define UINTMAX_C(c) __UINTMAX_C(c) +#else +/** \ingroup avr_stdint + define a constant of type int8_t */ + +#define INT8_C(value) ((int8_t) value) + +/** \ingroup avr_stdint + define a constant of type uint8_t */ + +#define UINT8_C(value) ((uint8_t) __CONCAT(value, U)) + +#if __USING_MINT8 + +#define INT16_C(value) __CONCAT(value, L) +#define UINT16_C(value) __CONCAT(value, UL) + +#define INT32_C(value) ((int32_t) __CONCAT(value, LL)) +#define UINT32_C(value) ((uint32_t) __CONCAT(value, ULL)) + +#else /* !__USING_MINT8 */ + +/** \ingroup avr_stdint + define a constant of type int16_t */ + +#define INT16_C(value) value + +/** \ingroup avr_stdint + define a constant of type uint16_t */ + +#define UINT16_C(value) __CONCAT(value, U) + +/** \ingroup avr_stdint + define a constant of type int32_t */ + +#define INT32_C(value) __CONCAT(value, L) + +/** \ingroup avr_stdint + define a constant of type uint32_t */ + +#define UINT32_C(value) __CONCAT(value, UL) + +#endif /* __USING_MINT8 */ + +/** \ingroup avr_stdint + define a constant of type int64_t */ + +#define INT64_C(value) __CONCAT(value, LL) + +/** \ingroup avr_stdint + define a constant of type uint64_t */ + +#define UINT64_C(value) __CONCAT(value, ULL) + +/** \ingroup avr_stdint + define a constant of type intmax_t */ + +#define INTMAX_C(value) __CONCAT(value, LL) + +/** \ingroup avr_stdint + define a constant of type uintmax_t */ + +#define UINTMAX_C(value) __CONCAT(value, ULL) + +#endif /* !__INT8_C */ + +/*@}*/ + +#endif /* (!defined __cplusplus || __cplusplus >= 201103L \ + || defined __STDC_CONSTANT_MACROS) */ + + +#endif /* _STDINT_H_ */ diff --git a/hardware/tools/avr/avr/include/stdio.h b/hardware/tools/avr/avr/include/stdio.h new file mode 100644 index 0000000000000000000000000000000000000000..9c2c2f662078879732e062b0f39cc18b5f6beb7a --- /dev/null +++ b/hardware/tools/avr/avr/include/stdio.h @@ -0,0 +1,989 @@ +/* Copyright (c) 2002, 2005, 2007 Joerg Wunsch + All rights reserved. + + Portions of documentation Copyright (c) 1990, 1991, 1993 + The Regents of the University of California. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + $Id$ +*/ + +#ifndef _STDIO_H_ +#define _STDIO_H_ 1 + +#ifndef __ASSEMBLER__ + +#include +#include + +#ifndef __DOXYGEN__ +#define __need_NULL +#define __need_size_t +#include +#endif /* !__DOXYGEN__ */ + +/** \file */ +/** \defgroup avr_stdio : Standard IO facilities + \code #include \endcode + +

Introduction to the Standard IO facilities

+ + This file declares the standard IO facilities that are implemented + in \c avr-libc. Due to the nature of the underlying hardware, + only a limited subset of standard IO is implemented. There is no + actual file implementation available, so only device IO can be + performed. Since there's no operating system, the application + needs to provide enough details about their devices in order to + make them usable by the standard IO facilities. + + Due to space constraints, some functionality has not been + implemented at all (like some of the \c printf conversions that + have been left out). Nevertheless, potential users of this + implementation should be warned: the \c printf and \c scanf families of functions, although + usually associated with presumably simple things like the + famous "Hello, world!" program, are actually fairly complex + which causes their inclusion to eat up a fair amount of code space. + Also, they are not fast due to the nature of interpreting the + format string at run-time. Whenever possible, resorting to the + (sometimes non-standard) predetermined conversion facilities that are + offered by avr-libc will usually cost much less in terms of speed + and code size. + +

Tunable options for code size vs. feature set

+ + In order to allow programmers a code size vs. functionality tradeoff, + the function vfprintf() which is the heart of the printf family can be + selected in different flavours using linker options. See the + documentation of vfprintf() for a detailed description. The same + applies to vfscanf() and the \c scanf family of functions. + +

Outline of the chosen API

+ + The standard streams \c stdin, \c stdout, and \c stderr are + provided, but contrary to the C standard, since avr-libc has no + knowledge about applicable devices, these streams are not already + pre-initialized at application startup. Also, since there is no + notion of "file" whatsoever to avr-libc, there is no function + \c fopen() that could be used to associate a stream to some device. + (See \ref stdio_note1 "note 1".) Instead, the function \c fdevopen() + is provided to associate a stream to a device, where the device + needs to provide a function to send a character, to receive a + character, or both. There is no differentiation between "text" and + "binary" streams inside avr-libc. Character \c \\n is sent + literally down to the device's \c put() function. If the device + requires a carriage return (\c \\r) character to be sent before + the linefeed, its \c put() routine must implement this (see + \ref stdio_note2 "note 2"). + + As an alternative method to fdevopen(), the macro + fdev_setup_stream() might be used to setup a user-supplied FILE + structure. + + It should be noted that the automatic conversion of a newline + character into a carriage return - newline sequence breaks binary + transfers. If binary transfers are desired, no automatic + conversion should be performed, but instead any string that aims + to issue a CR-LF sequence must use "\r\n" explicitly. + + For convenience, the first call to \c fdevopen() that opens a + stream for reading will cause the resulting stream to be aliased + to \c stdin. Likewise, the first call to \c fdevopen() that opens + a stream for writing will cause the resulting stream to be aliased + to both, \c stdout, and \c stderr. Thus, if the open was done + with both, read and write intent, all three standard streams will + be identical. Note that these aliases are indistinguishable from + each other, thus calling \c fclose() on such a stream will also + effectively close all of its aliases (\ref stdio_note3 "note 3"). + + It is possible to tie additional user data to a stream, using + fdev_set_udata(). The backend put and get functions can then + extract this user data using fdev_get_udata(), and act + appropriately. For example, a single put function could be used + to talk to two different UARTs that way, or the put and get + functions could keep internal state between calls there. + +

Format strings in flash ROM

+ + All the \c printf and \c scanf family functions come in two flavours: the + standard name, where the format string is expected to be in + SRAM, as well as a version with the suffix "_P" where the format + string is expected to reside in the flash ROM. The macro + \c PSTR (explained in \ref avr_pgmspace) becomes very handy + for declaring these format strings. + + \anchor stdio_without_malloc +

Running stdio without malloc()

+ + By default, fdevopen() requires malloc(). As this is often + not desired in the limited environment of a microcontroller, an + alternative option is provided to run completely without malloc(). + + The macro fdev_setup_stream() is provided to prepare a + user-supplied FILE buffer for operation with stdio. + +

Example

+ + \code + #include + + static int uart_putchar(char c, FILE *stream); + + static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL, + _FDEV_SETUP_WRITE); + + static int + uart_putchar(char c, FILE *stream) + { + + if (c == '\n') + uart_putchar('\r', stream); + loop_until_bit_is_set(UCSRA, UDRE); + UDR = c; + return 0; + } + + int + main(void) + { + init_uart(); + stdout = &mystdout; + printf("Hello, world!\n"); + + return 0; + } + \endcode + + This example uses the initializer form FDEV_SETUP_STREAM() rather + than the function-like fdev_setup_stream(), so all data + initialization happens during C start-up. + + If streams initialized that way are no longer needed, they can be + destroyed by first calling the macro fdev_close(), and then + destroying the object itself. No call to fclose() should be + issued for these streams. While calling fclose() itself is + harmless, it will cause an undefined reference to free() and thus + cause the linker to link the malloc module into the application. + +

Notes

+ + \anchor stdio_note1 \par Note 1: + It might have been possible to implement a device abstraction that + is compatible with \c fopen() but since this would have required + to parse a string, and to take all the information needed either + out of this string, or out of an additional table that would need to be + provided by the application, this approach was not taken. + + \anchor stdio_note2 \par Note 2: + This basically follows the Unix approach: if a device such as a + terminal needs special handling, it is in the domain of the + terminal device driver to provide this functionality. Thus, a + simple function suitable as \c put() for \c fdevopen() that talks + to a UART interface might look like this: + + \code + int + uart_putchar(char c, FILE *stream) + { + + if (c == '\n') + uart_putchar('\r'); + loop_until_bit_is_set(UCSRA, UDRE); + UDR = c; + return 0; + } + \endcode + + \anchor stdio_note3 \par Note 3: + This implementation has been chosen because the cost of maintaining + an alias is considerably smaller than the cost of maintaining full + copies of each stream. Yet, providing an implementation that offers + the complete set of standard streams was deemed to be useful. Not + only that writing \c printf() instead of fprintf(mystream, ...) + saves typing work, but since avr-gcc needs to resort to pass all + arguments of variadic functions on the stack (as opposed to passing + them in registers for functions that take a fixed number of + parameters), the ability to pass one parameter less by implying + \c stdin or stdout will also save some execution time. +*/ + +#if !defined(__DOXYGEN__) + +/* + * This is an internal structure of the library that is subject to be + * changed without warnings at any time. Please do *never* reference + * elements of it beyond by using the official interfaces provided. + */ +struct __file { + char *buf; /* buffer pointer */ + unsigned char unget; /* ungetc() buffer */ + uint8_t flags; /* flags, see below */ +#define __SRD 0x0001 /* OK to read */ +#define __SWR 0x0002 /* OK to write */ +#define __SSTR 0x0004 /* this is an sprintf/snprintf string */ +#define __SPGM 0x0008 /* fmt string is in progmem */ +#define __SERR 0x0010 /* found error */ +#define __SEOF 0x0020 /* found EOF */ +#define __SUNGET 0x040 /* ungetc() happened */ +#define __SMALLOC 0x80 /* handle is malloc()ed */ +#if 0 +/* possible future extensions, will require uint16_t flags */ +#define __SRW 0x0100 /* open for reading & writing */ +#define __SLBF 0x0200 /* line buffered */ +#define __SNBF 0x0400 /* unbuffered */ +#define __SMBF 0x0800 /* buf is from malloc */ +#endif + int size; /* size of buffer */ + int len; /* characters read or written so far */ + int (*put)(char, struct __file *); /* function to write one char to device */ + int (*get)(struct __file *); /* function to read one char from device */ + void *udata; /* User defined and accessible data. */ +}; + +#endif /* not __DOXYGEN__ */ + +/*@{*/ +/** + \c FILE is the opaque structure that is passed around between the + various standard IO functions. +*/ +typedef struct __file FILE; + +/** + Stream that will be used as an input stream by the simplified + functions that don't take a \c stream argument. + + The first stream opened with read intent using \c fdevopen() + will be assigned to \c stdin. +*/ +#define stdin (__iob[0]) + +/** + Stream that will be used as an output stream by the simplified + functions that don't take a \c stream argument. + + The first stream opened with write intent using \c fdevopen() + will be assigned to both, \c stdin, and \c stderr. +*/ +#define stdout (__iob[1]) + +/** + Stream destined for error output. Unless specifically assigned, + identical to \c stdout. + + If \c stderr should point to another stream, the result of + another \c fdevopen() must be explicitly assigned to it without + closing the previous \c stderr (since this would also close + \c stdout). +*/ +#define stderr (__iob[2]) + +/** + \c EOF declares the value that is returned by various standard IO + functions in case of an error. Since the AVR platform (currently) + doesn't contain an abstraction for actual files, its origin as + "end of file" is somewhat meaningless here. +*/ +#define EOF (-1) + +/** This macro inserts a pointer to user defined data into a FILE + stream object. + + The user data can be useful for tracking state in the put and get + functions supplied to the fdevopen() function. */ +#define fdev_set_udata(stream, u) do { (stream)->udata = u; } while(0) + +/** This macro retrieves a pointer to user defined data from a FILE + stream object. */ +#define fdev_get_udata(stream) ((stream)->udata) + +#if defined(__DOXYGEN__) +/** + \brief Setup a user-supplied buffer as an stdio stream + + This macro takes a user-supplied buffer \c stream, and sets it up + as a stream that is valid for stdio operations, similar to one that + has been obtained dynamically from fdevopen(). The buffer to setup + must be of type FILE. + + The arguments \c put and \c get are identical to those that need to + be passed to fdevopen(). + + The \c rwflag argument can take one of the values _FDEV_SETUP_READ, + _FDEV_SETUP_WRITE, or _FDEV_SETUP_RW, for read, write, or read/write + intent, respectively. + + \note No assignments to the standard streams will be performed by + fdev_setup_stream(). If standard streams are to be used, these + need to be assigned by the user. See also under + \ref stdio_without_malloc "Running stdio without malloc()". + */ +#define fdev_setup_stream(stream, put, get, rwflag) +#else /* !DOXYGEN */ +#define fdev_setup_stream(stream, p, g, f) \ + do { \ + (stream)->put = p; \ + (stream)->get = g; \ + (stream)->flags = f; \ + (stream)->udata = 0; \ + } while(0) +#endif /* DOXYGEN */ + +#define _FDEV_SETUP_READ __SRD /**< fdev_setup_stream() with read intent */ +#define _FDEV_SETUP_WRITE __SWR /**< fdev_setup_stream() with write intent */ +#define _FDEV_SETUP_RW (__SRD|__SWR) /**< fdev_setup_stream() with read/write intent */ + +/** + * Return code for an error condition during device read. + * + * To be used in the get function of fdevopen(). + */ +#define _FDEV_ERR (-1) + +/** + * Return code for an end-of-file condition during device read. + * + * To be used in the get function of fdevopen(). + */ +#define _FDEV_EOF (-2) + +#if defined(__DOXYGEN__) +/** + \brief Initializer for a user-supplied stdio stream + + This macro acts similar to fdev_setup_stream(), but it is to be + used as the initializer of a variable of type FILE. + + The remaining arguments are to be used as explained in + fdev_setup_stream(). + */ +#define FDEV_SETUP_STREAM(put, get, rwflag) +#else /* !DOXYGEN */ +#define FDEV_SETUP_STREAM(p, g, f) \ + { \ + .put = p, \ + .get = g, \ + .flags = f, \ + .udata = 0, \ + } +#endif /* DOXYGEN */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__DOXYGEN__) +/* + * Doxygen documentation can be found in fdevopen.c. + */ + +extern struct __file *__iob[]; + +#if defined(__STDIO_FDEVOPEN_COMPAT_12) +/* + * Declare prototype for the discontinued version of fdevopen() that + * has been in use up to avr-libc 1.2.x. The new implementation has + * some backwards compatibility with the old version. + */ +extern FILE *fdevopen(int (*__put)(char), int (*__get)(void), + int __opts __attribute__((unused))); +#else /* !defined(__STDIO_FDEVOPEN_COMPAT_12) */ +/* New prototype for avr-libc 1.4 and above. */ +extern FILE *fdevopen(int (*__put)(char, FILE*), int (*__get)(FILE*)); +#endif /* defined(__STDIO_FDEVOPEN_COMPAT_12) */ + +#endif /* not __DOXYGEN__ */ + +/** + This function closes \c stream, and disallows and further + IO to and from it. + + When using fdevopen() to setup the stream, a call to fclose() is + needed in order to free the internal resources allocated. + + If the stream has been set up using fdev_setup_stream() or + FDEV_SETUP_STREAM(), use fdev_close() instead. + + It currently always returns 0 (for success). +*/ +extern int fclose(FILE *__stream); + +/** + This macro frees up any library resources that might be associated + with \c stream. It should be called if \c stream is no longer + needed, right before the application is going to destroy the + \c stream object itself. + + (Currently, this macro evaluates to nothing, but this might change + in future versions of the library.) +*/ +#if defined(__DOXYGEN__) +# define fdev_close() +#else +# define fdev_close() ((void)0) +#endif + +/** + \c vfprintf is the central facility of the \c printf family of + functions. It outputs values to \c stream under control of a + format string passed in \c fmt. The actual values to print are + passed as a variable argument list \c ap. + + \c vfprintf returns the number of characters written to \c stream, + or \c EOF in case of an error. Currently, this will only happen + if \c stream has not been opened with write intent. + + The format string is composed of zero or more directives: ordinary + characters (not \c %), which are copied unchanged to the output + stream; and conversion specifications, each of which results in + fetching zero or more subsequent arguments. Each conversion + specification is introduced by the \c % character. The arguments must + properly correspond (after type promotion) with the conversion + specifier. After the \c %, the following appear in sequence: + + - Zero or more of the following flags: +
    +
  • \c # The value should be converted to an "alternate form". For + c, d, i, s, and u conversions, this option has no effect. + For o conversions, the precision of the number is + increased to force the first character of the output + string to a zero (except if a zero value is printed with + an explicit precision of zero). For x and X conversions, + a non-zero result has the string `0x' (or `0X' for X + conversions) prepended to it.
    • +
  • \c 0 (zero) Zero padding. For all conversions, the converted + value is padded on the left with zeros rather than blanks. + If a precision is given with a numeric conversion (d, i, + o, u, i, x, and X), the 0 flag is ignored.
    • +
  • \c - A negative field width flag; the converted value is to be + left adjusted on the field boundary. The converted value + is padded on the right with blanks, rather than on the + left with blanks or zeros. A - overrides a 0 if both are + given.
    • +
  • ' ' (space) A blank should be left before a positive number + produced by a signed conversion (d, or i).
    • +
  • \c + A sign must always be placed before a number produced by a + signed conversion. A + overrides a space if both are + used.
    • +
+ + - An optional decimal digit string specifying a minimum field width. + If the converted value has fewer characters than the field width, it + will be padded with spaces on the left (or right, if the left-adjustment + flag has been given) to fill out the field width. + - An optional precision, in the form of a period . followed by an + optional digit string. If the digit string is omitted, the + precision is taken as zero. This gives the minimum number of + digits to appear for d, i, o, u, x, and X conversions, or the + maximum number of characters to be printed from a string for \c s + conversions. + - An optional \c l or \c h length modifier, that specifies that the + argument for the d, i, o, u, x, or X conversion is a \c "long int" + rather than \c int. The \c h is ignored, as \c "short int" is + equivalent to \c int. + - A character that specifies the type of conversion to be applied. + + The conversion specifiers and their meanings are: + + - \c diouxX The int (or appropriate variant) argument is converted + to signed decimal (d and i), unsigned octal (o), unsigned + decimal (u), or unsigned hexadecimal (x and X) notation. + The letters "abcdef" are used for x conversions; the + letters "ABCDEF" are used for X conversions. The + precision, if any, gives the minimum number of digits that + must appear; if the converted value requires fewer digits, + it is padded on the left with zeros. + - \c p The void * argument is taken as an unsigned integer, + and converted similarly as a %\#x command would do. + - \c c The \c int argument is converted to an \c "unsigned char", and the + resulting character is written. + - \c s The \c "char *" argument is expected to be a pointer to an array + of character type (pointer to a string). Characters from + the array are written up to (but not including) a + terminating NUL character; if a precision is specified, no + more than the number specified are written. If a precision + is given, no null character need be present; if the + precision is not specified, or is greater than the size of + the array, the array must contain a terminating NUL + character. + - \c % A \c % is written. No argument is converted. The complete + conversion specification is "%%". + - \c eE The double argument is rounded and converted in the format + \c "[-]d.ddde±dd" where there is one digit before the + decimal-point character and the number of digits after it + is equal to the precision; if the precision is missing, it + is taken as 6; if the precision is zero, no decimal-point + character appears. An \e E conversion uses the letter \c 'E' + (rather than \c 'e') to introduce the exponent. The exponent + always contains two digits; if the value is zero, + the exponent is 00. + - \c fF The double argument is rounded and converted to decimal notation + in the format \c "[-]ddd.ddd", where the number of digits after the + decimal-point character is equal to the precision specification. + If the precision is missing, it is taken as 6; if the precision + is explicitly zero, no decimal-point character appears. If a + decimal point appears, at least one digit appears before it. + - \c gG The double argument is converted in style \c f or \c e (or + \c F or \c E for \c G conversions). The precision + specifies the number of significant digits. If the + precision is missing, 6 digits are given; if the precision + is zero, it is treated as 1. Style \c e is used if the + exponent from its conversion is less than -4 or greater + than or equal to the precision. Trailing zeros are removed + from the fractional part of the result; a decimal point + appears only if it is followed by at least one digit. + - \c S Similar to the \c s format, except the pointer is expected to + point to a program-memory (ROM) string instead of a RAM string. + + In no case does a non-existent or small field width cause truncation of a + numeric field; if the result of a conversion is wider than the field + width, the field is expanded to contain the conversion result. + + Since the full implementation of all the mentioned features becomes + fairly large, three different flavours of vfprintf() can be + selected using linker options. The default vfprintf() implements + all the mentioned functionality except floating point conversions. + A minimized version of vfprintf() is available that only implements + the very basic integer and string conversion facilities, but only + the \c # additional option can be specified using conversion + flags (these flags are parsed correctly from the format + specification, but then simply ignored). This version can be + requested using the following \ref gcc_minusW "compiler options": + + \code + -Wl,-u,vfprintf -lprintf_min + \endcode + + If the full functionality including the floating point conversions + is required, the following options should be used: + + \code + -Wl,-u,vfprintf -lprintf_flt -lm + \endcode + + \par Limitations: + - The specified width and precision can be at most 255. + + \par Notes: + - For floating-point conversions, if you link default or minimized + version of vfprintf(), the symbol \c ? will be output and double + argument will be skiped. So you output below will not be crashed. + For default version the width field and the "pad to left" ( symbol + minus ) option will work in this case. + - The \c hh length modifier is ignored (\c char argument is + promouted to \c int). More exactly, this realization does not check + the number of \c h symbols. + - But the \c ll length modifier will to abort the output, as this + realization does not operate \c long \c long arguments. + - The variable width or precision field (an asterisk \c * symbol) + is not realized and will to abort the output. + + */ + +extern int vfprintf(FILE *__stream, const char *__fmt, va_list __ap); + +/** + Variant of \c vfprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int vfprintf_P(FILE *__stream, const char *__fmt, va_list __ap); + +/** + The function \c fputc sends the character \c c (though given as type + \c int) to \c stream. It returns the character, or \c EOF in case + an error occurred. +*/ +extern int fputc(int __c, FILE *__stream); + +#if !defined(__DOXYGEN__) + +/* putc() function implementation, required by standard */ +extern int putc(int __c, FILE *__stream); + +/* putchar() function implementation, required by standard */ +extern int putchar(int __c); + +#endif /* not __DOXYGEN__ */ + +/** + The macro \c putc used to be a "fast" macro implementation with a + functionality identical to fputc(). For space constraints, in + \c avr-libc, it is just an alias for \c fputc. +*/ +#define putc(__c, __stream) fputc(__c, __stream) + +/** + The macro \c putchar sends character \c c to \c stdout. +*/ +#define putchar(__c) fputc(__c, stdout) + +/** + The function \c printf performs formatted output to stream + \c stdout. See \c vfprintf() for details. +*/ +extern int printf(const char *__fmt, ...); + +/** + Variant of \c printf() that uses a \c fmt string that resides + in program memory. +*/ +extern int printf_P(const char *__fmt, ...); + +/** + The function \c vprintf performs formatted output to stream + \c stdout, taking a variable argument list as in vfprintf(). + + See vfprintf() for details. +*/ +extern int vprintf(const char *__fmt, va_list __ap); + +/** + Variant of \c printf() that sends the formatted characters + to string \c s. +*/ +extern int sprintf(char *__s, const char *__fmt, ...); + +/** + Variant of \c sprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int sprintf_P(char *__s, const char *__fmt, ...); + +/** + Like \c sprintf(), but instead of assuming \c s to be of infinite + size, no more than \c n characters (including the trailing NUL + character) will be converted to \c s. + + Returns the number of characters that would have been written to + \c s if there were enough space. +*/ +extern int snprintf(char *__s, size_t __n, const char *__fmt, ...); + +/** + Variant of \c snprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int snprintf_P(char *__s, size_t __n, const char *__fmt, ...); + +/** + Like \c sprintf() but takes a variable argument list for the + arguments. +*/ +extern int vsprintf(char *__s, const char *__fmt, va_list ap); + +/** + Variant of \c vsprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int vsprintf_P(char *__s, const char *__fmt, va_list ap); + +/** + Like \c vsprintf(), but instead of assuming \c s to be of infinite + size, no more than \c n characters (including the trailing NUL + character) will be converted to \c s. + + Returns the number of characters that would have been written to + \c s if there were enough space. +*/ +extern int vsnprintf(char *__s, size_t __n, const char *__fmt, va_list ap); + +/** + Variant of \c vsnprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int vsnprintf_P(char *__s, size_t __n, const char *__fmt, va_list ap); +/** + The function \c fprintf performs formatted output to \c stream. + See \c vfprintf() for details. +*/ +extern int fprintf(FILE *__stream, const char *__fmt, ...); + +/** + Variant of \c fprintf() that uses a \c fmt string that resides + in program memory. +*/ +extern int fprintf_P(FILE *__stream, const char *__fmt, ...); + +/** + Write the string pointed to by \c str to stream \c stream. + + Returns 0 on success and EOF on error. +*/ +extern int fputs(const char *__str, FILE *__stream); + +/** + Variant of fputs() where \c str resides in program memory. +*/ +extern int fputs_P(const char *__str, FILE *__stream); + +/** + Write the string pointed to by \c str, and a trailing newline + character, to \c stdout. +*/ +extern int puts(const char *__str); + +/** + Variant of puts() where \c str resides in program memory. +*/ +extern int puts_P(const char *__str); + +/** + Write \c nmemb objects, \c size bytes each, to \c stream. + The first byte of the first object is referenced by \c ptr. + + Returns the number of objects successfully written, i. e. + \c nmemb unless an output error occured. + */ +extern size_t fwrite(const void *__ptr, size_t __size, size_t __nmemb, + FILE *__stream); + +/** + The function \c fgetc reads a character from \c stream. It returns + the character, or \c EOF in case end-of-file was encountered or an + error occurred. The routines feof() or ferror() must be used to + distinguish between both situations. +*/ +extern int fgetc(FILE *__stream); + +#if !defined(__DOXYGEN__) + +/* getc() function implementation, required by standard */ +extern int getc(FILE *__stream); + +/* getchar() function implementation, required by standard */ +extern int getchar(void); + +#endif /* not __DOXYGEN__ */ + +/** + The macro \c getc used to be a "fast" macro implementation with a + functionality identical to fgetc(). For space constraints, in + \c avr-libc, it is just an alias for \c fgetc. +*/ +#define getc(__stream) fgetc(__stream) + +/** + The macro \c getchar reads a character from \c stdin. Return + values and error handling is identical to fgetc(). +*/ +#define getchar() fgetc(stdin) + +/** + The ungetc() function pushes the character \c c (converted to an + unsigned char) back onto the input stream pointed to by \c stream. + The pushed-back character will be returned by a subsequent read on + the stream. + + Currently, only a single character can be pushed back onto the + stream. + + The ungetc() function returns the character pushed back after the + conversion, or \c EOF if the operation fails. If the value of the + argument \c c character equals \c EOF, the operation will fail and + the stream will remain unchanged. +*/ +extern int ungetc(int __c, FILE *__stream); + +/** + Read at most size - 1 bytes from \c stream, until a + newline character was encountered, and store the characters in the + buffer pointed to by \c str. Unless an error was encountered while + reading, the string will then be terminated with a \c NUL + character. + + If an error was encountered, the function returns NULL and sets the + error flag of \c stream, which can be tested using ferror(). + Otherwise, a pointer to the string will be returned. */ +extern char *fgets(char *__str, int __size, FILE *__stream); + +/** + Similar to fgets() except that it will operate on stream \c stdin, + and the trailing newline (if any) will not be stored in the string. + It is the caller's responsibility to provide enough storage to hold + the characters read. */ +extern char *gets(char *__str); + +/** + Read \c nmemb objects, \c size bytes each, from \c stream, + to the buffer pointed to by \c ptr. + + Returns the number of objects successfully read, i. e. + \c nmemb unless an input error occured or end-of-file was + encountered. feof() and ferror() must be used to distinguish + between these two conditions. + */ +extern size_t fread(void *__ptr, size_t __size, size_t __nmemb, + FILE *__stream); + +/** + Clear the error and end-of-file flags of \c stream. + */ +extern void clearerr(FILE *__stream); + +#if !defined(__DOXYGEN__) +/* fast inlined version of clearerr() */ +#define clearerror(s) do { (s)->flags &= ~(__SERR | __SEOF); } while(0) +#endif /* !defined(__DOXYGEN__) */ + +/** + Test the end-of-file flag of \c stream. This flag can only be cleared + by a call to clearerr(). + */ +extern int feof(FILE *__stream); + +#if !defined(__DOXYGEN__) +/* fast inlined version of feof() */ +#define feof(s) ((s)->flags & __SEOF) +#endif /* !defined(__DOXYGEN__) */ + +/** + Test the error flag of \c stream. This flag can only be cleared + by a call to clearerr(). + */ +extern int ferror(FILE *__stream); + +#if !defined(__DOXYGEN__) +/* fast inlined version of ferror() */ +#define ferror(s) ((s)->flags & __SERR) +#endif /* !defined(__DOXYGEN__) */ + +extern int vfscanf(FILE *__stream, const char *__fmt, va_list __ap); + +/** + Variant of vfscanf() using a \c fmt string in program memory. + */ +extern int vfscanf_P(FILE *__stream, const char *__fmt, va_list __ap); + +/** + The function \c fscanf performs formatted input, reading the + input data from \c stream. + + See vfscanf() for details. + */ +extern int fscanf(FILE *__stream, const char *__fmt, ...); + +/** + Variant of fscanf() using a \c fmt string in program memory. + */ +extern int fscanf_P(FILE *__stream, const char *__fmt, ...); + +/** + The function \c scanf performs formatted input from stream \c stdin. + + See vfscanf() for details. + */ +extern int scanf(const char *__fmt, ...); + +/** + Variant of scanf() where \c fmt resides in program memory. + */ +extern int scanf_P(const char *__fmt, ...); + +/** + The function \c vscanf performs formatted input from stream + \c stdin, taking a variable argument list as in vfscanf(). + + See vfscanf() for details. +*/ +extern int vscanf(const char *__fmt, va_list __ap); + +/** + The function \c sscanf performs formatted input, reading the + input data from the buffer pointed to by \c buf. + + See vfscanf() for details. + */ +extern int sscanf(const char *__buf, const char *__fmt, ...); + +/** + Variant of sscanf() using a \c fmt string in program memory. + */ +extern int sscanf_P(const char *__buf, const char *__fmt, ...); + +#if defined(__DOXYGEN__) +/** + Flush \c stream. + + This is a null operation provided for source-code compatibility + only, as the standard IO implementation currently does not perform + any buffering. + */ +extern int fflush(FILE *stream); +#else +static __inline__ int fflush(FILE *stream __attribute__((unused))) +{ + return 0; +} +#endif + +#ifndef __DOXYGEN__ +/* only mentioned for libstdc++ support, not implemented in library */ +#define BUFSIZ 1024 +#define _IONBF 0 +__extension__ typedef long long fpos_t; +extern int fgetpos(FILE *stream, fpos_t *pos); +extern FILE *fopen(const char *path, const char *mode); +extern FILE *freopen(const char *path, const char *mode, FILE *stream); +extern FILE *fdopen(int, const char *); +extern int fseek(FILE *stream, long offset, int whence); +extern int fsetpos(FILE *stream, fpos_t *pos); +extern long ftell(FILE *stream); +extern int fileno(FILE *); +extern void perror(const char *s); +extern int remove(const char *pathname); +extern int rename(const char *oldpath, const char *newpath); +extern void rewind(FILE *stream); +extern void setbuf(FILE *stream, char *buf); +extern int setvbuf(FILE *stream, char *buf, int mode, size_t size); +extern FILE *tmpfile(void); +extern char *tmpnam (char *s); +#endif /* !__DOXYGEN__ */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#ifndef __DOXYGEN__ +/* + * The following constants are currently not used by avr-libc's + * stdio subsystem. They are defined here since the gcc build + * environment expects them to be here. + */ +#define SEEK_SET 0 +#define SEEK_CUR 1 +#define SEEK_END 2 + +#endif + +#endif /* __ASSEMBLER */ + +#endif /* _STDLIB_H_ */ diff --git a/hardware/tools/avr/avr/include/stdlib.h b/hardware/tools/avr/avr/include/stdlib.h new file mode 100644 index 0000000000000000000000000000000000000000..a77f7b3abba9d17e623a9f06035af1e1220a8724 --- /dev/null +++ b/hardware/tools/avr/avr/include/stdlib.h @@ -0,0 +1,696 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + Copyright (c) 2004,2007 Joerg Wunsch + + Portions of documentation Copyright (c) 1990, 1991, 1993, 1994 + The Regents of the University of California. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + $Id$ +*/ + +#ifndef _STDLIB_H_ +#define _STDLIB_H_ 1 + +#ifndef __ASSEMBLER__ + +#ifndef __DOXYGEN__ +#define __need_NULL +#define __need_size_t +#define __need_wchar_t +#include + +#ifndef __ptr_t +#define __ptr_t void * +#endif +#endif /* !__DOXYGEN__ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file */ + +/** \defgroup avr_stdlib : General utilities + \code #include \endcode + + This file declares some basic C macros and functions as + defined by the ISO standard, plus some AVR-specific extensions. +*/ + +/*@{*/ +/** Result type for function div(). */ +typedef struct { + int quot; /**< The Quotient. */ + int rem; /**< The Remainder. */ +} div_t; + +/** Result type for function ldiv(). */ +typedef struct { + long quot; /**< The Quotient. */ + long rem; /**< The Remainder. */ +} ldiv_t; + +/** Comparision function type for qsort(), just for convenience. */ +typedef int (*__compar_fn_t)(const void *, const void *); + +#ifndef __DOXYGEN__ + +#ifndef __ATTR_CONST__ +# define __ATTR_CONST__ __attribute__((__const__)) +#endif + +#ifndef __ATTR_MALLOC__ +# define __ATTR_MALLOC__ __attribute__((__malloc__)) +#endif + +#ifndef __ATTR_NORETURN__ +# define __ATTR_NORETURN__ __attribute__((__noreturn__)) +#endif + +#ifndef __ATTR_PURE__ +# define __ATTR_PURE__ __attribute__((__pure__)) +#endif + +#ifndef __ATTR_GNU_INLINE__ +# ifdef __GNUC_STDC_INLINE__ +# define __ATTR_GNU_INLINE__ __attribute__((__gnu_inline__)) +# else +# define __ATTR_GNU_INLINE__ +# endif +#endif + +#endif + +/** The abort() function causes abnormal program termination to occur. + This realization disables interrupts and jumps to _exit() function + with argument equal to 1. In the limited AVR environment, execution is + effectively halted by entering an infinite loop. */ +extern void abort(void) __ATTR_NORETURN__; + +/** The abs() function computes the absolute value of the integer \c i. + \note The abs() and labs() functions are builtins of gcc. +*/ +extern int abs(int __i) __ATTR_CONST__; +#ifndef __DOXYGEN__ +#define abs(__i) __builtin_abs(__i) +#endif + +/** The labs() function computes the absolute value of the long integer + \c i. + \note The abs() and labs() functions are builtins of gcc. +*/ +extern long labs(long __i) __ATTR_CONST__; +#ifndef __DOXYGEN__ +#define labs(__i) __builtin_labs(__i) +#endif + +/** + The bsearch() function searches an array of \c nmemb objects, the + initial member of which is pointed to by \c base, for a member + that matches the object pointed to by \c key. The size of each + member of the array is specified by \c size. + + The contents of the array should be in ascending sorted order + according to the comparison function referenced by \c compar. + The \c compar routine is expected to have two arguments which + point to the key object and to an array member, in that order, + and should return an integer less than, equal to, or greater than + zero if the key object is found, respectively, to be less than, + to match, or be greater than the array member. + + The bsearch() function returns a pointer to a matching member of + the array, or a null pointer if no match is found. If two + members compare as equal, which member is matched is unspecified. +*/ +extern void *bsearch(const void *__key, const void *__base, size_t __nmemb, + size_t __size, int (*__compar)(const void *, const void *)); + +/* __divmodhi4 and __divmodsi4 from libgcc.a */ +/** + The div() function computes the value \c num/denom and returns + the quotient and remainder in a structure named \c div_t that + contains two int members named \c quot and \c rem. +*/ +extern div_t div(int __num, int __denom) __asm__("__divmodhi4") __ATTR_CONST__; +/** + The ldiv() function computes the value \c num/denom and returns + the quotient and remainder in a structure named \c ldiv_t that + contains two long integer members named \c quot and \c rem. +*/ +extern ldiv_t ldiv(long __num, long __denom) __asm__("__divmodsi4") __ATTR_CONST__; + +/** + The qsort() function is a modified partition-exchange sort, or + quicksort. + + The qsort() function sorts an array of \c nmemb objects, the + initial member of which is pointed to by \c base. The size of + each object is specified by \c size. The contents of the array + base are sorted in ascending order according to a comparison + function pointed to by \c compar, which requires two arguments + pointing to the objects being compared. + + The comparison function must return an integer less than, equal + to, or greater than zero if the first argument is considered to + be respectively less than, equal to, or greater than the second. +*/ +extern void qsort(void *__base, size_t __nmemb, size_t __size, + __compar_fn_t __compar); + +/** + The strtol() function converts the string in \c nptr to a long + value. The conversion is done according to the given base, which + must be between 2 and 36 inclusive, or be the special value 0. + + The string may begin with an arbitrary amount of white space (as + determined by isspace()) followed by a single optional \c '+' or \c '-' + sign. If \c base is zero or 16, the string may then include a + \c "0x" prefix, and the number will be read in base 16; otherwise, + a zero base is taken as 10 (decimal) unless the next character is + \c '0', in which case it is taken as 8 (octal). + + The remainder of the string is converted to a long value in the + obvious manner, stopping at the first character which is not a + valid digit in the given base. (In bases above 10, the letter \c 'A' + in either upper or lower case represents 10, \c 'B' represents 11, + and so forth, with \c 'Z' representing 35.) + + If \c endptr is not NULL, strtol() stores the address of the first + invalid character in \c *endptr. If there were no digits at all, + however, strtol() stores the original value of \c nptr in \c + *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' + on return, the entire string was valid.) + + The strtol() function returns the result of the conversion, unless + the value would underflow or overflow. If no conversion could be + performed, 0 is returned. If an overflow or underflow occurs, \c + errno is set to \ref avr_errno "ERANGE" and the function return value + is clamped to \c LONG_MIN or \c LONG_MAX, respectively. +*/ +extern long strtol(const char *__nptr, char **__endptr, int __base); + +/** + The strtoul() function converts the string in \c nptr to an + unsigned long value. The conversion is done according to the + given base, which must be between 2 and 36 inclusive, or be the + special value 0. + + The string may begin with an arbitrary amount of white space (as + determined by isspace()) followed by a single optional \c '+' or \c '-' + sign. If \c base is zero or 16, the string may then include a + \c "0x" prefix, and the number will be read in base 16; otherwise, + a zero base is taken as 10 (decimal) unless the next character is + \c '0', in which case it is taken as 8 (octal). + + The remainder of the string is converted to an unsigned long value + in the obvious manner, stopping at the first character which is + not a valid digit in the given base. (In bases above 10, the + letter \c 'A' in either upper or lower case represents 10, \c 'B' + represents 11, and so forth, with \c 'Z' representing 35.) + + If \c endptr is not NULL, strtoul() stores the address of the first + invalid character in \c *endptr. If there were no digits at all, + however, strtoul() stores the original value of \c nptr in \c + *endptr. (Thus, if \c *nptr is not \c '\\0' but \c **endptr is \c '\\0' + on return, the entire string was valid.) + + The strtoul() function return either the result of the conversion + or, if there was a leading minus sign, the negation of the result + of the conversion, unless the original (non-negated) value would + overflow; in the latter case, strtoul() returns ULONG_MAX, and \c + errno is set to \ref avr_errno "ERANGE". If no conversion could + be performed, 0 is returned. +*/ +extern unsigned long strtoul(const char *__nptr, char **__endptr, int __base); + +/** + The atol() function converts the initial portion of the string + pointed to by \p s to long integer representation. In contrast to + + \code strtol(s, (char **)NULL, 10); \endcode + + this function does not detect overflow (\c errno is not changed and + the result value is not predictable), uses smaller memory (flash and + stack) and works more quickly. +*/ +extern long atol(const char *__s) __ATTR_PURE__; + +/** + The atoi() function converts the initial portion of the string + pointed to by \p s to integer representation. In contrast to + + \code (int)strtol(s, (char **)NULL, 10); \endcode + + this function does not detect overflow (\c errno is not changed and + the result value is not predictable), uses smaller memory (flash and + stack) and works more quickly. +*/ +extern int atoi(const char *__s) __ATTR_PURE__; + +/** + The exit() function terminates the application. Since there is no + environment to return to, \c status is ignored, and code execution + will eventually reach an infinite loop, thereby effectively halting + all code processing. Before entering the infinite loop, interrupts + are globally disabled. + + In a C++ context, global destructors will be called before halting + execution. +*/ +extern void exit(int __status) __ATTR_NORETURN__; + +/** + The malloc() function allocates \c size bytes of memory. + If malloc() fails, a NULL pointer is returned. + + Note that malloc() does \e not initialize the returned memory to + zero bytes. + + See the chapter about \ref malloc "malloc() usage" for implementation + details. +*/ +extern void *malloc(size_t __size) __ATTR_MALLOC__; + +/** + The free() function causes the allocated memory referenced by \c + ptr to be made available for future allocations. If \c ptr is + NULL, no action occurs. +*/ +extern void free(void *__ptr); + +/** + \c malloc() \ref malloc_tunables "tunable". +*/ +extern size_t __malloc_margin; + +/** + \c malloc() \ref malloc_tunables "tunable". +*/ +extern char *__malloc_heap_start; + +/** + \c malloc() \ref malloc_tunables "tunable". +*/ +extern char *__malloc_heap_end; + +/** + Allocate \c nele elements of \c size each. Identical to calling + \c malloc() using nele * size as argument, except the + allocated memory will be cleared to zero. +*/ +extern void *calloc(size_t __nele, size_t __size) __ATTR_MALLOC__; + +/** + The realloc() function tries to change the size of the region + allocated at \c ptr to the new \c size value. It returns a + pointer to the new region. The returned pointer might be the + same as the old pointer, or a pointer to a completely different + region. + + The contents of the returned region up to either the old or the new + size value (whatever is less) will be identical to the contents of + the old region, even in case a new region had to be allocated. + + It is acceptable to pass \c ptr as NULL, in which case realloc() + will behave identical to malloc(). + + If the new memory cannot be allocated, realloc() returns NULL, and + the region at \c ptr will not be changed. +*/ +extern void *realloc(void *__ptr, size_t __size) __ATTR_MALLOC__; + +extern double strtod(const char *__nptr, char **__endptr); + +/** \ingroup avr_stdlib + \fn double atof (const char *nptr) + + The atof() function converts the initial portion of the string pointed + to by \a nptr to double representation. + + It is equivalent to calling + \code strtod(nptr, (char **)0); \endcode + */ +extern double atof(const char *__nptr); + +/** Highest number that can be generated by rand(). */ +#define RAND_MAX 0x7FFF + +/** + The rand() function computes a sequence of pseudo-random integers in the + range of 0 to \c RAND_MAX (as defined by the header file ). + + The srand() function sets its argument \c seed as the seed for a new + sequence of pseudo-random numbers to be returned by rand(). These + sequences are repeatable by calling srand() with the same seed value. + + If no seed value is provided, the functions are automatically seeded with + a value of 1. + + In compliance with the C standard, these functions operate on + \c int arguments. Since the underlying algorithm already uses + 32-bit calculations, this causes a loss of precision. See + \c random() for an alternate set of functions that retains full + 32-bit precision. +*/ +extern int rand(void); +/** + Pseudo-random number generator seeding; see rand(). +*/ +extern void srand(unsigned int __seed); + +/** + Variant of rand() that stores the context in the user-supplied + variable located at \c ctx instead of a static library variable + so the function becomes re-entrant. +*/ +extern int rand_r(unsigned long *__ctx); +/*@}*/ + +/*@{*/ +/** \name Non-standard (i.e. non-ISO C) functions. + \ingroup avr_stdlib +*/ +/** + \brief Convert an integer to a string. + + The function itoa() converts the integer value from \c val into an + ASCII representation that will be stored under \c s. The caller + is responsible for providing sufficient storage in \c s. + + \note The minimal size of the buffer \c s depends on the choice of + radix. For example, if the radix is 2 (binary), you need to supply a buffer + with a minimal length of 8 * sizeof (int) + 1 characters, i.e. one + character for each bit plus one for the string terminator. Using a larger + radix will require a smaller minimal buffer size. + + \warning If the buffer is too small, you risk a buffer overflow. + + Conversion is done using the \c radix as base, which may be a + number between 2 (binary conversion) and up to 36. If \c radix + is greater than 10, the next digit after \c '9' will be the letter + \c 'a'. + + If radix is 10 and val is negative, a minus sign will be prepended. + + The itoa() function returns the pointer passed as \c s. +*/ +#ifdef __DOXYGEN__ +extern char *itoa(int val, char *s, int radix); +#else +extern __inline__ __ATTR_GNU_INLINE__ +char *itoa (int __val, char *__s, int __radix) +{ + if (!__builtin_constant_p (__radix)) { + extern char *__itoa (int, char *, int); + return __itoa (__val, __s, __radix); + } else if (__radix < 2 || __radix > 36) { + *__s = 0; + return __s; + } else { + extern char *__itoa_ncheck (int, char *, unsigned char); + return __itoa_ncheck (__val, __s, __radix); + } +} +#endif + +/** + \ingroup avr_stdlib + + \brief Convert a long integer to a string. + + The function ltoa() converts the long integer value from \c val into an + ASCII representation that will be stored under \c s. The caller + is responsible for providing sufficient storage in \c s. + + \note The minimal size of the buffer \c s depends on the choice of + radix. For example, if the radix is 2 (binary), you need to supply a buffer + with a minimal length of 8 * sizeof (long int) + 1 characters, i.e. one + character for each bit plus one for the string terminator. Using a larger + radix will require a smaller minimal buffer size. + + \warning If the buffer is too small, you risk a buffer overflow. + + Conversion is done using the \c radix as base, which may be a + number between 2 (binary conversion) and up to 36. If \c radix + is greater than 10, the next digit after \c '9' will be the letter + \c 'a'. + + If radix is 10 and val is negative, a minus sign will be prepended. + + The ltoa() function returns the pointer passed as \c s. +*/ +#ifdef __DOXYGEN__ +extern char *ltoa(long val, char *s, int radix); +#else +extern __inline__ __ATTR_GNU_INLINE__ +char *ltoa (long __val, char *__s, int __radix) +{ + if (!__builtin_constant_p (__radix)) { + extern char *__ltoa (long, char *, int); + return __ltoa (__val, __s, __radix); + } else if (__radix < 2 || __radix > 36) { + *__s = 0; + return __s; + } else { + extern char *__ltoa_ncheck (long, char *, unsigned char); + return __ltoa_ncheck (__val, __s, __radix); + } +} +#endif + +/** + \ingroup avr_stdlib + + \brief Convert an unsigned integer to a string. + + The function utoa() converts the unsigned integer value from \c val into an + ASCII representation that will be stored under \c s. The caller + is responsible for providing sufficient storage in \c s. + + \note The minimal size of the buffer \c s depends on the choice of + radix. For example, if the radix is 2 (binary), you need to supply a buffer + with a minimal length of 8 * sizeof (unsigned int) + 1 characters, i.e. one + character for each bit plus one for the string terminator. Using a larger + radix will require a smaller minimal buffer size. + + \warning If the buffer is too small, you risk a buffer overflow. + + Conversion is done using the \c radix as base, which may be a + number between 2 (binary conversion) and up to 36. If \c radix + is greater than 10, the next digit after \c '9' will be the letter + \c 'a'. + + The utoa() function returns the pointer passed as \c s. +*/ +#ifdef __DOXYGEN__ +extern char *utoa(unsigned int val, char *s, int radix); +#else +extern __inline__ __ATTR_GNU_INLINE__ +char *utoa (unsigned int __val, char *__s, int __radix) +{ + if (!__builtin_constant_p (__radix)) { + extern char *__utoa (unsigned int, char *, int); + return __utoa (__val, __s, __radix); + } else if (__radix < 2 || __radix > 36) { + *__s = 0; + return __s; + } else { + extern char *__utoa_ncheck (unsigned int, char *, unsigned char); + return __utoa_ncheck (__val, __s, __radix); + } +} +#endif + +/** + \ingroup avr_stdlib + \brief Convert an unsigned long integer to a string. + + The function ultoa() converts the unsigned long integer value from + \c val into an ASCII representation that will be stored under \c s. + The caller is responsible for providing sufficient storage in \c s. + + \note The minimal size of the buffer \c s depends on the choice of + radix. For example, if the radix is 2 (binary), you need to supply a buffer + with a minimal length of 8 * sizeof (unsigned long int) + 1 characters, + i.e. one character for each bit plus one for the string terminator. Using a + larger radix will require a smaller minimal buffer size. + + \warning If the buffer is too small, you risk a buffer overflow. + + Conversion is done using the \c radix as base, which may be a + number between 2 (binary conversion) and up to 36. If \c radix + is greater than 10, the next digit after \c '9' will be the letter + \c 'a'. + + The ultoa() function returns the pointer passed as \c s. +*/ +#ifdef __DOXYGEN__ +extern char *ultoa(unsigned long val, char *s, int radix); +#else +extern __inline__ __ATTR_GNU_INLINE__ +char *ultoa (unsigned long __val, char *__s, int __radix) +{ + if (!__builtin_constant_p (__radix)) { + extern char *__ultoa (unsigned long, char *, int); + return __ultoa (__val, __s, __radix); + } else if (__radix < 2 || __radix > 36) { + *__s = 0; + return __s; + } else { + extern char *__ultoa_ncheck (unsigned long, char *, unsigned char); + return __ultoa_ncheck (__val, __s, __radix); + } +} +#endif + +/** \ingroup avr_stdlib +Highest number that can be generated by random(). */ +#define RANDOM_MAX 0x7FFFFFFF + +/** + \ingroup avr_stdlib + The random() function computes a sequence of pseudo-random integers in the + range of 0 to \c RANDOM_MAX (as defined by the header file ). + + The srandom() function sets its argument \c seed as the seed for a new + sequence of pseudo-random numbers to be returned by rand(). These + sequences are repeatable by calling srandom() with the same seed value. + + If no seed value is provided, the functions are automatically seeded with + a value of 1. +*/ +extern long random(void); +/** + \ingroup avr_stdlib + Pseudo-random number generator seeding; see random(). +*/ +extern void srandom(unsigned long __seed); + +/** + \ingroup avr_stdlib + Variant of random() that stores the context in the user-supplied + variable located at \c ctx instead of a static library variable + so the function becomes re-entrant. +*/ +extern long random_r(unsigned long *__ctx); +#endif /* __ASSEMBLER */ +/*@}*/ + +/*@{*/ +/** \name Conversion functions for double arguments. + \ingroup avr_stdlib + Note that these functions are not located in the default library, + libc.a, but in the mathematical library, libm.a. + So when linking the application, the \c -lm option needs to be + specified. +*/ +/** \ingroup avr_stdlib + Bit value that can be passed in \c flags to dtostre(). */ +#define DTOSTR_ALWAYS_SIGN 0x01 /* put '+' or ' ' for positives */ +/** \ingroup avr_stdlib + Bit value that can be passed in \c flags to dtostre(). */ +#define DTOSTR_PLUS_SIGN 0x02 /* put '+' rather than ' ' */ +/** \ingroup avr_stdlib + Bit value that can be passed in \c flags to dtostre(). */ +#define DTOSTR_UPPERCASE 0x04 /* put 'E' rather 'e' */ + +#ifndef __ASSEMBLER__ + +/** + \ingroup avr_stdlib + The dtostre() function converts the double value passed in \c val into + an ASCII representation that will be stored under \c s. The caller + is responsible for providing sufficient storage in \c s. + + Conversion is done in the format \c "[-]d.ddde±dd" where there is + one digit before the decimal-point character and the number of + digits after it is equal to the precision \c prec; if the precision + is zero, no decimal-point character appears. If \c flags has the + DTOSTR_UPPERCASE bit set, the letter \c 'E' (rather than \c 'e' ) will be + used to introduce the exponent. The exponent always contains two + digits; if the value is zero, the exponent is \c "00". + + If \c flags has the DTOSTR_ALWAYS_SIGN bit set, a space character + will be placed into the leading position for positive numbers. + + If \c flags has the DTOSTR_PLUS_SIGN bit set, a plus sign will be + used instead of a space character in this case. + + The dtostre() function returns the pointer to the converted string \c s. +*/ +extern char *dtostre(double __val, char *__s, unsigned char __prec, + unsigned char __flags); + +/** + \ingroup avr_stdlib + The dtostrf() function converts the double value passed in \c val into + an ASCII representationthat will be stored under \c s. The caller + is responsible for providing sufficient storage in \c s. + + Conversion is done in the format \c "[-]d.ddd". The minimum field + width of the output string (including the possible \c '.' and the possible + sign for negative values) is given in \c width, and \c prec determines + the number of digits after the decimal sign. \c width is signed value, + negative for left adjustment. + + The dtostrf() function returns the pointer to the converted string \c s. +*/ +extern char *dtostrf(double __val, signed char __width, + unsigned char __prec, char *__s); + +/** + \ingroup avr_stdlib + Successful termination for exit(); evaluates to 0. +*/ +#define EXIT_SUCCESS 0 + +/** + \ingroup avr_stdlib + Unsuccessful termination for exit(); evaluates to a non-zero value. +*/ +#define EXIT_FAILURE 1 + +/*@}*/ + +#ifndef __DOXYGEN__ +/* dummy declarations for libstdc++ compatibility */ +extern int atexit(void (*)(void)); +extern int system (const char *); +extern char *getenv (const char *); +#endif /* __DOXYGEN__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLER */ + +#endif /* _STDLIB_H_ */ diff --git a/hardware/tools/avr/avr/include/string.h b/hardware/tools/avr/avr/include/string.h new file mode 100644 index 0000000000000000000000000000000000000000..35d895b6d0fa55a2df475eba4ab44ae37d1c1cc6 --- /dev/null +++ b/hardware/tools/avr/avr/include/string.h @@ -0,0 +1,620 @@ +/* Copyright (c) 2002,2007 Marek Michalkiewicz + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/* + string.h + + Contributors: + Created by Marek Michalkiewicz + */ + +#ifndef _STRING_H_ +#define _STRING_H_ 1 + +#ifndef __DOXYGEN__ +#define __need_NULL +#define __need_size_t +#include + +#ifndef __ATTR_PURE__ +#define __ATTR_PURE__ __attribute__((__pure__)) +#endif + +#ifndef __ATTR_CONST__ +# define __ATTR_CONST__ __attribute__((__const__)) +#endif +#endif /* !__DOXYGEN__ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \file */ +/** \defgroup avr_string : Strings + \code #include \endcode + + The string functions perform string operations on NULL terminated + strings. + + \note If the strings you are working on resident in program space (flash), + you will need to use the string functions described in \ref avr_pgmspace. */ + + +/** \ingroup avr_string + + This macro finds the first (least significant) bit set in the + input value. + + This macro is very similar to the function ffs() except that + it evaluates its argument at compile-time, so it should only + be applied to compile-time constant expressions where it will + reduce to a constant itself. + Application of this macro to expressions that are not constant + at compile-time is not recommended, and might result in a huge + amount of code generated. + + \returns The _FFS() macro returns the position of the first + (least significant) bit set in the word val, or 0 if no bits are set. + The least significant bit is position 1. Only 16 bits of argument + are evaluted. +*/ +#if defined(__DOXYGEN__) +#define _FFS(x) +#else /* !DOXYGEN */ +#define _FFS(x) \ + (1 \ + + (((x) & 1) == 0) \ + + (((x) & 3) == 0) \ + + (((x) & 7) == 0) \ + + (((x) & 017) == 0) \ + + (((x) & 037) == 0) \ + + (((x) & 077) == 0) \ + + (((x) & 0177) == 0) \ + + (((x) & 0377) == 0) \ + + (((x) & 0777) == 0) \ + + (((x) & 01777) == 0) \ + + (((x) & 03777) == 0) \ + + (((x) & 07777) == 0) \ + + (((x) & 017777) == 0) \ + + (((x) & 037777) == 0) \ + + (((x) & 077777) == 0) \ + - (((x) & 0177777) == 0) * 16) +#endif /* DOXYGEN */ + +/** \ingroup avr_string + \fn int ffs(int val); + + \brief This function finds the first (least significant) bit set in the input value. + + \returns The ffs() function returns the position of the first + (least significant) bit set in the word val, or 0 if no bits are set. + The least significant bit is position 1. + + \note For expressions that are constant at compile time, consider + using the \ref _FFS macro instead. +*/ +extern int ffs(int __val) __ATTR_CONST__; + +/** \ingroup avr_string + \fn int ffsl(long val); + + \brief Same as ffs(), for an argument of type long. */ +extern int ffsl(long __val) __ATTR_CONST__; + +/** \ingroup avr_string + \fn int ffsll(long long val); + + \brief Same as ffs(), for an argument of type long long. */ +__extension__ extern int ffsll(long long __val) __ATTR_CONST__; + +/** \ingroup avr_string + \fn void *memccpy(void *dest, const void *src, int val, size_t len) + \brief Copy memory area. + + The memccpy() function copies no more than \p len bytes from memory + area \p src to memory area \p dest, stopping when the character \p val + is found. + + \returns The memccpy() function returns a pointer to the next character + in \p dest after \p val, or NULL if \p val was not found in the first + \p len characters of \p src. */ +extern void *memccpy(void *, const void *, int, size_t); + +/** \ingroup avr_string + \fn void *memchr(const void *src, int val, size_t len) + \brief Scan memory for a character. + + The memchr() function scans the first len bytes of the memory area pointed + to by src for the character val. The first byte to match val (interpreted + as an unsigned character) stops the operation. + + \returns The memchr() function returns a pointer to the matching byte or + NULL if the character does not occur in the given memory area. */ +extern void *memchr(const void *, int, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn int memcmp(const void *s1, const void *s2, size_t len) + \brief Compare memory areas + + The memcmp() function compares the first len bytes of the memory areas s1 + and s2. The comparision is performed using unsigned char operations. + + \returns The memcmp() function returns an integer less than, equal to, or + greater than zero if the first len bytes of s1 is found, respectively, to be + less than, to match, or be greater than the first len bytes of s2. + + \note Be sure to store the result in a 16 bit variable since you may get + incorrect results if you use an unsigned char or char due to truncation. + + \warning This function is not -mint8 compatible, although if you only care + about testing for equality, this function should be safe to use. */ +extern int memcmp(const void *, const void *, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn void *memcpy(void *dest, const void *src, size_t len) + \brief Copy a memory area. + + The memcpy() function copies len bytes from memory area src to memory area + dest. The memory areas may not overlap. Use memmove() if the memory + areas do overlap. + + \returns The memcpy() function returns a pointer to dest. */ +extern void *memcpy(void *, const void *, size_t); + +/** \ingroup avr_string + \fn void *memmem(const void *s1, size_t len1, const void *s2, size_t len2) + + The memmem() function finds the start of the first occurrence of the + substring \p s2 of length \p len2 in the memory area \p s1 of length + \p len1. + + \return The memmem() function returns a pointer to the beginning of + the substring, or \c NULL if the substring is not found. If \p len2 + is zero, the function returns \p s1. */ +extern void *memmem(const void *, size_t, const void *, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn void *memmove(void *dest, const void *src, size_t len) + \brief Copy memory area. + + The memmove() function copies len bytes from memory area src to memory area + dest. The memory areas may overlap. + + \returns The memmove() function returns a pointer to dest. */ +extern void *memmove(void *, const void *, size_t); + +/** \ingroup avr_string + \fn void *memrchr(const void *src, int val, size_t len) + + The memrchr() function is like the memchr() function, except that it + searches backwards from the end of the \p len bytes pointed to by \p + src instead of forwards from the front. (Glibc, GNU extension.) + + \return The memrchr() function returns a pointer to the matching + byte or \c NULL if the character does not occur in the given memory + area. */ +extern void *memrchr(const void *, int, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn void *memset(void *dest, int val, size_t len) + \brief Fill memory with a constant byte. + + The memset() function fills the first len bytes of the memory area pointed + to by dest with the constant byte val. + + \returns The memset() function returns a pointer to the memory area dest. */ +extern void *memset(void *, int, size_t); + +/** \ingroup avr_string + \fn char *strcat(char *dest, const char *src) + \brief Concatenate two strings. + + The strcat() function appends the src string to the dest string + overwriting the '\\0' character at the end of dest, and then adds a + terminating '\\0' character. The strings may not overlap, and the dest + string must have enough space for the result. + + \returns The strcat() function returns a pointer to the resulting string + dest. */ +extern char *strcat(char *, const char *); + +/** \ingroup avr_string + \fn char *strchr(const char *src, int val) + \brief Locate character in string. + + The strchr() function returns a pointer to the first occurrence of + the character \p val in the string \p src. + + Here "character" means "byte" - these functions do not work with + wide or multi-byte characters. + + \returns The strchr() function returns a pointer to the matched + character or \c NULL if the character is not found. */ +extern char *strchr(const char *, int) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strchrnul(const char *s, int c) + + The strchrnul() function is like strchr() except that if \p c is not + found in \p s, then it returns a pointer to the null byte at the end + of \p s, rather than \c NULL. (Glibc, GNU extension.) + + \return The strchrnul() function returns a pointer to the matched + character, or a pointer to the null byte at the end of \p s (i.e., + \c s+strlen(s)) if the character is not found. */ +extern char *strchrnul(const char *, int) __ATTR_PURE__; + +/** \ingroup avr_string + \fn int strcmp(const char *s1, const char *s2) + \brief Compare two strings. + + The strcmp() function compares the two strings \p s1 and \p s2. + + \returns The strcmp() function returns an integer less than, equal + to, or greater than zero if \p s1 is found, respectively, to be less + than, to match, or be greater than \p s2. A consequence of the + ordering used by strcmp() is that if \p s1 is an initial substring + of \p s2, then \p s1 is considered to be "less than" \p s2. */ +extern int strcmp(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strcpy(char *dest, const char *src) + \brief Copy a string. + + The strcpy() function copies the string pointed to by src (including the + terminating '\\0' character) to the array pointed to by dest. The strings + may not overlap, and the destination string dest must be large enough to + receive the copy. + + \returns The strcpy() function returns a pointer to the destination + string dest. + + \note If the destination string of a strcpy() is not large enough (that + is, if the programmer was stupid/lazy, and failed to check the size before + copying) then anything might happen. Overflowing fixed length strings is + a favourite cracker technique. */ +extern char *strcpy(char *, const char *); + +/** \ingroup avr_string + \fn int strcasecmp(const char *s1, const char *s2) + \brief Compare two strings ignoring case. + + The strcasecmp() function compares the two strings \p s1 and \p s2, + ignoring the case of the characters. + + \returns The strcasecmp() function returns an integer less than, + equal to, or greater than zero if \p s1 is found, respectively, to + be less than, to match, or be greater than \p s2. A consequence of + the ordering used by strcasecmp() is that if \p s1 is an initial + substring of \p s2, then \p s1 is considered to be "less than" + \p s2. */ +extern int strcasecmp(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strcasestr(const char *s1, const char *s2) + + The strcasestr() function finds the first occurrence of the + substring \p s2 in the string \p s1. This is like strstr(), except + that it ignores case of alphabetic symbols in searching for the + substring. (Glibc, GNU extension.) + + \return The strcasestr() function returns a pointer to the beginning + of the substring, or \c NULL if the substring is not found. If \p s2 + points to a string of zero length, the function returns \p s1. */ +extern char *strcasestr(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_string + \fn size_t strcspn(const char *s, const char *reject) + + The strcspn() function calculates the length of the initial segment + of \p s which consists entirely of characters not in \p reject. + + \return The strcspn() function returns the number of characters in + the initial segment of \p s which are not in the string \p reject. + The terminating zero is not considered as a part of string. */ +extern size_t strcspn(const char *__s, const char *__reject) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strdup(const char *s1) + \brief Duplicate a string. + + The strdup() function allocates memory and copies into it the string + addressed by s1, including the terminating null character. + + \warning The strdup() function calls malloc() to allocate the memory + for the duplicated string! The user is responsible for freeing the + memory by calling free(). + + \returns The strdup() function returns a pointer to the resulting string + dest. If malloc() cannot allocate enough storage for the string, strdup() + will return NULL. + + \warning Be sure to check the return value of the strdup() function to + make sure that the function has succeeded in allocating the memory! +*/ +extern char *strdup(const char *s1); + +/** \ingroup avr_string + \fn size_t strlcat(char *dst, const char *src, size_t siz) + \brief Concatenate two strings. + + Appends \p src to string \p dst of size \p siz (unlike strncat(), + \p siz is the full size of \p dst, not space left). At most \p siz-1 + characters will be copied. Always NULL terminates (unless \p siz <= + \p strlen(dst)). + + \returns The strlcat() function returns strlen(src) + MIN(siz, + strlen(initial dst)). If retval >= siz, truncation occurred. */ +extern size_t strlcat(char *, const char *, size_t); + +/** \ingroup avr_string + \fn size_t strlcpy(char *dst, const char *src, size_t siz) + \brief Copy a string. + + Copy \p src to string \p dst of size \p siz. At most \p siz-1 + characters will be copied. Always NULL terminates (unless \p siz == 0). + + \returns The strlcpy() function returns strlen(src). If retval >= siz, + truncation occurred. */ +extern size_t strlcpy(char *, const char *, size_t); + +/** \ingroup avr_string + \fn size_t strlen(const char *src) + \brief Calculate the length of a string. + + The strlen() function calculates the length of the string src, not + including the terminating '\\0' character. + + \returns The strlen() function returns the number of characters in + src. */ +extern size_t strlen(const char *) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strlwr(char *s) + \brief Convert a string to lower case. + + The strlwr() function will convert a string to lower case. Only the upper + case alphabetic characters [A .. Z] are converted. Non-alphabetic + characters will not be changed. + + \returns The strlwr() function returns a pointer to the converted + string. */ +extern char *strlwr(char *); + +/** \ingroup avr_string + \fn char *strncat(char *dest, const char *src, size_t len) + \brief Concatenate two strings. + + The strncat() function is similar to strcat(), except that only the first + n characters of src are appended to dest. + + \returns The strncat() function returns a pointer to the resulting string + dest. */ +extern char *strncat(char *, const char *, size_t); + +/** \ingroup avr_string + \fn int strncmp(const char *s1, const char *s2, size_t len) + \brief Compare two strings. + + The strncmp() function is similar to strcmp(), except it only compares the + first (at most) n characters of s1 and s2. + + \returns The strncmp() function returns an integer less than, equal to, or + greater than zero if s1 (or the first n bytes thereof) is found, + respectively, to be less than, to match, or be greater than s2. */ +extern int strncmp(const char *, const char *, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strncpy(char *dest, const char *src, size_t len) + \brief Copy a string. + + The strncpy() function is similar to strcpy(), except that not more than n + bytes of src are copied. Thus, if there is no null byte among the first n + bytes of src, the result will not be null-terminated. + + In the case where the length of src is less than that of n, the remainder + of dest will be padded with nulls. + + \returns The strncpy() function returns a pointer to the destination + string dest. */ +extern char *strncpy(char *, const char *, size_t); + +/** \ingroup avr_string + \fn int strncasecmp(const char *s1, const char *s2, size_t len) + \brief Compare two strings ignoring case. + + The strncasecmp() function is similar to strcasecmp(), except it + only compares the first \p len characters of \p s1. + + \returns The strncasecmp() function returns an integer less than, + equal to, or greater than zero if \p s1 (or the first \p len bytes + thereof) is found, respectively, to be less than, to match, or be + greater than \p s2. A consequence of the ordering used by + strncasecmp() is that if \p s1 is an initial substring of \p s2, + then \p s1 is considered to be "less than" \p s2. */ +extern int strncasecmp(const char *, const char *, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn size_t strnlen(const char *src, size_t len) + \brief Determine the length of a fixed-size string. + + The strnlen function returns the number of characters in the string + pointed to by src, not including the terminating '\\0' character, but at + most len. In doing this, strnlen looks only at the first len characters at + src and never beyond src+len. + + \returns The strnlen function returns strlen(src), if that is less than + len, or len if there is no '\\0' character among the first len + characters pointed to by src. */ +extern size_t strnlen(const char *, size_t) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strpbrk(const char *s, const char *accept) + + The strpbrk() function locates the first occurrence in the string + \p s of any of the characters in the string \p accept. + + \return The strpbrk() function returns a pointer to the character + in \p s that matches one of the characters in \p accept, or \c NULL + if no such character is found. The terminating zero is not + considered as a part of string: if one or both args are empty, the + result will be \c NULL. */ +extern char *strpbrk(const char *__s, const char *__accept) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strrchr(const char *src, int val) + \brief Locate character in string. + + The strrchr() function returns a pointer to the last occurrence of the + character val in the string src. + + Here "character" means "byte" - these functions do not work with wide or + multi-byte characters. + + \returns The strrchr() function returns a pointer to the matched character + or NULL if the character is not found. */ +extern char *strrchr(const char *, int) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strrev(char *s) + \brief Reverse a string. + + The strrev() function reverses the order of the string. + + \returns The strrev() function returns a pointer to the beginning of the + reversed string. */ +extern char *strrev(char *); + +/** \ingroup avr_string + \fn char *strsep(char **sp, const char *delim) + \brief Parse a string into tokens. + + The strsep() function locates, in the string referenced by \p *sp, + the first occurrence of any character in the string \p delim (or the + terminating '\\0' character) and replaces it with a '\\0'. The + location of the next character after the delimiter character (or \c + NULL, if the end of the string was reached) is stored in \p *sp. An + ``empty'' field, i.e. one caused by two adjacent delimiter + characters, can be detected by comparing the location referenced by + the pointer returned in \p *sp to '\\0'. + + \return The strsep() function returns a pointer to the original + value of \p *sp. If \p *sp is initially \c NULL, strsep() returns + \c NULL. */ +extern char *strsep(char **, const char *); + +/** \ingroup avr_string + \fn size_t strspn(const char *s, const char *accept) + + The strspn() function calculates the length of the initial segment + of \p s which consists entirely of characters in \p accept. + + \return The strspn() function returns the number of characters in + the initial segment of \p s which consist only of characters from \p + accept. The terminating zero is not considered as a part of string. */ +extern size_t strspn(const char *__s, const char *__accept) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strstr(const char *s1, const char *s2) + \brief Locate a substring. + + The strstr() function finds the first occurrence of the substring \p + s2 in the string \p s1. The terminating '\\0' characters are not + compared. + + \returns The strstr() function returns a pointer to the beginning of + the substring, or \c NULL if the substring is not found. If \p s2 + points to a string of zero length, the function returns \p s1. */ +extern char *strstr(const char *, const char *) __ATTR_PURE__; + +/** \ingroup avr_string + \fn char *strtok(char *s, const char *delim) + \brief Parses the string s into tokens. + + strtok parses the string s into tokens. The first call to strtok + should have s as its first argument. Subsequent calls should have + the first argument set to NULL. If a token ends with a delimiter, this + delimiting character is overwritten with a '\\0' and a pointer to the next + character is saved for the next call to strtok. The delimiter string + delim may be different for each call. + + \returns The strtok() function returns a pointer to the next token or + NULL when no more tokens are found. + + \note strtok() is NOT reentrant. For a reentrant version of this function + see \c strtok_r(). +*/ +extern char *strtok(char *, const char *); + +/** \ingroup avr_string + \fn char *strtok_r(char *string, const char *delim, char **last) + \brief Parses string into tokens. + + strtok_r parses string into tokens. The first call to strtok_r + should have string as its first argument. Subsequent calls should have + the first argument set to NULL. If a token ends with a delimiter, this + delimiting character is overwritten with a '\\0' and a pointer to the next + character is saved for the next call to strtok_r. The delimiter string + \p delim may be different for each call. \p last is a user allocated char* + pointer. It must be the same while parsing the same string. strtok_r is + a reentrant version of strtok(). + + \returns The strtok_r() function returns a pointer to the next token or + NULL when no more tokens are found. */ +extern char *strtok_r(char *, const char *, char **); + +/** \ingroup avr_string + \fn char *strupr(char *s) + \brief Convert a string to upper case. + + The strupr() function will convert a string to upper case. Only the lower + case alphabetic characters [a .. z] are converted. Non-alphabetic + characters will not be changed. + + \returns The strupr() function returns a pointer to the converted + string. The pointer is the same as that passed in since the operation is + perform in place. */ +extern char *strupr(char *); + +#ifndef __DOXYGEN__ +/* libstdc++ compatibility, dummy declarations */ +extern int strcoll(const char *s1, const char *s2); +extern char *strerror(int errnum); +extern size_t strxfrm(char *dest, const char *src, size_t n); +#endif /* !__DOXYGEN__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* _STRING_H_ */ + diff --git a/hardware/tools/avr/avr/include/sys/types.h b/hardware/tools/avr/avr/include/sys/types.h new file mode 100644 index 0000000000000000000000000000000000000000..e5df837c9aaada964c90ecfca24cf9893138c047 --- /dev/null +++ b/hardware/tools/avr/avr/include/sys/types.h @@ -0,0 +1,6 @@ +#ifndef _SYS_TYPES_H_ +#define _SYS_TYPES_H_ 1 + +typedef long off_t; + +#endif diff --git a/hardware/tools/avr/avr/include/time.h b/hardware/tools/avr/avr/include/time.h new file mode 100644 index 0000000000000000000000000000000000000000..ffffaaca7effe65e35a7b1f07076681370db4bff --- /dev/null +++ b/hardware/tools/avr/avr/include/time.h @@ -0,0 +1,509 @@ +/* + * (C)2012 Michael Duane Rice All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. Redistributions in binary + * form must reproduce the above copyright notice, this list of conditions + * and the following disclaimer in the documentation and/or other materials + * provided with the distribution. Neither the name of the copyright holders + * nor the names of contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* $Id$ */ + +/** \file */ + +/** \defgroup avr_time : Time + \code #include \endcode +

Introduction to the Time functions

+ This file declares the time functions implemented in \c avr-libc. + + The implementation aspires to conform with ISO/IEC 9899 (C90). However, due to limitations of the + target processor and the nature of its development environment, a practical implementation must + of necessity deviate from the standard. + + + + Section 7.23.2.1 clock() + The type clock_t, the macro CLOCKS_PER_SEC, and the function clock() are not implemented. We + consider these items belong to operating system code, or to application code when no operating + system is present. + + Section 7.23.2.3 mktime() + The standard specifies that mktime() should return (time_t) -1, if the time cannot be represented. + This implementation always returns a 'best effort' representation. + + Section 7.23.2.4 time() + The standard specifies that time() should return (time_t) -1, if the time is not available. + Since the application must initialize the time system, this functionality is not implemented. + + Section 7.23.2.2, difftime() + Due to the lack of a 64 bit double, the function difftime() returns a long integer. In most cases + this change will be invisible to the user, handled automatically by the compiler. + + Section 7.23.1.4 struct tm + Per the standard, struct tm->tm_isdst is greater than zero when Daylight Saving time is in effect. + This implementation further specifies that, when positive, the value of tm_isdst represents + the amount time is advanced during Daylight Saving time. + + Section 7.23.3.5 strftime() + Only the 'C' locale is supported, therefore the modifiers 'E' and 'O' are ignored. + The 'Z' conversion is also ignored, due to the lack of time zone name. + + In addition to the above departures from the standard, there are some behaviors which are different + from what is often expected, though allowed under the standard. + + There is no 'platform standard' method to obtain the current time, time zone, or + daylight savings 'rules' in the AVR environment. Therefore the application must initialize + the time system with this information. The functions set_zone(), set_dst(), and + set_system_time() are provided for initialization. Once initialized, system time is maintained by + calling the function system_tick() at one second intervals. + + Though not specified in the standard, it is often expected that time_t is a signed integer + representing an offset in seconds from Midnight Jan 1 1970... i.e. 'Unix time'. This implementation + uses an unsigned 32 bit integer offset from Midnight Jan 1 2000. The use of this 'epoch' helps to + simplify the conversion functions, while the 32 bit value allows time to be properly represented + until Tue Feb 7 06:28:15 2136 UTC. The macros UNIX_OFFSET and NTP_OFFSET are defined to assist in + converting to and from Unix and NTP time stamps. + + Unlike desktop counterparts, it is impractical to implement or maintain the 'zoneinfo' database. + Therefore no attempt is made to account for time zone, daylight saving, or leap seconds in past dates. + All calculations are made according to the currently configured time zone and daylight saving 'rule'. + + In addition to C standard functions, re-entrant versions of ctime(), asctime(), gmtime() and + localtime() are provided which, in addition to being re-entrant, have the property of claiming + less permanent storage in RAM. An additional time conversion, isotime() and its re-entrant version, + uses far less storage than either ctime() or asctime(). + + Along with the usual smattering of utility functions, such as is_leap_year(), this library includes + a set of functions related the sun and moon, as well as sidereal time functions. +*/ + +#ifndef TIME_H +#define TIME_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + /** \ingroup avr_time */ + /* @{ */ + + /** + time_t represents seconds elapsed from Midnight, Jan 1 2000 UTC (the Y2K 'epoch'). + Its range allows this implementation to represent time up to Tue Feb 7 06:28:15 2136 UTC. + */ + typedef uint32_t time_t; + + /** + The time function returns the systems current time stamp. + If timer is not a null pointer, the return value is also assigned to the object it points to. + */ + time_t time(time_t *timer); + + /** + The difftime function returns the difference between two binary time stamps, + time1 - time0. + */ + int32_t difftime(time_t time1, time_t time0); + + + /** + The tm structure contains a representation of time 'broken down' into components of the + Gregorian calendar. + + The value of tm_isdst is zero if Daylight Saving Time is not in effect, and is negative if + the information is not available. + + When Daylight Saving Time is in effect, the value represents the number of + seconds the clock is advanced. + + See the set_dst() function for more information about Daylight Saving. + + */ + struct tm { + int8_t tm_sec; /**< seconds after the minute - [ 0 to 59 ] */ + int8_t tm_min; /**< minutes after the hour - [ 0 to 59 ] */ + int8_t tm_hour; /**< hours since midnight - [ 0 to 23 ] */ + int8_t tm_mday; /**< day of the month - [ 1 to 31 ] */ + int8_t tm_wday; /**< days since Sunday - [ 0 to 6 ] */ + int8_t tm_mon; /**< months since January - [ 0 to 11 ] */ + int16_t tm_year; /**< years since 1900 */ + int16_t tm_yday; /**< days since January 1 - [ 0 to 365 ] */ + int16_t tm_isdst; /**< Daylight Saving Time flag */ + }; + +#ifndef __DOXYGEN__ + /* We have to provide clock_t / CLOCKS_PER_SEC so that libstdc++-v3 can + be built. We define CLOCKS_PER_SEC via a symbol _CLOCKS_PER_SEC_ + so that the user can provide the value on the link line, which should + result in little or no run-time overhead compared with a constant. */ + typedef unsigned long clock_t; + extern char *_CLOCKS_PER_SEC_; +#define CLOCKS_PER_SEC ((clock_t) _CLOCKS_PER_SEC_) + extern clock_t clock(void); +#endif /* !__DOXYGEN__ */ + + /** + This function 'compiles' the elements of a broken-down time structure, returning a binary time stamp. + The elements of timeptr are interpreted as representing Local Time. + + The original values of the tm_wday and tm_yday elements of the structure are ignored, + and the original values of the other elements are not restricted to the ranges stated for struct tm. + + On successful completion, the values of all elements of timeptr are set to the appropriate range. + */ + time_t mktime(struct tm * timeptr); + + /** + This function 'compiles' the elements of a broken-down time structure, returning a binary time stamp. + The elements of timeptr are interpreted as representing UTC. + + The original values of the tm_wday and tm_yday elements of the structure are ignored, + and the original values of the other elements are not restricted to the ranges stated for struct tm. + + Unlike mktime(), this function DOES NOT modify the elements of timeptr. + */ + time_t mk_gmtime(const struct tm * timeptr); + + /** + The gmtime function converts the time stamp pointed to by timer into broken-down time, + expressed as UTC. + */ + struct tm *gmtime(const time_t * timer); + + /** + Re entrant version of gmtime(). + */ + void gmtime_r(const time_t * timer, struct tm * timeptr); + + /** + The localtime function converts the time stamp pointed to by timer into broken-down time, + expressed as Local time. + */ + struct tm *localtime(const time_t * timer); + + /** + Re entrant version of localtime(). + */ + void localtime_r(const time_t * timer, struct tm * timeptr); + + /** + The asctime function converts the broken-down time of timeptr, into an ascii string in the form + + Sun Mar 23 01:03:52 2013 + */ + char *asctime(const struct tm * timeptr); + + /** + Re entrant version of asctime(). + */ + void asctime_r(const struct tm * timeptr, char *buf); + + /** + The ctime function is equivalent to asctime(localtime(timer)) + */ + char *ctime(const time_t * timer); + + /** + Re entrant version of ctime(). + */ + void ctime_r(const time_t * timer, char *buf); + + /** + The isotime function constructs an ascii string in the form + \code2013-03-23 01:03:52\endcode + */ + char *isotime(const struct tm * tmptr); + + /** + Re entrant version of isotime() + */ + void isotime_r(const struct tm *, char *); + + /** + A complete description of strftime() is beyond the pale of this document. + Refer to ISO/IEC document 9899 for details. + + All conversions are made using the 'C Locale', ignoring the E or O modifiers. Due to the lack of + a time zone 'name', the 'Z' conversion is also ignored. + */ + size_t strftime(char *s, size_t maxsize, const char *format, const struct tm * timeptr); + + /** + Specify the Daylight Saving function. + + The Daylight Saving function should examine its parameters to determine whether + Daylight Saving is in effect, and return a value appropriate for tm_isdst. + + Working examples for the USA and the EU are available.. + + \code #include \endcode + for the European Union, and + \code #include \endcode + for the United States + + If a Daylight Saving function is not specified, the system will ignore Daylight Saving. + */ + void set_dst(int (*) (const time_t *, int32_t *)); + + /** + Set the 'time zone'. The parameter is given in seconds East of the Prime Meridian. + Example for New York City: + \code set_zone(-5 * ONE_HOUR);\endcode + + If the time zone is not set, the time system will operate in UTC only. + */ + void set_zone(int32_t); + + /** + Initialize the system time. Examples are... + + From a Clock / Calendar type RTC: + \code + struct tm rtc_time; + + read_rtc(&rtc_time); + rtc_time.tm_isdst = 0; + set_system_time( mktime(&rtc_time) ); + \endcode + + From a Network Time Protocol time stamp: + \code + set_system_time(ntp_timestamp - NTP_OFFSET); + \endcode + + From a UNIX time stamp: + \code + set_system_time(unix_timestamp - UNIX_OFFSET); + \endcode + + */ + void set_system_time(time_t timestamp); + + /** + Maintain the system time by calling this function at a rate of 1 Hertz. + + It is anticipated that this function will typically be called from within an + Interrupt Service Routine, (though that is not required). It therefore includes code which + makes it simple to use from within a 'Naked' ISR, avoiding the cost of saving and restoring + all the cpu registers. + + Such an ISR may resemble the following example... + \code + ISR(RTC_OVF_vect, ISR_NAKED) + { + system_tick(); + reti(); + } + \endcode + */ + void system_tick(void); + + /** + Enumerated labels for the days of the week. + */ + enum _WEEK_DAYS_ { + SUNDAY, + MONDAY, + TUESDAY, + WEDNESDAY, + THURSDAY, + FRIDAY, + SATURDAY + }; + + /** + Enumerated labels for the months. + */ + enum _MONTHS_ { + JANUARY, + FEBRUARY, + MARCH, + APRIL, + MAY, + JUNE, + JULY, + AUGUST, + SEPTEMBER, + OCTOBER, + NOVEMBER, + DECEMBER + }; + + /** + Return 1 if year is a leap year, zero if it is not. + */ + uint8_t is_leap_year(int16_t year); + + /** + Return the length of month, given the year and month, where month is in the range 1 to 12. + */ + uint8_t month_length(int16_t year, uint8_t month); + + /** + Return the calendar week of year, where week 1 is considered to begin on the + day of week specified by 'start'. The returned value may range from zero to 52. + */ + uint8_t week_of_year(const struct tm * timeptr, uint8_t start); + + /** + Return the calendar week of month, where the first week is considered to begin on the + day of week specified by 'start'. The returned value may range from zero to 5. + */ + uint8_t week_of_month(const struct tm * timeptr, uint8_t start); + + /** + Structure which represents a date as a year, week number of that year, and day of week. + See http://en.wikipedia.org/wiki/ISO_week_date for more information. + */ + struct week_date { + int year; /**< year number (Gregorian calendar) */ + int week; /**< week number (#1 is where first Thursday is in) */ + int day; /**< day within week */ + }; + + /** + Return a week_date structure with the ISO_8601 week based date corresponding to the given + year and day of year. See http://en.wikipedia.org/wiki/ISO_week_date for more + information. + */ + struct week_date * iso_week_date( int year, int yday); + + /** + Re-entrant version of iso-week_date. + */ + void iso_week_date_r( int year, int yday, struct week_date *); + + /** + Convert a Y2K time stamp into a FAT file system time stamp. + */ + uint32_t fatfs_time(const struct tm * timeptr); + + /** One hour, expressed in seconds */ +#define ONE_HOUR 3600 + + /** Angular degree, expressed in arc seconds */ +#define ONE_DEGREE 3600 + + /** One day, expressed in seconds */ +#define ONE_DAY 86400 + + /** Difference between the Y2K and the UNIX epochs, in seconds. To convert a Y2K + timestamp to UNIX... + \code + long unix; + time_t y2k; + + y2k = time(NULL); + unix = y2k + UNIX_OFFSET; + \endcode + */ +#define UNIX_OFFSET 946684800 + + /** Difference between the Y2K and the NTP epochs, in seconds. To convert a Y2K + timestamp to NTP... + \code + unsigned long ntp; + time_t y2k; + + y2k = time(NULL); + ntp = y2k + NTP_OFFSET; + \endcode + */ +#define NTP_OFFSET 3155673600 + + /* + * =================================================================== + * Ephemera + */ + + /** + Set the geographic coordinates of the 'observer', for use with several of the + following functions. Parameters are passed as seconds of North Latitude, and seconds + of East Longitude. + + For New York City... + \code set_position( 40.7142 * ONE_DEGREE, -74.0064 * ONE_DEGREE); \endcode + */ + void set_position(int32_t latitude, int32_t longitude); + + /** + Computes the difference between apparent solar time and mean solar time. + The returned value is in seconds. + */ + int16_t equation_of_time(const time_t * timer); + + /** + Computes the amount of time the sun is above the horizon, at the location of the observer. + + NOTE: At observer locations inside a polar circle, this value can be zero during the winter, + and can exceed ONE_DAY during the summer. + + The returned value is in seconds. + */ + int32_t daylight_seconds(const time_t * timer); + + /** + Computes the time of solar noon, at the location of the observer. + */ + time_t solar_noon(const time_t * timer); + + /** + Return the time of sunrise, at the location of the observer. See the note about daylight_seconds(). + */ + time_t sun_rise(const time_t * timer); + + /** + Return the time of sunset, at the location of the observer. See the note about daylight_seconds(). + */ + time_t sun_set(const time_t * timer); + + /** Returns the declination of the sun in radians. */ + double solar_declination(const time_t * timer); + + /** + Returns an approximation to the phase of the moon. + The sign of the returned value indicates a waning or waxing phase. + The magnitude of the returned value indicates the percentage illumination. + */ + int8_t moon_phase(const time_t * timer); + + /** + Returns Greenwich Mean Sidereal Time, as seconds into the sidereal day. + The returned value will range from 0 through 86399 seconds. + */ + unsigned long gm_sidereal(const time_t * timer); + + /** + Returns Local Mean Sidereal Time, as seconds into the sidereal day. + The returned value will range from 0 through 86399 seconds. + */ + unsigned long lm_sidereal(const time_t * timer); + + /* @} */ +#ifdef __cplusplus +} +#endif + +#endif /* TIME_H */ diff --git a/hardware/tools/avr/avr/include/unistd.h b/hardware/tools/avr/avr/include/unistd.h new file mode 100644 index 0000000000000000000000000000000000000000..c904e62b6aee48c2d4d04a435d9e9fbff2d94e93 --- /dev/null +++ b/hardware/tools/avr/avr/include/unistd.h @@ -0,0 +1,8 @@ +#define __need_size_t +#include + +#include + +extern int write (int, const void *, size_t); +extern int read (int, void *, size_t); +off_t lseek (int, off_t, int); diff --git a/hardware/tools/avr/avr/include/util/atomic.h b/hardware/tools/avr/avr/include/util/atomic.h new file mode 100644 index 0000000000000000000000000000000000000000..fd76e862d2fd20389873e17095eb323ee0ad7b9f --- /dev/null +++ b/hardware/tools/avr/avr/include/util/atomic.h @@ -0,0 +1,308 @@ +/* Copyright (c) 2007 Dean Camera + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +/* $Id$ */ + +#ifndef _UTIL_ATOMIC_H_ +#define _UTIL_ATOMIC_H_ 1 + +#include +#include + +#if !defined(__DOXYGEN__) +/* Internal helper functions. */ +static __inline__ uint8_t __iSeiRetVal(void) +{ + sei(); + return 1; +} + +static __inline__ uint8_t __iCliRetVal(void) +{ + cli(); + return 1; +} + +static __inline__ void __iSeiParam(const uint8_t *__s) +{ + sei(); + __asm__ volatile ("" ::: "memory"); + (void)__s; +} + +static __inline__ void __iCliParam(const uint8_t *__s) +{ + cli(); + __asm__ volatile ("" ::: "memory"); + (void)__s; +} + +static __inline__ void __iRestore(const uint8_t *__s) +{ + SREG = *__s; + __asm__ volatile ("" ::: "memory"); +} +#endif /* !__DOXYGEN__ */ + +/** \file */ +/** \defgroup util_atomic Atomically and Non-Atomically Executed Code Blocks + + \code + #include + \endcode + + \note The macros in this header file require the ISO/IEC 9899:1999 + ("ISO C99") feature of for loop variables that are declared inside + the for loop itself. For that reason, this header file can only + be used if the standard level of the compiler (option --std=) is + set to either \c c99 or \c gnu99. + + The macros in this header file deal with code blocks that are + guaranteed to be excuted Atomically or Non-Atmomically. The term + "Atomic" in this context refers to the unability of the respective + code to be interrupted. + + These macros operate via automatic manipulation of the Global + Interrupt Status (I) bit of the SREG register. Exit paths from + both block types are all managed automatically without the need + for special considerations, i. e. the interrupt status will be + restored to the same value it has been when entering the + respective block. + + A typical example that requires atomic access is a 16 (or more) + bit variable that is shared between the main execution path and an + ISR. While declaring such a variable as volatile ensures that the + compiler will not optimize accesses to it away, it does not + guarantee atomic access to it. Assuming the following example: + + \code +#include +#include +#include + +volatile uint16_t ctr; + +ISR(TIMER1_OVF_vect) +{ + ctr--; +} + +... +int +main(void) +{ + ... + ctr = 0x200; + start_timer(); + while (ctr != 0) + // wait + ; + ... +} + \endcode + + There is a chance where the main context will exit its wait loop + when the variable \c ctr just reached the value 0xFF. This happens + because the compiler cannot natively access a 16-bit variable + atomically in an 8-bit CPU. So the variable is for example at + 0x100, the compiler then tests the low byte for 0, which succeeds. + It then proceeds to test the high byte, but that moment the ISR + triggers, and the main context is interrupted. The ISR will + decrement the variable from 0x100 to 0xFF, and the main context + proceeds. It now tests the high byte of the variable which is + (now) also 0, so it concludes the variable has reached 0, and + terminates the loop. + + Using the macros from this header file, the above code can be + rewritten like: + + \code +#include +#include +#include +#include + +volatile uint16_t ctr; + +ISR(TIMER1_OVF_vect) +{ + ctr--; +} + +... +int +main(void) +{ + ... + ctr = 0x200; + start_timer(); + sei(); + uint16_t ctr_copy; + do + { + ATOMIC_BLOCK(ATOMIC_FORCEON) + { + ctr_copy = ctr; + } + } + while (ctr_copy != 0); + ... +} + \endcode + + This will install the appropriate interrupt protection before + accessing variable \c ctr, so it is guaranteed to be consistently + tested. If the global interrupt state were uncertain before + entering the ATOMIC_BLOCK, it should be executed with the + parameter ATOMIC_RESTORESTATE rather than ATOMIC_FORCEON. + + See \ref optim_code_reorder for things to be taken into account + with respect to compiler optimizations. +*/ + +/** \def ATOMIC_BLOCK(type) + \ingroup util_atomic + + Creates a block of code that is guaranteed to be executed + atomically. Upon entering the block the Global Interrupt Status + flag in SREG is disabled, and re-enabled upon exiting the block + from any exit path. + + Two possible macro parameters are permitted, ATOMIC_RESTORESTATE + and ATOMIC_FORCEON. +*/ +#if defined(__DOXYGEN__) +#define ATOMIC_BLOCK(type) +#else +#define ATOMIC_BLOCK(type) for ( type, __ToDo = __iCliRetVal(); \ + __ToDo ; __ToDo = 0 ) +#endif /* __DOXYGEN__ */ + +/** \def NONATOMIC_BLOCK(type) + \ingroup util_atomic + + Creates a block of code that is executed non-atomically. Upon + entering the block the Global Interrupt Status flag in SREG is + enabled, and disabled upon exiting the block from any exit + path. This is useful when nested inside ATOMIC_BLOCK sections, + allowing for non-atomic execution of small blocks of code while + maintaining the atomic access of the other sections of the parent + ATOMIC_BLOCK. + + Two possible macro parameters are permitted, + NONATOMIC_RESTORESTATE and NONATOMIC_FORCEOFF. +*/ +#if defined(__DOXYGEN__) +#define NONATOMIC_BLOCK(type) +#else +#define NONATOMIC_BLOCK(type) for ( type, __ToDo = __iSeiRetVal(); \ + __ToDo ; __ToDo = 0 ) +#endif /* __DOXYGEN__ */ + +/** \def ATOMIC_RESTORESTATE + \ingroup util_atomic + + This is a possible parameter for ATOMIC_BLOCK. When used, it will + cause the ATOMIC_BLOCK to restore the previous state of the SREG + register, saved before the Global Interrupt Status flag bit was + disabled. The net effect of this is to make the ATOMIC_BLOCK's + contents guaranteed atomic, without changing the state of the + Global Interrupt Status flag when execution of the block + completes. +*/ +#if defined(__DOXYGEN__) +#define ATOMIC_RESTORESTATE +#else +#define ATOMIC_RESTORESTATE uint8_t sreg_save \ + __attribute__((__cleanup__(__iRestore))) = SREG +#endif /* __DOXYGEN__ */ + +/** \def ATOMIC_FORCEON + \ingroup util_atomic + + This is a possible parameter for ATOMIC_BLOCK. When used, it will + cause the ATOMIC_BLOCK to force the state of the SREG register on + exit, enabling the Global Interrupt Status flag bit. This saves on + flash space as the previous value of the SREG register does not + need to be saved at the start of the block. + + Care should be taken that ATOMIC_FORCEON is only used when it is + known that interrupts are enabled before the block's execution or + when the side effects of enabling global interrupts at the block's + completion are known and understood. +*/ +#if defined(__DOXYGEN__) +#define ATOMIC_FORCEON +#else +#define ATOMIC_FORCEON uint8_t sreg_save \ + __attribute__((__cleanup__(__iSeiParam))) = 0 +#endif /* __DOXYGEN__ */ + +/** \def NONATOMIC_RESTORESTATE + \ingroup util_atomic + + This is a possible parameter for NONATOMIC_BLOCK. When used, it + will cause the NONATOMIC_BLOCK to restore the previous state of + the SREG register, saved before the Global Interrupt Status flag + bit was enabled. The net effect of this is to make the + NONATOMIC_BLOCK's contents guaranteed non-atomic, without changing + the state of the Global Interrupt Status flag when execution of + the block completes. +*/ +#if defined(__DOXYGEN__) +#define NONATOMIC_RESTORESTATE +#else +#define NONATOMIC_RESTORESTATE uint8_t sreg_save \ + __attribute__((__cleanup__(__iRestore))) = SREG +#endif /* __DOXYGEN__ */ + +/** \def NONATOMIC_FORCEOFF + \ingroup util_atomic + + This is a possible parameter for NONATOMIC_BLOCK. When used, it + will cause the NONATOMIC_BLOCK to force the state of the SREG + register on exit, disabling the Global Interrupt Status flag + bit. This saves on flash space as the previous value of the SREG + register does not need to be saved at the start of the block. + + Care should be taken that NONATOMIC_FORCEOFF is only used when it + is known that interrupts are disabled before the block's execution + or when the side effects of disabling global interrupts at the + block's completion are known and understood. +*/ +#if defined(__DOXYGEN__) +#define NONATOMIC_FORCEOFF +#else +#define NONATOMIC_FORCEOFF uint8_t sreg_save \ + __attribute__((__cleanup__(__iCliParam))) = 0 +#endif /* __DOXYGEN__ */ + +#endif diff --git a/hardware/tools/avr/avr/include/util/crc16.h b/hardware/tools/avr/avr/include/util/crc16.h new file mode 100644 index 0000000000000000000000000000000000000000..630b6fc99b88a571e5dadab3a6f6cb5af91fe0de --- /dev/null +++ b/hardware/tools/avr/avr/include/util/crc16.h @@ -0,0 +1,403 @@ +/* Copyright (c) 2002, 2003, 2004 Marek Michalkiewicz + Copyright (c) 2005, 2007 Joerg Wunsch + Copyright (c) 2013 Dave Hylands + Copyright (c) 2013 Frederic Nadeau + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _UTIL_CRC16_H_ +#define _UTIL_CRC16_H_ + +#include + +/** \file */ +/** \defgroup util_crc : CRC Computations + \code#include \endcode + + This header file provides a optimized inline functions for calculating + cyclic redundancy checks (CRC) using common polynomials. + + \par References: + + \par + + See the Dallas Semiconductor app note 27 for 8051 assembler example and + general CRC optimization suggestions. The table on the last page of the + app note is the key to understanding these implementations. + + \par + + Jack Crenshaw's "Implementing CRCs" article in the January 1992 isue of \e + Embedded \e Systems \e Programming. This may be difficult to find, but it + explains CRC's in very clear and concise terms. Well worth the effort to + obtain a copy. + + A typical application would look like: + + \code + // Dallas iButton test vector. + uint8_t serno[] = { 0x02, 0x1c, 0xb8, 0x01, 0, 0, 0, 0xa2 }; + + int + checkcrc(void) + { + uint8_t crc = 0, i; + + for (i = 0; i < sizeof serno / sizeof serno[0]; i++) + crc = _crc_ibutton_update(crc, serno[i]); + + return crc; // must be 0 + } + \endcode +*/ + +/** \ingroup util_crc + Optimized CRC-16 calculation. + + Polynomial: x^16 + x^15 + x^2 + 1 (0xa001)
+ Initial value: 0xffff + + This CRC is normally used in disk-drive controllers. + + The following is the equivalent functionality written in C. + + \code + uint16_t + crc16_update(uint16_t crc, uint8_t a) + { + int i; + + crc ^= a; + for (i = 0; i < 8; ++i) + { + if (crc & 1) + crc = (crc >> 1) ^ 0xA001; + else + crc = (crc >> 1); + } + + return crc; + } + + \endcode */ + +static __inline__ uint16_t +_crc16_update(uint16_t __crc, uint8_t __data) +{ + uint8_t __tmp; + uint16_t __ret; + + __asm__ __volatile__ ( + "eor %A0,%2" "\n\t" + "mov %1,%A0" "\n\t" + "swap %1" "\n\t" + "eor %1,%A0" "\n\t" + "mov __tmp_reg__,%1" "\n\t" + "lsr %1" "\n\t" + "lsr %1" "\n\t" + "eor %1,__tmp_reg__" "\n\t" + "mov __tmp_reg__,%1" "\n\t" + "lsr %1" "\n\t" + "eor %1,__tmp_reg__" "\n\t" + "andi %1,0x07" "\n\t" + "mov __tmp_reg__,%A0" "\n\t" + "mov %A0,%B0" "\n\t" + "lsr %1" "\n\t" + "ror __tmp_reg__" "\n\t" + "ror %1" "\n\t" + "mov %B0,__tmp_reg__" "\n\t" + "eor %A0,%1" "\n\t" + "lsr __tmp_reg__" "\n\t" + "ror %1" "\n\t" + "eor %B0,__tmp_reg__" "\n\t" + "eor %A0,%1" + : "=r" (__ret), "=d" (__tmp) + : "r" (__data), "0" (__crc) + : "r0" + ); + return __ret; +} + +/** \ingroup util_crc + Optimized CRC-XMODEM calculation. + + Polynomial: x^16 + x^12 + x^5 + 1 (0x1021)
+ Initial value: 0x0 + + This is the CRC used by the Xmodem-CRC protocol. + + The following is the equivalent functionality written in C. + + \code + uint16_t + crc_xmodem_update (uint16_t crc, uint8_t data) + { + int i; + + crc = crc ^ ((uint16_t)data << 8); + for (i=0; i<8; i++) + { + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc <<= 1; + } + + return crc; + } + \endcode */ + +static __inline__ uint16_t +_crc_xmodem_update(uint16_t __crc, uint8_t __data) +{ + uint16_t __ret; /* %B0:%A0 (alias for __crc) */ + uint8_t __tmp1; /* %1 */ + uint8_t __tmp2; /* %2 */ + /* %3 __data */ + + __asm__ __volatile__ ( + "eor %B0,%3" "\n\t" /* crc.hi ^ data */ + "mov __tmp_reg__,%B0" "\n\t" + "swap __tmp_reg__" "\n\t" /* swap(crc.hi ^ data) */ + + /* Calculate the ret.lo of the CRC. */ + "mov %1,__tmp_reg__" "\n\t" + "andi %1,0x0f" "\n\t" + "eor %1,%B0" "\n\t" + "mov %2,%B0" "\n\t" + "eor %2,__tmp_reg__" "\n\t" + "lsl %2" "\n\t" + "andi %2,0xe0" "\n\t" + "eor %1,%2" "\n\t" /* __tmp1 is now ret.lo. */ + + /* Calculate the ret.hi of the CRC. */ + "mov %2,__tmp_reg__" "\n\t" + "eor %2,%B0" "\n\t" + "andi %2,0xf0" "\n\t" + "lsr %2" "\n\t" + "mov __tmp_reg__,%B0" "\n\t" + "lsl __tmp_reg__" "\n\t" + "rol %2" "\n\t" + "lsr %B0" "\n\t" + "lsr %B0" "\n\t" + "lsr %B0" "\n\t" + "andi %B0,0x1f" "\n\t" + "eor %B0,%2" "\n\t" + "eor %B0,%A0" "\n\t" /* ret.hi is now ready. */ + "mov %A0,%1" "\n\t" /* ret.lo is now ready. */ + : "=d" (__ret), "=d" (__tmp1), "=d" (__tmp2) + : "r" (__data), "0" (__crc) + : "r0" + ); + return __ret; +} + +/** \ingroup util_crc + Optimized CRC-CCITT calculation. + + Polynomial: x^16 + x^12 + x^5 + 1 (0x8408)
+ Initial value: 0xffff + + This is the CRC used by PPP and IrDA. + + See RFC1171 (PPP protocol) and IrDA IrLAP 1.1 + + \note Although the CCITT polynomial is the same as that used by the Xmodem + protocol, they are quite different. The difference is in how the bits are + shifted through the alorgithm. Xmodem shifts the MSB of the CRC and the + input first, while CCITT shifts the LSB of the CRC and the input first. + + The following is the equivalent functionality written in C. + + \code + uint16_t + crc_ccitt_update (uint16_t crc, uint8_t data) + { + data ^= lo8 (crc); + data ^= data << 4; + + return ((((uint16_t)data << 8) | hi8 (crc)) ^ (uint8_t)(data >> 4) + ^ ((uint16_t)data << 3)); + } + \endcode */ + +static __inline__ uint16_t +_crc_ccitt_update (uint16_t __crc, uint8_t __data) +{ + uint16_t __ret; + + __asm__ __volatile__ ( + "eor %A0,%1" "\n\t" + + "mov __tmp_reg__,%A0" "\n\t" + "swap %A0" "\n\t" + "andi %A0,0xf0" "\n\t" + "eor %A0,__tmp_reg__" "\n\t" + + "mov __tmp_reg__,%B0" "\n\t" + + "mov %B0,%A0" "\n\t" + + "swap %A0" "\n\t" + "andi %A0,0x0f" "\n\t" + "eor __tmp_reg__,%A0" "\n\t" + + "lsr %A0" "\n\t" + "eor %B0,%A0" "\n\t" + + "eor %A0,%B0" "\n\t" + "lsl %A0" "\n\t" + "lsl %A0" "\n\t" + "lsl %A0" "\n\t" + "eor %A0,__tmp_reg__" + + : "=d" (__ret) + : "r" (__data), "0" (__crc) + : "r0" + ); + return __ret; +} + +/** \ingroup util_crc + Optimized Dallas (now Maxim) iButton 8-bit CRC calculation. + + Polynomial: x^8 + x^5 + x^4 + 1 (0x8C)
+ Initial value: 0x0 + + See http://www.maxim-ic.com/appnotes.cfm/appnote_number/27 + + The following is the equivalent functionality written in C. + + \code + uint8_t + _crc_ibutton_update(uint8_t crc, uint8_t data) + { + uint8_t i; + + crc = crc ^ data; + for (i = 0; i < 8; i++) + { + if (crc & 0x01) + crc = (crc >> 1) ^ 0x8C; + else + crc >>= 1; + } + + return crc; + } + \endcode +*/ + +static __inline__ uint8_t +_crc_ibutton_update(uint8_t __crc, uint8_t __data) +{ + uint8_t __i, __pattern; + __asm__ __volatile__ ( + " eor %0, %4" "\n\t" + " ldi %1, 8" "\n\t" + " ldi %2, 0x8C" "\n\t" + "1: lsr %0" "\n\t" + " brcc 2f" "\n\t" + " eor %0, %2" "\n\t" + "2: dec %1" "\n\t" + " brne 1b" "\n\t" + : "=r" (__crc), "=d" (__i), "=d" (__pattern) + : "0" (__crc), "r" (__data)); + return __crc; +} + +/** \ingroup util_crc + Optimized CRC-8-CCITT calculation. + + Polynomial: x^8 + x^2 + x + 1 (0xE0)
+ + For use with simple CRC-8
+ Initial value: 0x0 + + For use with CRC-8-ROHC
+ Initial value: 0xff
+ Reference: http://tools.ietf.org/html/rfc3095#section-5.9.1 + + For use with CRC-8-ATM/ITU
+ Initial value: 0xff
+ Final XOR value: 0x55
+ Reference: http://www.itu.int/rec/T-REC-I.432.1-199902-I/en + + The C equivalent has been originally written by Dave Hylands. + Assembly code is based on _crc_ibutton_update optimization. + + The following is the equivalent functionality written in C. + + \code + uint8_t + _crc8_ccitt_update (uint8_t inCrc, uint8_t inData) + { + uint8_t i; + uint8_t data; + + data = inCrc ^ inData; + + for ( i = 0; i < 8; i++ ) + { + if (( data & 0x80 ) != 0 ) + { + data <<= 1; + data ^= 0x07; + } + else + { + data <<= 1; + } + } + return data; + } + \endcode +*/ + +static __inline__ uint8_t +_crc8_ccitt_update(uint8_t __crc, uint8_t __data) +{ + uint8_t __i, __pattern; + __asm__ __volatile__ ( + " eor %0, %4" "\n\t" + " ldi %1, 8" "\n\t" + " ldi %2, 0x07" "\n\t" + "1: lsl %0" "\n\t" + " brcc 2f" "\n\t" + " eor %0, %2" "\n\t" + "2: dec %1" "\n\t" + " brne 1b" "\n\t" + : "=r" (__crc), "=d" (__i), "=d" (__pattern) + : "0" (__crc), "r" (__data)); + return __crc; +} + +#endif /* _UTIL_CRC16_H_ */ diff --git a/hardware/tools/avr/avr/include/util/delay.h b/hardware/tools/avr/avr/include/util/delay.h new file mode 100644 index 0000000000000000000000000000000000000000..6313536ccee1bd741b56d5703de3c7e49176d1aa --- /dev/null +++ b/hardware/tools/avr/avr/include/util/delay.h @@ -0,0 +1,302 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + Copyright (c) 2004,2005,2007 Joerg Wunsch + Copyright (c) 2007 Florin-Viorel Petrov + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _UTIL_DELAY_H_ +#define _UTIL_DELAY_H_ 1 + +#ifndef __DOXYGEN__ +# ifndef __HAS_DELAY_CYCLES +# define __HAS_DELAY_CYCLES 1 +# endif +#endif /* __DOXYGEN__ */ + +#include +#include +#include + +/** \file */ +/** \defgroup util_delay : Convenience functions for busy-wait delay loops + \code + #define F_CPU 1000000UL // 1 MHz + //#define F_CPU 14.7456E6 + #include + \endcode + + \note As an alternative method, it is possible to pass the + F_CPU macro down to the compiler from the Makefile. + Obviously, in that case, no \c \#define statement should be + used. + + The functions in this header file are wrappers around the basic + busy-wait functions from . They are meant as + convenience functions where actual time values can be specified + rather than a number of cycles to wait for. The idea behind is + that compile-time constant expressions will be eliminated by + compiler optimization so floating-point expressions can be used + to calculate the number of delay cycles needed based on the CPU + frequency passed by the macro F_CPU. + + \note In order for these functions to work as intended, compiler + optimizations must be enabled, and the delay time + must be an expression that is a known constant at + compile-time. If these requirements are not met, the resulting + delay will be much longer (and basically unpredictable), and + applications that otherwise do not use floating-point calculations + will experience severe code bloat by the floating-point library + routines linked into the application. + + The functions available allow the specification of microsecond, and + millisecond delays directly, using the application-supplied macro + F_CPU as the CPU clock frequency (in Hertz). + +*/ + +#if !defined(__DOXYGEN__) +static __inline__ void _delay_us(double __us) __attribute__((__always_inline__)); +static __inline__ void _delay_ms(double __ms) __attribute__((__always_inline__)); +#endif + +#ifndef F_CPU +/* prevent compiler error by supplying a default */ +# warning "F_CPU not defined for " +/** \ingroup util_delay + \def F_CPU + \brief CPU frequency in Hz + + The macro F_CPU specifies the CPU frequency to be considered by + the delay macros. This macro is normally supplied by the + environment (e.g. from within a project header, or the project's + Makefile). The value 1 MHz here is only provided as a "vanilla" + fallback if no such user-provided definition could be found. + + In terms of the delay functions, the CPU frequency can be given as + a floating-point constant (e.g. 3.6864E6 for 3.6864 MHz). + However, the macros in require it to be an + integer value. + */ +# define F_CPU 1000000UL +#endif + +#ifndef __OPTIMIZE__ +# warning "Compiler optimizations disabled; functions from won't work as designed" +#endif + +#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ + !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ + __STDC_HOSTED__ +# include +#endif + +/** + \ingroup util_delay + + Perform a delay of \c __ms milliseconds, using _delay_loop_2(). + + The macro F_CPU is supposed to be defined to a + constant defining the CPU clock frequency (in Hertz). + + The maximal possible delay is 262.14 ms / F_CPU in MHz. + + When the user request delay which exceed the maximum possible one, + _delay_ms() provides a decreased resolution functionality. In this + mode _delay_ms() will work with a resolution of 1/10 ms, providing + delays up to 6.5535 seconds (independent from CPU frequency). The + user will not be informed about decreased resolution. + + If the avr-gcc toolchain has __builtin_avr_delay_cycles() + support, maximal possible delay is 4294967.295 ms/ F_CPU in MHz. For + values greater than the maximal possible delay, overflows results in + no delay i.e., 0ms. + + Conversion of \c __ms into clock cycles may not always result in + integer. By default, the clock cycles rounded up to next + integer. This ensures that the user gets at least \c __ms + microseconds of delay. + + Alternatively, by defining the macro \c __DELAY_ROUND_DOWN__, or + \c __DELAY_ROUND_CLOSEST__, before including this header file, the + algorithm can be made to round down, or round to closest integer, + respectively. + + \note + + The implementation of _delay_ms() based on + __builtin_avr_delay_cycles() is not backward compatible with older + implementations. In order to get functionality backward compatible + with previous versions, the macro \c "__DELAY_BACKWARD_COMPATIBLE__" + must be defined before including this header file. Also, the + backward compatible algorithm will be chosen if the code is + compiled in a freestanding environment (GCC option + \c -ffreestanding), as the math functions required for rounding are + not available to the compiler then. + + */ +void +_delay_ms(double __ms) +{ + double __tmp ; +#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ + !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ + __STDC_HOSTED__ + uint32_t __ticks_dc; + extern void __builtin_avr_delay_cycles(unsigned long); + __tmp = ((F_CPU) / 1e3) * __ms; + + #if defined(__DELAY_ROUND_DOWN__) + __ticks_dc = (uint32_t)fabs(__tmp); + + #elif defined(__DELAY_ROUND_CLOSEST__) + __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); + + #else + //round up by default + __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); + #endif + + __builtin_avr_delay_cycles(__ticks_dc); + +#else + uint16_t __ticks; + __tmp = ((F_CPU) / 4e3) * __ms; + if (__tmp < 1.0) + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + } + return; + } + else + __ticks = (uint16_t)__tmp; + _delay_loop_2(__ticks); +#endif +} + +/** + \ingroup util_delay + + Perform a delay of \c __us microseconds, using _delay_loop_1(). + + The macro F_CPU is supposed to be defined to a + constant defining the CPU clock frequency (in Hertz). + + The maximal possible delay is 768 us / F_CPU in MHz. + + If the user requests a delay greater than the maximal possible one, + _delay_us() will automatically call _delay_ms() instead. The user + will not be informed about this case. + + If the avr-gcc toolchain has __builtin_avr_delay_cycles() + support, maximal possible delay is 4294967.295 us/ F_CPU in MHz. For + values greater than the maximal possible delay, overflow results in + no delay i.e., 0us. + + Conversion of \c __us into clock cycles may not always result in + integer. By default, the clock cycles rounded up to next + integer. This ensures that the user gets at least \c __us + microseconds of delay. + + Alternatively, by defining the macro \c __DELAY_ROUND_DOWN__, or + \c __DELAY_ROUND_CLOSEST__, before including this header file, the + algorithm can be made to round down, or round to closest integer, + respectively. + + \note + + The implementation of _delay_ms() based on + __builtin_avr_delay_cycles() is not backward compatible with older + implementations. In order to get functionality backward compatible + with previous versions, the macro \c __DELAY_BACKWARD_COMPATIBLE__ + must be defined before including this header file. Also, the + backward compatible algorithm will be chosen if the code is + compiled in a freestanding environment (GCC option + \c -ffreestanding), as the math functions required for rounding are + not available to the compiler then. + + */ +void +_delay_us(double __us) +{ + double __tmp ; +#if __HAS_DELAY_CYCLES && defined(__OPTIMIZE__) && \ + !defined(__DELAY_BACKWARD_COMPATIBLE__) && \ + __STDC_HOSTED__ + uint32_t __ticks_dc; + extern void __builtin_avr_delay_cycles(unsigned long); + __tmp = ((F_CPU) / 1e6) * __us; + + #if defined(__DELAY_ROUND_DOWN__) + __ticks_dc = (uint32_t)fabs(__tmp); + + #elif defined(__DELAY_ROUND_CLOSEST__) + __ticks_dc = (uint32_t)(fabs(__tmp)+0.5); + + #else + //round up by default + __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); + #endif + + __builtin_avr_delay_cycles(__ticks_dc); + +#else + uint8_t __ticks; + double __tmp2 ; + __tmp = ((F_CPU) / 3e6) * __us; + __tmp2 = ((F_CPU) / 4e6) * __us; + if (__tmp < 1.0) + __ticks = 1; + else if (__tmp2 > 65535) + { + _delay_ms(__us / 1000.0); + } + else if (__tmp > 255) + { + uint16_t __ticks=(uint16_t)__tmp2; + _delay_loop_2(__ticks); + return; + } + else + __ticks = (uint8_t)__tmp; + _delay_loop_1(__ticks); +#endif +} + + +#endif /* _UTIL_DELAY_H_ */ diff --git a/hardware/tools/avr/avr/include/util/delay_basic.h b/hardware/tools/avr/avr/include/util/delay_basic.h new file mode 100644 index 0000000000000000000000000000000000000000..9bf1e4598c74a95519018f6efb6278983288edd1 --- /dev/null +++ b/hardware/tools/avr/avr/include/util/delay_basic.h @@ -0,0 +1,113 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + Copyright (c) 2007 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _UTIL_DELAY_BASIC_H_ +#define _UTIL_DELAY_BASIC_H_ 1 + +#include + +#if !defined(__DOXYGEN__) +static __inline__ void _delay_loop_1(uint8_t __count) __attribute__((__always_inline__)); +static __inline__ void _delay_loop_2(uint16_t __count) __attribute__((__always_inline__)); +#endif + +/** \file */ +/** \defgroup util_delay_basic : Basic busy-wait delay loops + \code + #include + \endcode + + The functions in this header file implement simple delay loops + that perform a busy-waiting. They are typically used to + facilitate short delays in the program execution. They are + implemented as count-down loops with a well-known CPU cycle + count per loop iteration. As such, no other processing can + occur simultaneously. It should be kept in mind that the + functions described here do not disable interrupts. + + In general, for long delays, the use of hardware timers is + much preferrable, as they free the CPU, and allow for + concurrent processing of other events while the timer is + running. However, in particular for very short delays, the + overhead of setting up a hardware timer is too much compared + to the overall delay time. + + Two inline functions are provided for the actual delay algorithms. + +*/ + +/** \ingroup util_delay_basic + + Delay loop using an 8-bit counter \c __count, so up to 256 + iterations are possible. (The value 256 would have to be passed + as 0.) The loop executes three CPU cycles per iteration, not + including the overhead the compiler needs to setup the counter + register. + + Thus, at a CPU speed of 1 MHz, delays of up to 768 microseconds + can be achieved. +*/ +void +_delay_loop_1(uint8_t __count) +{ + __asm__ volatile ( + "1: dec %0" "\n\t" + "brne 1b" + : "=r" (__count) + : "0" (__count) + ); +} + +/** \ingroup util_delay_basic + + Delay loop using a 16-bit counter \c __count, so up to 65536 + iterations are possible. (The value 65536 would have to be + passed as 0.) The loop executes four CPU cycles per iteration, + not including the overhead the compiler requires to setup the + counter register pair. + + Thus, at a CPU speed of 1 MHz, delays of up to about 262.1 + milliseconds can be achieved. + */ +void +_delay_loop_2(uint16_t __count) +{ + __asm__ volatile ( + "1: sbiw %0,1" "\n\t" + "brne 1b" + : "=w" (__count) + : "0" (__count) + ); +} + +#endif /* _UTIL_DELAY_BASIC_H_ */ diff --git a/hardware/tools/avr/avr/include/util/eu_dst.h b/hardware/tools/avr/avr/include/util/eu_dst.h new file mode 100644 index 0000000000000000000000000000000000000000..eee7f613236cc0dee3ad864ff765a306d3158cd1 --- /dev/null +++ b/hardware/tools/avr/avr/include/util/eu_dst.h @@ -0,0 +1,116 @@ +/* + * (c)2012 Michael Duane Rice All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. Redistributions in binary + * form must reproduce the above copyright notice, this list of conditions + * and the following disclaimer in the documentation and/or other materials + * provided with the distribution. Neither the name of the copyright holders + * nor the names of contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* $Id$ */ + +/** + Daylight Saving function for the European Union. To utilize this function, you must + \code #include \endcode + and + \code set_dst(eu_dst); \endcode + + Given the time stamp and time zone parameters provided, the Daylight Saving function must + return a value appropriate for the tm structures' tm_isdst element. That is... + + 0 : If Daylight Saving is not in effect. + + -1 : If it cannot be determined if Daylight Saving is in effect. + + A positive integer : Represents the number of seconds a clock is advanced for Daylight Saving. + This will typically be ONE_HOUR. + + Daylight Saving 'rules' are subject to frequent change. For production applications it is + recommended to write your own DST function, which uses 'rules' obtained from, and modifiable by, + the end user ( perhaps stored in EEPROM ). +*/ + +#ifndef EU_DST_H +#define EU_DST_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + + int eu_dst(const time_t * timer, int32_t * z) { + struct tm tmptr; + uint8_t month, mday, hour, day_of_week, d; + int n; + + /* obtain the variables */ + gmtime_r(timer, &tmptr); + month = tmptr.tm_mon; + day_of_week = tmptr.tm_wday; + mday = tmptr.tm_mday - 1; + hour = tmptr.tm_hour; + + if ((month > MARCH) && (month < OCTOBER)) + return ONE_HOUR; + + if (month < MARCH) + return 0; + if (month > OCTOBER) + return 0; + + /* determine mday of last Sunday */ + n = tmptr.tm_mday - 1; + n -= day_of_week; + n += 7; + d = n % 7; /* date of first Sunday */ + + n = 31 - d; + n /= 7; /* number of Sundays left in the month */ + + d = d + 7 * n; /* mday of final Sunday */ + + if (month == MARCH) { + if (d < mday) + return 0; + if (d > mday) + return ONE_HOUR; + if (hour < 2) + return 0; + return ONE_HOUR; + } + if (d < mday) + return ONE_HOUR; + if (d > mday) + return 0; + if (hour < 2) + return ONE_HOUR; + return 0; + + } + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/tools/avr/avr/include/util/parity.h b/hardware/tools/avr/avr/include/util/parity.h new file mode 100644 index 0000000000000000000000000000000000000000..b28813e74e070d81bca8546395bbe70ea1616035 --- /dev/null +++ b/hardware/tools/avr/avr/include/util/parity.h @@ -0,0 +1,65 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + Copyright (c) 2004,2005,2007 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +#ifndef _UTIL_PARITY_H_ +#define _UTIL_PARITY_H_ + +/** \file */ +/** \defgroup util_parity : Parity bit generation + \code #include \endcode + + This header file contains optimized assembler code to calculate + the parity bit for a byte. +*/ +/** \def parity_even_bit + \ingroup util_parity + \returns 1 if \c val has an odd number of bits set. */ +#define parity_even_bit(val) \ +(__extension__({ \ + unsigned char __t; \ + __asm__ ( \ + "mov __tmp_reg__,%0" "\n\t" \ + "swap %0" "\n\t" \ + "eor %0,__tmp_reg__" "\n\t" \ + "mov __tmp_reg__,%0" "\n\t" \ + "lsr %0" "\n\t" \ + "lsr %0" "\n\t" \ + "eor %0,__tmp_reg__" \ + : "=r" (__t) \ + : "0" ((unsigned char)(val)) \ + : "r0" \ + ); \ + (((__t + 1) >> 1) & 1); \ + })) + +#endif /* _UTIL_PARITY_H_ */ diff --git a/hardware/tools/avr/avr/include/util/setbaud.h b/hardware/tools/avr/avr/include/util/setbaud.h new file mode 100644 index 0000000000000000000000000000000000000000..c774638da7ad3653878882a88b2db3a5051b0c3d --- /dev/null +++ b/hardware/tools/avr/avr/include/util/setbaud.h @@ -0,0 +1,243 @@ +/* Copyright (c) 2007 Cliff Lawson + Copyright (c) 2007 Carlos Lamas + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ + +/** + \file +*/ + +/** + \defgroup util_setbaud : Helper macros for baud rate calculations + \code + #define F_CPU 11059200 + #define BAUD 38400 + #include + \endcode + + This header file requires that on entry values are already defined + for F_CPU and BAUD. In addition, the macro BAUD_TOL will define + the baud rate tolerance (in percent) that is acceptable during + the calculations. The value of BAUD_TOL will default to 2 %. + + This header file defines macros suitable to setup the UART baud + rate prescaler registers of an AVR. All calculations are done + using the C preprocessor. Including this header file causes no + other side effects so it is possible to include this file more than + once (supposedly, with different values for the BAUD parameter), + possibly even within the same function. + + Assuming that the requested BAUD is valid for the given F_CPU then + the macro UBRR_VALUE is set to the required prescaler value. Two + additional macros are provided for the low and high bytes of the + prescaler, respectively: UBRRL_VALUE is set to the lower byte of + the UBRR_VALUE and UBRRH_VALUE is set to the upper byte. An + additional macro USE_2X will be defined. Its value is set to 1 if + the desired BAUD rate within the given tolerance could only be + achieved by setting the U2X bit in the UART configuration. It will + be defined to 0 if U2X is not needed. + + Example usage: + + \code + #include + + #define F_CPU 4000000 + + static void + uart_9600(void) + { + #define BAUD 9600 + #include + UBRRH = UBRRH_VALUE; + UBRRL = UBRRL_VALUE; + #if USE_2X + UCSRA |= (1 << U2X); + #else + UCSRA &= ~(1 << U2X); + #endif + } + + static void + uart_38400(void) + { + #undef BAUD // avoid compiler warning + #define BAUD 38400 + #include + UBRRH = UBRRH_VALUE; + UBRRL = UBRRL_VALUE; + #if USE_2X + UCSRA |= (1 << U2X); + #else + UCSRA &= ~(1 << U2X); + #endif + } + \endcode + + In this example, two functions are defined to setup the UART + to run at 9600 Bd, and 38400 Bd, respectively. Using a CPU + clock of 4 MHz, 9600 Bd can be achieved with an acceptable + tolerance without setting U2X (prescaler 25), while 38400 Bd + require U2X to be set (prescaler 12). +*/ + +#ifndef F_CPU +# error "setbaud.h requires F_CPU to be defined" +#endif + +#ifndef BAUD +# error "setbaud.h requires BAUD to be defined" +#endif + +#if !(F_CPU) +# error "F_CPU must be a constant value" +#endif + +#if !(BAUD) +# error "BAUD must be a constant value" +#endif + +#if defined(__DOXYGEN__) +/** + \def BAUD_TOL + \ingroup util_setbaud + + Input and output macro for + + Define the acceptable baud rate tolerance in percent. If not set + on entry, it will be set to its default value of 2. +*/ +#define BAUD_TOL 2 + +/** + \def UBRR_VALUE + \ingroup util_setbaud + + Output macro from + + Contains the calculated baud rate prescaler value for the UBRR + register. +*/ +#define UBRR_VALUE + +/** + \def UBRRL_VALUE + \ingroup util_setbaud + + Output macro from + + Contains the lower byte of the calculated prescaler value + (UBRR_VALUE). +*/ +#define UBRRL_VALUE + +/** + \def UBRRH_VALUE + \ingroup util_setbaud + + Output macro from + + Contains the upper byte of the calculated prescaler value + (UBRR_VALUE). +*/ +#define UBRRH_VALUE + +/** + \def USE_2X + \ingroup util_setbaud + + Output macro from + + Contains the value 1 if the desired baud rate tolerance could only + be achieved by setting the U2X bit in the UART configuration. + Contains 0 otherwise. +*/ +#define USE_2X 0 + +#else /* !__DOXYGEN__ */ + +#undef USE_2X + +/* Baud rate tolerance is 2 % unless previously defined */ +#ifndef BAUD_TOL +# define BAUD_TOL 2 +#endif + +#ifdef __ASSEMBLER__ +#define UBRR_VALUE (((F_CPU) + 8 * (BAUD)) / (16 * (BAUD)) -1) +#else +#define UBRR_VALUE (((F_CPU) + 8UL * (BAUD)) / (16UL * (BAUD)) -1UL) +#endif + +#if 100 * (F_CPU) > \ + (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) +# define USE_2X 1 +#elif 100 * (F_CPU) < \ + (16 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) +# define USE_2X 1 +#else +# define USE_2X 0 +#endif + +#if USE_2X +/* U2X required, recalculate */ +#undef UBRR_VALUE + +#ifdef __ASSEMBLER__ +#define UBRR_VALUE (((F_CPU) + 4 * (BAUD)) / (8 * (BAUD)) -1) +#else +#define UBRR_VALUE (((F_CPU) + 4UL * (BAUD)) / (8UL * (BAUD)) -1UL) +#endif + +#if 100 * (F_CPU) > \ + (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) + (BAUD) * (BAUD_TOL)) +# warning "Baud rate achieved is higher than allowed" +#endif + +#if 100 * (F_CPU) < \ + (8 * ((UBRR_VALUE) + 1)) * (100 * (BAUD) - (BAUD) * (BAUD_TOL)) +# warning "Baud rate achieved is lower than allowed" +#endif + +#endif /* USE_U2X */ + +#ifdef UBRR_VALUE + /* Check for overflow */ +# if UBRR_VALUE >= (1 << 12) +# warning "UBRR value overflow" +# endif + +# define UBRRL_VALUE (UBRR_VALUE & 0xff) +# define UBRRH_VALUE (UBRR_VALUE >> 8) +#endif + +#endif /* __DOXYGEN__ */ +/* end of util/setbaud.h */ diff --git a/hardware/tools/avr/avr/include/util/twi.h b/hardware/tools/avr/avr/include/util/twi.h new file mode 100644 index 0000000000000000000000000000000000000000..14bc8308323c0b2c0bf67e6fb97cb7ac7510e009 --- /dev/null +++ b/hardware/tools/avr/avr/include/util/twi.h @@ -0,0 +1,237 @@ +/* Copyright (c) 2002, Marek Michalkiewicz + Copyright (c) 2005, 2007 Joerg Wunsch + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. */ + +/* $Id$ */ +/* copied from: Id: avr/twi.h,v 1.4 2004/11/01 21:19:54 arcanum Exp */ + +#ifndef _UTIL_TWI_H_ +#define _UTIL_TWI_H_ 1 + +#include + +/** \file */ +/** \defgroup util_twi : TWI bit mask definitions + \code #include \endcode + + This header file contains bit mask definitions for use with + the AVR TWI interface. +*/ +/** \name TWSR values + + Mnemonics: +
TW_MT_xxx - master transmitter +
TW_MR_xxx - master receiver +
TW_ST_xxx - slave transmitter +
TW_SR_xxx - slave receiver + */ + +/*@{*/ +/* Master */ +/** \ingroup util_twi + \def TW_START + start condition transmitted */ +#define TW_START 0x08 + +/** \ingroup util_twi + \def TW_REP_START + repeated start condition transmitted */ +#define TW_REP_START 0x10 + +/* Master Transmitter */ +/** \ingroup util_twi + \def TW_MT_SLA_ACK + SLA+W transmitted, ACK received */ +#define TW_MT_SLA_ACK 0x18 + +/** \ingroup util_twi + \def TW_MT_SLA_NACK + SLA+W transmitted, NACK received */ +#define TW_MT_SLA_NACK 0x20 + +/** \ingroup util_twi + \def TW_MT_DATA_ACK + data transmitted, ACK received */ +#define TW_MT_DATA_ACK 0x28 + +/** \ingroup util_twi + \def TW_MT_DATA_NACK + data transmitted, NACK received */ +#define TW_MT_DATA_NACK 0x30 + +/** \ingroup util_twi + \def TW_MT_ARB_LOST + arbitration lost in SLA+W or data */ +#define TW_MT_ARB_LOST 0x38 + +/* Master Receiver */ +/** \ingroup util_twi + \def TW_MR_ARB_LOST + arbitration lost in SLA+R or NACK */ +#define TW_MR_ARB_LOST 0x38 + +/** \ingroup util_twi + \def TW_MR_SLA_ACK + SLA+R transmitted, ACK received */ +#define TW_MR_SLA_ACK 0x40 + +/** \ingroup util_twi + \def TW_MR_SLA_NACK + SLA+R transmitted, NACK received */ +#define TW_MR_SLA_NACK 0x48 + +/** \ingroup util_twi + \def TW_MR_DATA_ACK + data received, ACK returned */ +#define TW_MR_DATA_ACK 0x50 + +/** \ingroup util_twi + \def TW_MR_DATA_NACK + data received, NACK returned */ +#define TW_MR_DATA_NACK 0x58 + +/* Slave Transmitter */ +/** \ingroup util_twi + \def TW_ST_SLA_ACK + SLA+R received, ACK returned */ +#define TW_ST_SLA_ACK 0xA8 + +/** \ingroup util_twi + \def TW_ST_ARB_LOST_SLA_ACK + arbitration lost in SLA+RW, SLA+R received, ACK returned */ +#define TW_ST_ARB_LOST_SLA_ACK 0xB0 + +/** \ingroup util_twi + \def TW_ST_DATA_ACK + data transmitted, ACK received */ +#define TW_ST_DATA_ACK 0xB8 + +/** \ingroup util_twi + \def TW_ST_DATA_NACK + data transmitted, NACK received */ +#define TW_ST_DATA_NACK 0xC0 + +/** \ingroup util_twi + \def TW_ST_LAST_DATA + last data byte transmitted, ACK received */ +#define TW_ST_LAST_DATA 0xC8 + +/* Slave Receiver */ +/** \ingroup util_twi + \def TW_SR_SLA_ACK + SLA+W received, ACK returned */ +#define TW_SR_SLA_ACK 0x60 + +/** \ingroup util_twi + \def TW_SR_ARB_LOST_SLA_ACK + arbitration lost in SLA+RW, SLA+W received, ACK returned */ +#define TW_SR_ARB_LOST_SLA_ACK 0x68 + +/** \ingroup util_twi + \def TW_SR_GCALL_ACK + general call received, ACK returned */ +#define TW_SR_GCALL_ACK 0x70 + +/** \ingroup util_twi + \def TW_SR_ARB_LOST_GCALL_ACK + arbitration lost in SLA+RW, general call received, ACK returned */ +#define TW_SR_ARB_LOST_GCALL_ACK 0x78 + +/** \ingroup util_twi + \def TW_SR_DATA_ACK + data received, ACK returned */ +#define TW_SR_DATA_ACK 0x80 + +/** \ingroup util_twi + \def TW_SR_DATA_NACK + data received, NACK returned */ +#define TW_SR_DATA_NACK 0x88 + +/** \ingroup util_twi + \def TW_SR_GCALL_DATA_ACK + general call data received, ACK returned */ +#define TW_SR_GCALL_DATA_ACK 0x90 + +/** \ingroup util_twi + \def TW_SR_GCALL_DATA_NACK + general call data received, NACK returned */ +#define TW_SR_GCALL_DATA_NACK 0x98 + +/** \ingroup util_twi + \def TW_SR_STOP + stop or repeated start condition received while selected */ +#define TW_SR_STOP 0xA0 + +/* Misc */ +/** \ingroup util_twi + \def TW_NO_INFO + no state information available */ +#define TW_NO_INFO 0xF8 + +/** \ingroup util_twi + \def TW_BUS_ERROR + illegal start or stop condition */ +#define TW_BUS_ERROR 0x00 + + +/** + * \ingroup util_twi + * \def TW_STATUS_MASK + * The lower 3 bits of TWSR are reserved on the ATmega163. + * The 2 LSB carry the prescaler bits on the newer ATmegas. + */ +#define TW_STATUS_MASK (_BV(TWS7)|_BV(TWS6)|_BV(TWS5)|_BV(TWS4)|\ + _BV(TWS3)) +/** + * \ingroup util_twi + * \def TW_STATUS + * + * TWSR, masked by TW_STATUS_MASK + */ +#define TW_STATUS (TWSR & TW_STATUS_MASK) +/*@}*/ + +/** + * \name R/~W bit in SLA+R/W address field. + */ + +/*@{*/ +/** \ingroup util_twi + \def TW_READ + SLA+R address */ +#define TW_READ 1 + +/** \ingroup util_twi + \def TW_WRITE + SLA+W address */ +#define TW_WRITE 0 +/*@}*/ + +#endif /* _UTIL_TWI_H_ */ diff --git a/hardware/tools/avr/avr/include/util/usa_dst.h b/hardware/tools/avr/avr/include/util/usa_dst.h new file mode 100644 index 0000000000000000000000000000000000000000..bf2165677d8f98601817611a6cbd0756ca8f5d38 --- /dev/null +++ b/hardware/tools/avr/avr/include/util/usa_dst.h @@ -0,0 +1,130 @@ +/* + * (c)2012 Michael Duane Rice All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. Redistributions in binary + * form must reproduce the above copyright notice, this list of conditions + * and the following disclaimer in the documentation and/or other materials + * provided with the distribution. Neither the name of the copyright holders + * nor the names of contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* $Id$ */ + +/** + Daylight Saving function for the USA. To utilize this function, you must + \code #include \endcode + and + \code set_dst(usa_dst); \endcode + + Given the time stamp and time zone parameters provided, the Daylight Saving function must + return a value appropriate for the tm structures' tm_isdst element. That is... + + 0 : If Daylight Saving is not in effect. + + -1 : If it cannot be determined if Daylight Saving is in effect. + + A positive integer : Represents the number of seconds a clock is advanced for Daylight Saving. + This will typically be ONE_HOUR. + + Daylight Saving 'rules' are subject to frequent change. For production applications it is + recommended to write your own DST function, which uses 'rules' obtained from, and modifiable by, + the end user ( perhaps stored in EEPROM ). + +*/ + +#ifndef USA_DST_H +#define USA_DST_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#ifndef DST_START_MONTH +#define DST_START_MONTH MARCH +#endif + +#ifndef DST_END_MONTH +#define DST_END_MONTH NOVEMBER +#endif + +#ifndef DST_START_WEEK +#define DST_START_WEEK 2 +#endif + +#ifndef DST_END_WEEK +#define DST_END_WEEK 1 +#endif + + int usa_dst(const time_t * timer, int32_t * z) { + time_t t; + struct tm tmptr; + uint8_t month, week, hour, day_of_week, d; + int n; + + /* obtain the variables */ + t = *timer + *z; + gmtime_r(&t, &tmptr); + month = tmptr.tm_mon; + day_of_week = tmptr.tm_wday; + week = week_of_month(&tmptr, 0); + hour = tmptr.tm_hour; + + if ((month > DST_START_MONTH) && (month < DST_END_MONTH)) + return ONE_HOUR; + + if (month < DST_START_MONTH) + return 0; + if (month > DST_END_MONTH) + return 0; + + if (month == DST_START_MONTH) { + + if (week < DST_START_WEEK) + return 0; + if (week > DST_START_WEEK) + return ONE_HOUR; + + if (day_of_week > SUNDAY) + return ONE_HOUR; + if (hour >= 2) + return ONE_HOUR; + return 0; + } + if (week > DST_END_WEEK) + return 0; + if (week < DST_END_WEEK) + return ONE_HOUR; + if (day_of_week > SUNDAY) + return 0; + if (hour >= 1) + return 0; + return ONE_HOUR; + + } + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o b/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o new file mode 100644 index 0000000000000000000000000000000000000000..31a9f51d0367ac54698c723a0a7692a17ed94602 Binary files /dev/null and b/hardware/tools/avr/avr/lib/avr25/crtat86rf401.o differ diff --git a/hardware/tools/avr/avr/lib/avr25/crtata5272.o b/hardware/tools/avr/avr/lib/avr25/crtata5272.o new file mode 100644 index 0000000000000000000000000000000000000000..c42926cefd24fb3855f9485b409f29c8c8bb1499 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